Multi-channel reference voltage generation circuit, analog-to-digital converter and receiver

Abstract

Embodiments of the present disclosure provide a multi-channel reference voltage generation circuit, an analog-to-digital converter using the multi-channel reference voltage generation circuit, and a receiver. The multi-channel reference voltage generation circuit includes a main stage circuit and a replica stage circuit. The main stage circuit includes a main stage reference voltage generation module and a main stage bias voltage filtering module. The main stage reference voltage generation module receives an input reference voltage and generates a first bias voltage and a second bias voltage. The replica stage circuit includes a plurality of replica stage reference voltage generation modules and a plurality of replica stage bias voltage filtering modules. Each replica stage reference voltage generation module receives the first bias voltage and the second bias voltage provided by the main stage circuit and outputs a replicated reference voltage, so that the replica stage circuit can output multiple reference voltages. The multi-channel reference voltage generation circuit of the present disclosure can replicate one reference voltage into multiple reference voltages, and at the same time can reduce the response time of the reference voltage of the sub-analog-to-digital converter.

Description

Technical Field

[0001] The present disclosure relates to high-speed communication, and more particularly, to a multi-channel reference voltage generation circuit, a time-interleaved analog-to-digital converter using the multi-channel reference voltage generation circuit, and a receiver. Background Art

[0002] With the increasing demand for high-speed communication in data centers, the communication rate of serial interfaces has been continuously improved, and the requirements for receiver performance have also become higher and higher. Traditional receivers based on analog structures are difficult to meet the needs of current high-data-rate applications. Therefore, new receivers based on high-speed time-interleaved analog-to-digital converters have gradually become the mainstream, which are generally used in high-speed communication systems of 10 Gbps and above.

[0003] A high-speed time-interleaved analog-to-digital converter works in cooperation with multiple sub-analog-to-digital converters to improve the overall sampling rate. Each sub-analog-to-digital converter samples the same analog signal at different time phases and compares it with a reference voltage to generate a corresponding digital code stream. Currently, the most advanced high-speed time-interleaved analog-to-digital converter solutions have adopted 64-channel or even 128-channel sub-analog-to-digital converters.

[0004] In this architecture, the existing sub-analog-to-digital converters use the same reference voltage. To avoid mutual interference between sub-analog-to-digital converters during the sampling process, an additional reference voltage buffer needs to be equipped for each sub-analog-to-digital converter to isolate the reference voltage it uses from the common reference voltage. This increases the design complexity and also brings an increase in power consumption and area. Summary of the Invention

[0005] In order to meet the requirements of sub-analog-to-digital converters for reference voltage, a reference voltage generation circuit needs to be designed, which can suppress the interference of the reference voltage during the sampling and comparison processes between sub-analog-to-digital converters on the basis of reducing power consumption and area consumption, and is easy to implement and manufacture.

[0006] In view of the problems existing in the prior art, embodiments of the present disclosure provide a multi-channel reference voltage generation circuit, a time-interleaved analog-to-digital converter using the multi-channel reference voltage generation circuit, and a receiver.

[0007] According to a first aspect of the present disclosure, a multi-channel reference voltage generation circuit is provided, which includes a primary circuit and a replica circuit. The primary circuit includes a primary reference voltage generation module and a primary bias voltage filtering module. The primary reference voltage generation module is configured to receive an input reference voltage and generate a first bias voltage and a second bias voltage. The primary bias voltage filtering module is connected to the first bias voltage and the second bias voltage to suppress external interference to the first bias voltage and the second bias voltage; the replica circuit includes a plurality of replica reference voltage generation modules and a plurality of replica bias voltage filtering modules. Each replica reference voltage generation module receives the first bias voltage and the second bias voltage sent by the primary circuit and outputs a replicated reference voltage, so that the replica circuit outputs a plurality of replicated reference voltages. Each replica bias voltage filtering module is connected to the first bias voltage and the second bias voltage to suppress external interference to the first bias voltage and the second bias voltage, and each replica reference voltage generation module includes a source follower with an open-loop structure, wherein the plurality of replicated reference voltages are the same as the input reference voltage. In addition, the primary reference voltage generation module may output a primary reference voltage, which is the same as the input reference voltage.

[0008] In the multi-channel reference voltage generation circuit of the embodiment of the present disclosure, by means of replicating the bias voltage through a source follower, each sub-analog-to-digital converter can generate an independent reference voltage, preventing interference to the reference voltage. By providing a bias voltage filtering module for the bias voltage, interference from the sub-analog-to-digital converter to the bias voltage is suppressed, and thus a replicated reference voltage with higher accuracy can be obtained.

[0009] Optionally, the primary reference voltage generation module includes an amplifier, whose non-inverting input terminal receives the input reference voltage, and the output terminal outputs the first bias voltage; a source follower, which receives the first bias voltage and outputs the primary reference voltage, the primary reference voltage being a replicated reference voltage, and the output primary reference voltage is input to the inverting input terminal of the amplifier. The above structure of the primary reference voltage generation module enables the amplifier to form a closed-loop control structure, ensuring that the primary reference voltage is the same as the input reference voltage.

[0010] Optionally, the source follower includes a first NMOS transistor (N-type metal-oxide-semiconductor field-effect transistor) and a second NMOS transistor. The gates of the first NMOS transistor and the second NMOS transistor are connected to the first bias voltage. The source of the second NMOS transistor is connected to the inverting input terminal of the amplifier and outputs a main-stage reference voltage. A first PMOS transistor (P-type metal-oxide-semiconductor field-effect transistor) and a second PMOS transistor. The source of the first PMOS transistor is connected to the source of the first NMOS transistor, and its gate and drain are connected together to generate a second bias voltage, and its drain is connected to a current source. The source of the second PMOS transistor is connected to the source of the second NMOS transistor, and its gate is connected to the gate of the first PMOS transistor.

[0011] With the above circuit structure, the main-stage reference voltage generation module of the present disclosure embodiment can generate stable first and second bias voltages.

[0012] Optionally, each replica-stage reference voltage generation module includes a third NMOS transistor and a third PMOS transistor. The gate of the third NMOS transistor is connected to the first bias voltage, its source is connected to the source of the third PMOS transistor and outputs a replicated reference voltage, and the gate of the third PMOS transistor is connected to the second bias voltage.

[0013] Each replica-stage reference voltage generation module of the present disclosure embodiment only needs one NMOS transistor and one PMOS transistor to generate an independent reference voltage, thus simplifying the circuit design and reducing power consumption and chip area. The first bias voltage and the second bias voltage can be respectively used to determine the DC operating points of the NMOS transistor and the PMOS transistor in the replica-stage reference voltage generation module, ensuring that the replica-stage reference voltage is the same as the main-stage reference voltage.

[0014] Optionally, the main-stage bias voltage filtering module includes first and second filtering capacitors respectively connected to the first and second bias voltages. The first and second filtering capacitors include a capacitor formed by a combination of a MOS (Metal-Oxide-Semiconductor) capacitor and a MOM (Metal-Oxide-Metal) capacitor. This way of constructing the capacitor can reduce the capacitor area. The filtering capacitor can also only use MOS capacitors or MOM capacitors, but this method will increase the area of the integrated circuit compared to using a combination of MOS and MOM capacitors.

[0015] Optionally, each of the multiple replica-stage bias voltage filtering modules includes third and fourth filtering capacitors respectively connected to the first and second bias voltages. The third and fourth filtering capacitors include a capacitor formed by a combination of a MOS capacitor and a MOM capacitor.

[0016] Optionally, the third and fourth filter capacitors are disposed on the layout of a device for receiving a plurality of replicated reference voltages generated by the multiple reference voltage generation circuit.

[0017] Optionally, the multiple reference voltage generation circuit further includes a first overvoltage protection circuit, which includes a first comparator, whose non-inverting input terminal is connected to a reference power supply voltage, and whose inverting input terminal is connected to a first bias voltage. The reference power supply voltage is less than the power supply voltage and is a certain proportion of the power supply voltage; a fourth PMOS transistor, whose gate is connected to the output terminal of the comparator, whose source is connected to the power supply voltage, and whose drain is connected to the drain of the second NMOS transistor; a fourth NMOS transistor, whose drain is connected to the drain of the second NMOS transistor, and whose gate is connected to the output terminal of the comparator. When the first bias voltage is lower than the reference power supply voltage, the fourth NMOS transistor is turned on and the fourth PMOS transistor is turned off.

[0018] Optionally, the multiple reference voltage generation circuit further includes a second overvoltage protection circuit, which includes a second comparator, whose non-inverting input terminal is connected to a reference power supply voltage, and whose inverting input terminal is connected to a first bias voltage. The reference power supply voltage is less than the power supply voltage and is a certain proportion of the power supply voltage; a fifth PMOS transistor, whose gate is connected to the output terminal of the comparator, whose source is connected to the power supply voltage, and whose drain is connected to the drain of the third NMOS transistor; a fifth NMOS transistor, whose drain is connected to the drain of the third NMOS transistor, and whose gate is connected to the output terminal of the comparator. When the first bias voltage is lower than the reference power supply voltage, the fifth NMOS transistor is turned on and the fifth PMOS transistor is turned off.

[0019] Optionally, the second NMOS transistor and the third NMOS transistor can use low-voltage MOS transistors. The fourth and fifth NMOS transistors can use high-voltage MOS transistors. The overvoltage protection circuit can enable the source follower to use MOS transistors with a lower threshold voltage, increase the adjustment range of the reference voltage, and prevent the gate-drain voltage and gate-source voltage of the NMOS transistor from exceeding the maximum voltage required by the process.

[0020] Optionally, the ratio of the reference power supply voltage to the power supply voltage is between 0.35 and 0.8, for example, about two-thirds of the power supply voltage.

[0021] The second aspect of the present disclosure provides a time-interleaved analog-to-digital converter, which includes: one or more levels of buffers for dividing an input high-speed data signal into multiple sub-data signals; a plurality of sub-analog-to-digital converters, each of which receives one of the multiple sub-data signals output by the one or more levels of buffers and performs analog-to-digital conversion on it; and the multi-channel reference voltage generation circuit as described above, which generates multiple replicated reference voltages for providing a separate reference voltage for each of the plurality of sub-analog-to-digital converters.

[0022] The third aspect of the present disclosure provides a receiver, which includes a terminal for matching the transmission line impedance, a continuous-time linear equalizer, a variable gain amplifier, the time-interleaved analog-to-digital converter as described above, and a digital backend.

[0023] Implementing any device of the present disclosure does not necessarily require achieving all of the above-described advantages simultaneously. Other features and advantages of the present disclosure will be described in the subsequent embodiments of the specification, and some of them will become obvious from the embodiments of the specification, or will be understood by implementing the present disclosure. The objectives and advantages of the embodiments of the present disclosure can be realized and obtained through the structures pointed out in the specification, claims, and drawings. Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0025] Figure 1 is a circuit block diagram of a multi-channel reference voltage generation circuit according to an embodiment of the present disclosure;

[0026] Figure 2 is a circuit schematic diagram of a multi-channel reference voltage generation circuit according to an embodiment of the present disclosure;

[0027] Figure 3 is a schematic diagram of an overvoltage protection circuit according to an embodiment of the present disclosure;

[0028] Figure 4 is a schematic structural diagram of an analog-to-digital converter using the multi-channel reference voltage generation circuit according to an embodiment of the present disclosure;

[0029] Figure 5 is a schematic structural diagram of a receiver using the multi-channel reference voltage generation circuit according to an embodiment of the present disclosure. Detailed Embodiments

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Various different embodiments can be combined with each other to form other embodiments not shown in the following description. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present disclosure.

[0031] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the specification and claims of the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, terms such as "a" or "an" do not necessarily denote a quantity limitation. Terms such as "comprising" or "including" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. Terms such as "connected" or "coupled" do not necessarily refer to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper", "lower", "left", and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0032] Figure 1 The circuit block diagram of a multi-channel reference voltage generation circuit according to an embodiment of the present disclosure is shown. The primary circuit includes a primary reference voltage generation module 101 and a primary bias voltage filtering module 102. The primary reference voltage generation module 101 receives the input of the reference voltage VREF, generates and sends a first bias voltage VNBIAS (representing the bias voltage of the NMOS) and a second bias voltage VPBIAS (representing the bias voltage of the PMOS) to the replica circuit. Additionally, the first bias voltage VNBIAS and the second bias voltage VPBIAS are connected to the primary bias voltage filtering module 102, which can be placed near the device receiving the multi-channel reference voltage, i.e., at its layout position for tight coupling, which may refer to the layout position of the sub-analog-to-digital converter in this embodiment, to suppress sampling noise. The primary reference voltage generation module 101 may include an amplifier feedback module and a source follower. The amplifier feedback module forms a closed-loop control to generate the first bias voltage VNBIAS. The source follower generates a primary reference voltage VREF0, which accurately replicates the reference voltage VREF and is transmitted to the amplifier feedback module. The amplifier feedback module enables the circuit to automatically adjust the first bias voltage to ensure the stability of the output primary reference voltage.

[0033] The replica stage circuit includes a plurality of replica stage reference voltage generation modules 111 and a plurality of replica stage bias voltage filtering modules 112. Each replica stage reference voltage generation module 111 includes a source follower with an open-loop structure, which is connected to a replica stage bias voltage filtering module 112. Each replica stage reference voltage generation module 111 receives a first bias voltage VNBIAS and a second bias voltage VPBIAS, and outputs a replicated reference voltage. Thus, N replica stage reference voltage generation modules 111 can output N reference voltages, namely VREF1 to VREFN.

[0034] The main stage bias voltage filtering module 102 and the replica stage bias voltage filtering module 112 can each include a filtering capacitor, which filters the first bias voltage VNBIAS and the second bias voltage VPBIAS to reduce the ripple and interference of the bias voltage. The bias voltage filtering module can be placed near the device receiving the reference voltage, such as at its layout position, so as to suppress the interference of the device on the bias voltage. For example, when using the reference voltage output by the replica stage circuit to drive a sub-analog-to-digital converter, the main stage circuit, the replica stage circuit, and the sub-analog-to-digital converter are closely coupled in sequence in the layout. If the output reference voltage of the main stage circuit is also used to drive the sub-analog-to-digital converter, it is also placed near the sub-analog-to-digital converter circuit similarly.

[0035] Figure 2More specifically, it shows the circuit structure of a multi-channel reference voltage generation circuit according to an embodiment of the present disclosure. In the main circuit, a single-channel reference voltage VREF is input to the non-inverting input terminal of the amplifier Amp1. The first bias voltage output by the amplifier is represented by VNBIAS, which is connected to the gates of NMOS M1 and NMOS M2. The source of NMOS M1 is connected to the source of PMOS M3, and the source of NMOS M2 is connected to the source of PMOS M4, forming a push-pull source follower structure. The source of NMOS M2 is connected to the inverting input terminal of the amplifier Amp1. The source voltage of NMOS M2 is the replicated main reference voltage VREF0. The gate and drain of PMOS M3 are connected together, and the second bias voltage here is represented by VPBIAS. The drain of PMOS M3 is connected to the common ground terminal via a current source, and the current source is used to provide a bias current for PMOS M3 to determine the DC operating point of PMOS M3. This DC operating point is also used for PMOS M4, PMOS M41 to PMOS M4N to ensure the stable operation of the MOS transistors. The drain of PMOS M4 is connected to the common ground terminal. The gate of PMOS M3 is connected to the gate of PMOS M4. The input-output connection mode of the amplifier Amp1 forms an amplifier feedback circuit, and the gate voltage of NMOS M2 is regulated through negative feedback. NMOS M1, NMOS M2, PMOS M1, and PMOS M2 form a push-pull source follower, which combines closed-loop control to ensure that the source voltage VREF0 accurately follows the input reference voltage VREF.

[0036] In the circuit of the replication stage 1, the gate of NMOS M21 is connected to the first bias voltage VNBIAS, and the source of NMOS M21 is connected to the source of PMOS M41, where the first-channel reference voltage VREF1 is replicated. The gate of PMOS M41 is connected to the second bias voltage. The circuits of other replication stages are the same as that of the replication stage 1. For example, the gate of NMOS M2N is connected to the first bias voltage VNBIAS, and the source of NMOS M2N is connected to the source of PMOS M4N, where the Nth-channel reference voltage VREFN is replicated. The gate of PMOS M4N is connected to the second bias voltage. Different from the main circuit, the reference voltages in the circuits of the replication stages 1 to N are in an open-loop configuration. The replicated multi-channel reference voltages VREF1 to VREFN are respectively provided for use by the sub-analog-to-digital converters 1 to the sub-analog-to-digital converters N.

[0037] When each sub - ADC uses a reference voltage to convert an input analog signal, there will be sampling noise, which affects the first bias voltage VNBIAS and the second bias voltage VPBIAS. Therefore, near the sub - ADC, to suppress the interference of sampling noise on the first bias voltage VNBIAS and the second bias voltage VPBIAS, the first and second bias voltages VNBIAS and VPBIAS are respectively connected to filter capacitors. In the main - stage circuit, the filter capacitor C11 is connected between the first bias voltage VNBIAS and the common ground terminal, and the filter capacitor C21 is connected between the second bias voltage VPBIAS and the common ground terminal. Specifically, one end of the filter capacitor C11 can be connected to the output terminal of the amplifier, and one end of the filter capacitor C2 can be connected between the gates of the PMOS M3 and the PMOS M4.

[0038] Similarly, each replica stage also has filter capacitors respectively connected between the first bias voltage VNBIAS and the second bias voltage VPBIAS and the common ground terminal. For example, for the sub - ADC N, at its corresponding layout position, the filter capacitors C1N and C2N are respectively connected between the first bias voltage VNBIAS and the second bias voltage VPBIAS and the common ground terminal. Thus, the filter capacitors C1, C11 to C1N are connected in parallel, and C2, C21 to C2N are connected in parallel. The main - stage circuit and each replica - stage circuit have the same bias voltage, ensuring the consistency of the circuit, avoiding output deviation, and being suitable for high - precision ADCs. To ensure the consistency of the circuit, the filter capacitors C1, C11 to C1N can use the same configuration, and the filter capacitors C2, C21 to C2N can use the same configuration.

[0039] Optionally, the filter capacitor can be composed of MOS capacitors and / or MOM capacitors. The capacitor composed of a combination of MOS capacitors and MOM capacitors can save chip area.

[0040] In the present disclosure, through the method of source - follower - replicated bias, each sub - ADC can generate a separate reference voltage, and this separate reference voltage can be generated only through one NMOS transistor and one PMOS transistor, greatly simplifying the circuit design of the sub - ADC and reducing the power consumption and area of the sub - ADC. The source - follower is not limited to the push - pull source - follower. For example, it can be replaced by an NMOS source - follower or a PMOS source - follower.

[0041] In an embodiment, when the power - supply voltage connected to the drains of M2, M21 to M2N is consistent with the process - required voltage of the NMOS transistor, these drains can be directly connected to the same power - supply voltage.

[0042] In another embodiment, in order to increase the voltage range of the reference voltage that the circuit can generate, MOS transistors with a low threshold voltage can be used. However, MOS transistors with a low threshold voltage generally can withstand lower gate-source voltage, gate-drain voltage, and source-drain voltage. At this time, the power supply voltage connected to the drain may be higher than the process requirement voltage of the MOS transistor, and an additional overvoltage protection circuit is required to ensure that the gate-source voltage and gate-drain voltage of the NMOS transistor do not exceed the process requirements. Figure 3 It is a schematic diagram of an overvoltage protection circuit. This circuit can be used for overvoltage protection of NMOS M2, NMOS M21 to NMOS M2N in the main stage and each replica stage circuit.

[0043] Taking NMOS M2 as an example, in the overvoltage protection circuit, the comparator COMP compares the magnitudes of the reference power supply voltage V1 and the first bias voltage VNBIAS. In Figure 3 the embodiment, the reference power supply voltage V1 and the first bias voltage VNBIAS are respectively connected to the non-inverting input terminal and the inverting input terminal. The output terminal of the comparator COMP is connected to the gate of the PMOS M5. The source of the PMOS M5 is connected to the power supply voltage VDDH, and its drain is connected to the drain of the NMOS M2. The gate of the NMOS M2 is connected to the inverting input terminal of the comparator COMP, that is, connected to the first bias voltage VNBIAS, and its drain is connected to the drain of another NMOS M6. The gate of the NMOS M6 is connected to the output of the comparator COMP, and its source is grounded. In this circuit, M5 and M6 can be high-voltage MOS transistors, and M2 can be a low-voltage MOS transistor. As used in this disclosure, a high-voltage MOS transistor has a higher threshold voltage than a low-voltage MOS transistor. For example, a high-voltage MOS transistor can refer to a MOS transistor with a gate drive voltage not lower than 1.2V, and a low-voltage MOS transistor can refer to a MOS transistor with a gate drive voltage not exceeding 0.75V.

[0044] The reference power supply voltage V1 is set to a value less than the power supply voltage VDDH. According to the general design method of MOS transistors, the reference power supply voltage V1 can be determined as a certain proportion of VDDH. Preferably, the ratio of the reference power supply voltage V1 to VDDH can be between 0.35 and 0.8. For example, it can be two-thirds of the magnitude of VDDH. This ratio can be determined according to the difference between VDDH and the first bias voltage. When the overvoltage protection circuit is operating, when the first bias voltage VNBIAS is higher than the reference power supply voltage V1, PD_HV becomes low level, PMOS M5 conducts, and NMOS M6 turns off. At this time, the circuit is in the normal operating state, and the gate-source voltage and gate-drain voltage of NMOS M2 are both a fixed proportion of the power supply voltage VDDH and will not exceed the process requirement value. When the first bias voltage VNBIAS is lower than the reference power supply voltage V1, PD_HV becomes high level, PMOS M5 turns off, and NMOS M6 conducts. At this time, the circuit is in the protection state to ensure that NMOS M2 will not be affected by the high level.

[0045] Optionally, the reference power supply voltage V1 is set to two-thirds of the power supply voltage VDDH so that when the first bias VNBIAS is greater than two-thirds of VDDH, the drain of NMOS M2 will be connected to the higher VDDH voltage, ensuring that the source-drain voltage of NMOS M2 will not exceed the process requirements. The ratio of the reference power supply voltage V1 to the power supply voltage VDDH can be set to other values less than 1 as needed.

[0046] The introduction of the overvoltage protection circuit enables the source follower to use MOS transistors with a lower threshold voltage, thereby expanding the adjustment range of the reference voltage. The above circuit is also applicable to the overvoltage protection of NMOS M21 to NMOS M2N.

[0047] By means of the source follower to copy the bias, multiple reference voltages can be accurately copied from one reference voltage, and at the same time, the response time of the reference voltage of the sub-analog-to-digital converter can be reduced. By setting filter capacitors in each sub-analog-to-digital converter, the interference to the reference voltage during the sampling and comparison processes between sub-analog-to-digital converters can be suppressed. Using the above overvoltage protection circuit, the gate-drain voltage and gate-source voltage of the source follower NMOS transistor can be prevented from exceeding the maximum voltage required by the process. The multi-reference voltage generation circuit of the embodiments of the present disclosure is also applicable to other circuit scenarios that require multiple reference voltages.

[0048] Figure 4A time-interleaved analog-to-digital converter according to an embodiment of the present disclosure is shown, which includes a multi-path reference voltage generation circuit according to an embodiment of the present disclosure. The analog-to-digital converter includes a multi-stage buffer, for example, it can be 1 to 3 stages, to divide a high-speed data signal into multiple paths, such as 8 paths, 16 paths, 32 paths, 64 paths, 128 paths, etc., and then through a sub-analog-to-digital converter, perform analog-to-digital conversion on the down-sampled data after being divided into multiple paths. Preferably, the high-speed data signal can be divided into 64 paths. Figure 4 The embodiment of Figure 4 shows a two-stage buffer that divides the high-speed data signal to sub-analog-to-digital converters 111 to sub-analog-to-digital converters NNN. The multi-path reference voltage generation circuit according to an embodiment of the present disclosure can generate replicated reference voltages for each path of the sub-analog-to-digital converter, preventing interference between multiple sub-analog-to-digital converters due to sharing the same reference voltage, thereby avoiding an adverse impact on the signal-to-noise ratio of the analog-to-digital converter.

[0049] The high-speed data in the embodiments of the present disclosure can be a data rate above 10 Gbps. For NRZ (Non-Return to Zero), the data rate is preferably above 10 Gbps, and more preferably 56 Gbps. For PAM4 (Four-Level Pulse Amplitude Modulation), the data rate is preferably at least 56 Gbps, and more preferably at least 112 Gbps.

[0050] Figure 5 A receiver 50 according to an embodiment of the present disclosure is shown, in which the analog-to-digital converter includes a multi-path reference voltage generation circuit according to an embodiment of the present disclosure. The receiver includes a terminal 51, a continuous time linear equalizer (CTLE) 52, a variable gain amplifier (VGA) 53, an analog-to-digital converter (ADC) 54, and a digital back end (DBE) 55. The terminal 51 is used to match the transmission line impedance, making the terminal load impedance match the transmission line impedance, thereby avoiding or reducing signal reflection and ensuring signal integrity. The terminal can adopt, for example, a differential terminal resistor.

[0051] The continuous time linear equalizer 52 enhances the high-frequency signal components through frequency-selective amplification, thereby reducing signal distortion. The variable gain amplifier 53 can dynamically adjust the gain of the signal, can adjust the gain according to the signal strength, and variably enhances the signal amplitude in frequency, so that the input signal reaches an appropriate level range in the subsequent analog-to-digital converter.

[0052] The analog-to-digital converter 54 converts the received equalized signal into a digital signal for subsequent digital signal processing. The analog-to-digital converter 54 is a time-interleaved analog-to-digital converter and has a multi-channel reference voltage generation circuit according to an embodiment of the present disclosure. A schematic structural diagram of the analog-to-digital converter 54 can be seen in Figure 4 .

[0053] The digital backend may include, but is not limited to, a feed-forward equalizer (FFE), a decision feedback equalizer (DFE), a clock data recovery module (CDR), and an adaptive equalizer to implement functions such as equalization, filtering, and symbol recovery. Here, a serializer / deserializer (SerDes) receiver may employ an existing digital signal processor as the digital backend.

[0054] The above is only an exemplary implementation manner of the present disclosure and is not used to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A multi-channel reference voltage generation circuit, characterized in that Comprising: A main - stage circuit, which includes a main - stage reference - voltage generation module and a main - stage bias - voltage filtering module. The main - stage reference - voltage generation module is used to receive an input reference voltage and generate a first bias voltage and a second bias voltage. The main - stage bias - voltage filtering module is connected to the first bias voltage and the second bias voltage to suppress external interference to the first bias voltage and the second bias voltage; A replication - stage circuit, which includes a plurality of replication - stage reference - voltage generation modules and a plurality of replication - stage bias - voltage filtering modules. Each replication - stage reference - voltage generation module receives the first bias voltage and the second bias voltage sent by the main - stage circuit and outputs a replicated reference voltage, so that the replication - stage circuit outputs a plurality of replicated reference voltages. Each replication - stage bias - voltage filtering module is connected to the first bias voltage and the second bias voltage to suppress external interference to the first bias voltage and the second bias voltage, and each replication - stage reference - voltage generation module includes a source - follower with an open - loop structure, which is connected to a replication - stage bias - voltage filtering module, wherein the plurality of replicated reference voltages are the same as the input reference voltage.

2. The multi-reference voltage generation circuit according to claim 1, wherein The main - stage reference - voltage generation module includes: An amplifier, whose non - inverting input terminal receives the input reference voltage and whose output terminal outputs the first bias voltage; A source - follower, which receives the first bias voltage and outputs a main - stage reference voltage. The main - stage reference voltage is a replicated reference voltage, and the output main - stage reference voltage is input to the inverting input terminal of the amplifier.

3. The multi-reference voltage generation circuit according to claim 2, wherein The source - follower includes: A first NMOS transistor and a second NMOS transistor. The gates of the first NMOS transistor and the second NMOS transistor are connected to the first bias voltage. The source of the second NMOS transistor is connected to the inverting input terminal of the amplifier and outputs the main - stage reference voltage; A first PMOS transistor and a second PMOS transistor. The source of the first PMOS transistor is connected to the source of the first NMOS transistor. Its gate and drain are connected together to generate the second bias voltage, and its drain is connected to a current source. The source of the second PMOS transistor is connected to the source of the second NMOS transistor. Its gate is connected to the gate of the first PMOS transistor, and its drain is connected to the common ground terminal.

4. The multi-reference voltage generation circuit according to claim 1, wherein Each of the replication - stage reference - voltage generation modules includes a third NMOS transistor and a third PMOS transistor, wherein the gate of the third NMOS transistor is connected to the first bias voltage, its source is connected to the source of the third PMOS transistor and outputs a replicated reference voltage, and the gate of the third PMOS transistor is connected to the second bias voltage, and its drain is connected to the common ground terminal.

5. The multi-reference voltage generation circuit according to claim 3, wherein It further includes a first over - voltage protection circuit, which includes: A first comparator, whose non - inverting input terminal is connected to a reference power - supply voltage, and whose inverting input terminal is connected to the first bias voltage. The reference power - supply voltage is less than the power - supply voltage; A fourth PMOS transistor, whose gate is connected to the output terminal of the comparator, whose source is connected to the power - supply voltage, and whose drain is connected to the drain of the second NMOS transistor; A fourth NMOS transistor, whose drain is connected to the drain of the second NMOS transistor, whose gate is connected to the output terminal of the comparator, and whose source is connected to the common ground terminal; When the first bias voltage is lower than the reference power supply voltage, the fourth NMOS transistor is turned on and the fourth PMOS transistor is turned off.

6. The multi-reference voltage generation circuit according to claim 4, wherein It further includes a second overvoltage protection circuit, which includes: A second comparator, whose non-inverting input terminal is connected to the reference power supply voltage, and whose inverting input terminal is connected to the first bias voltage, and the reference power supply voltage is less than the power supply voltage; A fifth PMOS transistor, whose gate is connected to the output terminal of the comparator, whose source is connected to the power supply voltage, and whose drain is connected to the drain of the third NMOS transistor; A fifth NMOS transistor, whose drain is connected to the drain of the third NMOS transistor, whose gate is connected to the output terminal of the comparator, and whose source is connected to the common ground terminal, When the first bias voltage is lower than the reference power supply voltage, the fifth NMOS transistor is turned on and the fifth PMOS transistor is turned off.

7. The multi-reference voltage generation circuit according to claim 5 or 6, characterized in that The ratio of the reference power supply voltage to the power supply voltage is between 0.35 and 0.

8.

8. The multi-reference voltage generation circuit according to claim 1, wherein The primary bias voltage filtering module includes first and second filtering capacitors respectively connected to the first and second bias voltages, and the first and second filtering capacitors include capacitors formed by a combination of MOS capacitors and MOM capacitors.

9. The multi-reference voltage generation circuit according to claim 1, wherein Each of the multiple replicated stage bias voltage filtering modules includes third and fourth filtering capacitors respectively connected to the first and second bias voltages, and the third and fourth filtering capacitors include capacitors formed by a combination of MOS capacitors and MOM capacitors.

10. The multi-reference voltage generation circuit according to claim 9, wherein The third and fourth filtering capacitors are placed on the layout of a device for receiving multiple replicated reference voltages generated by the multiple reference voltage generation circuit.

11. A time-interleaved analog-to-digital converter, which includes: One or more stages of buffers for dividing an input high-speed data signal into multiple sub-data signals; Multiple sub-analog-to-digital converters, each sub-analog-to-digital converter receives one of the multiple sub-data signals output by one or more stages of buffers and performs analog-to-digital conversion on it; The multiple reference voltage generation circuit according to any one of claims 1-10, which generates multiple replicated reference voltages for providing a separate reference voltage for each sub-module converter in multiple sub-analog-to-digital converters.

12. A receiver, which includes a terminal for matching the transmission line impedance, a continuous-time linear equalizer, a variable gain amplifier, the time-interleaved analog-to-digital converter according to claim 11, and a digital backend.

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