Circuit board, manufacturing method thereof and superconducting quantum computer

Abstract

The invention provides a circuit board, a manufacturing method thereof and a superconducting quantum computer, and belongs to the technical field of quantum information and circuit boards. The circuit board is used for carrying a superconducting quantum chip, and comprises a signal sub-board which comprises a superconducting line layer configured to transmit an electric signal of the superconducting quantum chip and two dielectric layers arranged at two sides of the superconducting line layer; the two shielding layers and the two heat conduction layers are sequentially arranged on the two sides of the signal daughter board, through metalized via holes are formed in the shielding layers, the dielectric layer and the superconducting line layer so that the shielding layers can be electrically connected with the superconducting line layer, and the superconducting line layer can be subjected to electromagnetic shielding through the shielding layers; the heat conduction layer conducts heat generated by the superconducting circuit layer to the outside through the metalized via hole, the dielectric layer and the shielding layer. The circuit board provided by the invention has relatively good anti-interference performance and a good heat dissipation effect.

Description

Technical Field

[0001] The present invention belongs to the field of quantum information and circuit boards, in particular to the field of superconducting quantum chip manufacturing and packaging. In particular, at least one embodiment of the present invention relates to a circuit board and a manufacturing method thereof, and a superconducting quantum computer. Background Art

[0002] In view of the sensitivity of superconducting quantum chips to environmental noise, superconducting quantum chips need to be physically protected and shielded from noise by packaging boxes. As the number of superconducting quantum bits in superconducting quantum chips increases, the number of signal lines required for packaging boxes also increases accordingly.

[0003] Typically, a common copper-clad printed circuit board (PCB) is used inside a package box to transmit signals. When electrical signals pass through the copper lines inside the package box, heat is generated, and as the number of lines increases, the heat accumulation problem becomes more and more serious.

[0004] At the same time, if the heat dissipation capacity of the packaging box is insufficient, the heat generated inside the packaging box cannot be dissipated in time, which will cause the temperature of the packaging box to rise.

[0005] If the total heat generated inside the packaging box is too high and the cooling capacity of the refrigerator is not enough to completely offset this heat, the temperature of all components in the MC (Mixing Chamber) layer of the refrigerator will also rise.

[0006] The above situation will cause the temperature of the superconducting quantum chip to increase, thereby reducing the fidelity of the 0 state (|0>) of the superconducting quantum bit. Summary of the invention

[0007] In view of this, in order to at least partially solve the above-mentioned technical problems, the present invention provides a circuit board and a manufacturing method thereof, and a superconducting quantum computer. The circuit board can transmit the electrical signals of the superconducting quantum chip while ensuring sufficient heat dissipation and having strong anti-interference performance.

[0008] According to an embodiment of one aspect of the present invention, a circuit board is provided for carrying a superconducting quantum chip, comprising: a signal sub-board, comprising a superconducting circuit layer configured to transmit electrical signals of the superconducting quantum chip, and two dielectric layers arranged on both sides of the superconducting circuit layer; and two shielding layers and two thermal conductive layers sequentially arranged on both sides of the signal sub-board, wherein the shielding layer, the dielectric layer and the superconducting circuit layer are formed with through metallized vias to electrically connect the shielding layer with the superconducting circuit layer, so that the shielding layer performs electromagnetic shielding on the superconducting circuit layer, and the thermal conductive layer conducts the heat generated by the superconducting circuit layer to the outside through the metallized vias, the dielectric layer and the shielding layer.

[0009] According to an embodiment of another aspect of the present invention, there is provided a method for manufacturing the above-mentioned circuit board, comprising: providing a first circuit sub-board, wherein the first circuit sub-board comprises a first dielectric layer, and a first superconducting plate layer and a first shielding layer respectively located on both sides of the first dielectric layer, and a first heat-conducting layer is arranged on the surface of the first shielding layer, and the first shielding layer is electrically connected to the first superconducting plate layer through a first metallized via hole, wherein the first superconducting plate layer comprises at least one signal line, and a first ground plane symmetrically arranged on both sides of the signal line along a first direction of the signal line; providing a second circuit sub-board, wherein the second circuit sub-board comprises a second dielectric layer, and a second superconducting plate layer and a second shielding layer respectively located on both sides of the second dielectric layer, and a second heat-conducting layer is arranged on the surface of the second shielding layer, and the second shielding layer is electrically connected to the second superconducting plate layer through a second metallized via hole, wherein the second superconducting plate layer comprises at least one strip groove arranged through, and a second ground plane symmetrically arranged on both sides of the strip groove along the first direction of the strip groove; and aligning and welding the first circuit sub-board and the second circuit sub-board so that the signal line is embedded in the strip groove, and the first ground plane and the second ground plane are electrically connected.

[0010] According to another embodiment of the present invention, there is provided a superconducting quantum computer, comprising the above-mentioned circuit board; and a superconducting quantum chip, wherein the superconducting quantum chip is mounted on the above-mentioned circuit board.

[0011] According to the circuit board for carrying a superconducting quantum chip provided by the above embodiment of the present invention, a superconducting circuit layer for transmitting electrical signals is made of superconducting material. Since the superconducting material has low resistance and low heat generation in the superconducting state, the heat generation of the superconducting circuit layer can be reduced.

[0012] According to the circuit board for carrying a superconducting quantum chip provided by the above embodiment of the present invention, the superconducting circuit layer is electromagnetically shielded by shielding layers located on both sides of the superconducting circuit layer to shield interference signals, so that the circuit board has better anti-interference performance and can transmit electrical signals with higher quality.

[0013] According to the circuit board for carrying a superconducting quantum chip provided by the above embodiment of the present invention, the use of metallized vias and shielding layers is beneficial to enhancing the heat dissipation of the superconducting circuit layer to achieve a better heat dissipation effect, thereby preventing the problem of reduced bit fidelity and chip failure caused by heat accumulation.

[0014] According to the circuit board for carrying a superconducting quantum chip provided by the above embodiment of the present invention, the shielding layer and the metallized vias are used to increase the isolation between signal lines, thereby reducing the crosstalk between the signal lines.

[0015] According to the circuit board for carrying a superconducting quantum chip provided by the above embodiment of the present invention, the circuit board uses a ceramic material to make a dielectric layer. Since the ceramic material has a high thermal conductivity, it is beneficial to conduct the heat generated by the superconducting circuit layer, which is beneficial to the heat dissipation of the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0017] Figure 1 A schematic diagram of the isometric structure of a circuit board provided in an embodiment of the present invention;

[0018] Figure 2 A schematic cross-sectional view of a circuit board provided in an embodiment of the present invention;

[0019] Figure 3 A schematic diagram of a process flow of a method for manufacturing a circuit board provided by an embodiment of the present invention;

[0020] Figure 4 A schematic diagram of the isometric structure of a first circuit sub-board provided in an embodiment of the present invention;

[0021] Figure 5 for Figure 4 A cross-sectional schematic diagram of the first circuit sub-board shown;

[0022] Figure 6 A schematic diagram of the isometric structure of a second circuit sub-board provided in an embodiment of the present invention;

[0023] Figure 7 for Figure 6 A cross-sectional schematic diagram of the second circuit sub-board shown;

[0024] Figure 8 A schematic diagram of a process flow for manufacturing a first metallized via provided by an embodiment of the present invention;

[0025] Fig. 9 A schematic diagram of an isometric structure of a first dielectric layer having a first metallized via provided in an embodiment of the present invention;

[0026] Fig.10 for Fig. 9 A schematic cross-sectional view of a first dielectric layer having a first metallized via hole formed therein;

[0027] Fig.11 A schematic diagram of an axonometric structure of etching a first superconducting plate layer on a first dielectric layer to form a signal line and a first ground plane provided by an embodiment of the present invention;

[0028] Fig.12 for Fig.11 A schematic cross-sectional view of the components shown;

[0029] Fig.13 A schematic diagram of an axonometric structure of a first heat-conducting layer disposed on a first shielding layer provided in an embodiment of the present invention;

[0030] Fig.14 A schematic diagram of a structure for manufacturing a first solder joint on the surface of a first metallized via hole provided by an embodiment of the present invention;

[0031] Fig.15 A schematic diagram of a structure for manufacturing a second solder joint on the surface of a second metallized via hole provided by an embodiment of the present invention;

[0032] Fig.16 A schematic diagram of a structure in which a first circuit sub-board and a second circuit sub-board are aligned and welded together according to an embodiment of the present invention;

[0033] Fig.17 A cross-sectional schematic diagram of the first circuit sub-board and the second circuit sub-board being aligned and welded according to an embodiment of the present invention; and

[0034] Fig.18 It is a comparison chart of the crosstalk simulation calculation results between the signal lines of the circuit boards provided in comparative example 1 and embodiment 1 of the present invention.

[0035] Description of reference numerals:

[0036] 100-circuit board;

[0037] 1011- first heat conducting layer;

[0038] 1012- first shielding layer;

[0039] 1021- second heat conducting layer;

[0040] 1022- second shielding layer;

[0041] 200-Signal daughter board;

[0042] 201- first dielectric layer;

[0043] 202- second dielectric layer;

[0044] 203-superconducting circuit layer;

[0045] 2031-first superconducting plate layer;

[0046] 2032- second superconducting plate layer;

[0047] 2033-Signal line;

[0048] 2034-First ground plane;

[0049] 2035-strip groove;

[0050] 2036-Second ground plane;

[0051] 204-first solder resist layer;

[0052] 205- second solder resist layer;

[0053] 11- first circuit sub-board;

[0054] 111-first metallized via hole;

[0055] 22-a second circuit sub-board;

[0056] 112-second metallized via;

[0057] 113-first soldering point;

[0058] 114-Second soldering point. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical scheme and advantages of the present invention more clear, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the invention thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, for clarity, the sizes and relative sizes of layers and regions may be exaggerated, and the same reference numerals throughout represent the same elements.

[0060] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0061] Printed Circuit Board (PCB) is an important component of electronic devices. In terms of functions, PCB mainly realizes electrical connection, mechanical support, signal transmission and heat dissipation.

[0062] Electrical connection refers to connecting various electronic components together according to design requirements to form a complete circuit, thereby ensuring that current can be transmitted smoothly between various components and realize various functions of electronic equipment.

[0063] The mechanical support provides a fixed foundation and support for electronic components, so that various electronic components can maintain the correct position, orientation, and posture on the circuit board to ensure the stability and reliability of electronic equipment.

[0064] Signal transmission refers to the transmission and processing of signals to ensure the integrity and accuracy of signals and reduce signal interference and attenuation. Heat dissipation can dissipate the heat generated by electronic components to ensure the normal operation of electronic equipment.

[0065] In the related art, the basic structure of a PCB usually mainly includes an insulating substrate, conductive circuits, pads, etc.

[0066] The insulating substrate is usually made of materials such as glass fiber and epoxy resin, and therefore has good insulation properties and mechanical strength, thereby providing physical support for the circuit.

[0067] The conductive circuit can be formed on the insulating substrate through micro-nano processing such as coating and etching, and can usually be realized in the form of copper foil circuit. The conductive circuit is used to connect various electronic components to realize the transmission of current or signal.

[0068] The pads are used to weld the metal areas of the pins of electronic components, providing electrical connection points for the components.

[0069] As an electronic device, PCB is also used in superconducting quantum chips, and due to the particularity of superconducting quantum chips (sensitivity to environmental noise, physical realization, etc.), higher requirements are placed on PCB. For example, superconducting quantum chips are sensitive to temperature. Excessive temperature will cause superconducting circuits to lose superconductivity, which will significantly reduce the fidelity of superconducting quantum bits, and may make superconducting quantum chips unable to work properly. In addition, various noise signals will interfere with the normal reading and control of superconducting quantum bits, thereby affecting normal quantum computing.

[0070] Therefore, when the superconducting quantum chip is mounted on the PCB, it is hoped that the circuit board has good performance in the above aspects. However, the current PCB has many problems in use, such as high heat generation, weak heat dissipation, poor anti-interference, etc.

[0071] In view of this, after research, the present invention proposes a circuit board and a manufacturing method thereof, and a superconducting quantum computer. The circuit board uses superconducting materials to transmit signals, and is also configured with materials that enhance thermal conductivity, thereby taking into account the thermal design and electromagnetic design required for the superconducting quantum chip during the packaging process. It should be noted that the circuit board provided by the present invention is not limited to being applied to superconducting quantum chips, but can also be applied to conventional chips, classical chips or semiconductor chips, or other electronic devices.

[0072] Figure 1 A schematic diagram of the isometric structure of a circuit board provided in an embodiment of the present invention.

[0073] Figure 2 A schematic cross-sectional view of a circuit board provided in an embodiment of the present invention.

[0074] According to an exemplary embodiment of the present invention, the present invention provides a circuit board for carrying a superconducting quantum chip, referring to Figure 1 , Figure 2 As shown, the circuit board 100 includes:

[0075] The signal sub-board 200 includes a superconducting circuit layer 203 configured to transmit the electrical signal of the superconducting quantum chip, and two dielectric layers arranged on both sides of the superconducting circuit layer 203; and

[0076] Two shielding layers and two thermally conductive layers are sequentially arranged on both sides of the signal sub-board 200. The shielding layer, the dielectric layer and the superconducting circuit layer are formed with through metallized vias to electrically connect the shielding layer with the superconducting circuit layer 203, so that the shielding layer can electromagnetically shield the superconducting circuit layer 203. The thermally conductive layer conducts the heat generated by the superconducting circuit layer 203 to the outside through the metallized vias, the dielectric layer and the shielding layer.

[0077] In the embodiment of the present invention, the signal sub-board 200 includes a first dielectric layer 201, a second dielectric layer 202, and a superconducting circuit layer 203 located between the first dielectric layer 201 and the second dielectric layer 202. The first dielectric layer 201 and the second dielectric layer 202 clamp the superconducting circuit layer 203 inside, and can provide physical protection for the superconducting circuit layer 203.

[0078] In an embodiment of the present invention, the circuit board 100 includes a first shielding layer 1012 and a first thermal conductive layer 1011 which are arranged on the first side of the signal sub-board 200 and stacked in sequence, and the first shielding layer 1012 covers the first dielectric layer 201, and the first shielding layer 1012 is electrically connected to the superconducting circuit layer 203 through a first metallized via penetrating the first dielectric layer 201.

[0079] In an embodiment of the present invention, the circuit board 100 includes a second shielding layer 1022 and a second thermal conductive layer 1021 which are arranged on the second side of the signal sub-board 200 and stacked in sequence, and the second shielding layer 1022 covers the second dielectric layer 202, and the second shielding layer 1022 is electrically connected to the superconducting circuit layer 203 through a second metallized via penetrating the second dielectric layer 202.

[0080] In the embodiment of the present invention, the first shielding layer 1012 and the second shielding layer 1022 perform electromagnetic shielding on the superconducting circuit layer 203, that is, shielding of interfering electrical signals can be achieved, which can improve signal transmission quality and reduce interference. In addition, the first shielding layer 1012 and the second shielding layer 1022 can also be used as a path for signal return flow, playing a role in signal return flow.

[0081] In the embodiment of the present invention, the first shielding layer 1012 and the second shielding layer 1022 can be made of superconducting materials, which is conducive to achieving a better electromagnetic shielding effect. The shielding layers made of superconducting materials located on both sides of the superconducting circuit layer 203 perform electromagnetic shielding on the superconducting circuit layer 203, which can shield external interference signals, so that the circuit board has better anti-interference performance, thereby improving the transmission quality of electrical signals.

[0082] In some embodiments, the first shielding layer 1012 , the second shielding layer 1022 , and the superconducting circuit layer 203 may be made of the same material.

[0083] It should be noted that the material of the first dielectric layer 201 and the material of the second dielectric layer 202 may be the same or different.

[0084] In some embodiments, the materials of the first dielectric layer 201 and the second dielectric layer 202 may be organic materials, such as organic resins, which may be epoxy resins, polyimide or polytetrafluoroethylene. The thickness of the first dielectric layer 201 and the second dielectric layer 202 is not specifically limited here and can be adjusted according to the actual use scenario and requirements of the circuit board 100.

[0085] In some embodiments, the first dielectric layer 201 and the second dielectric layer 202 can be ceramic layers, respectively. The first dielectric layer 201 and the second dielectric layer 202 are preferably made of ceramic materials. Since the thermal conductivity of ceramic materials is high, it is more conducive to conducting the heat generated by the superconducting circuit layer 203, thereby facilitating the heat dissipation of the circuit board 100. In addition, compared with the first dielectric layer 201 and the second dielectric layer 202 formed by organic resin, the dielectric loss of the first dielectric layer 202 and the second dielectric layer 203 made of ceramic materials is low, which is also conducive to reducing signal insertion loss.

[0086] In the embodiments of the present invention, the ceramic material includes but is not limited to aluminum oxide, silicon oxide, silicon nitride, zirconium oxide, aluminum nitride, beryllium oxide, silicon carbide, magnesium oxide, zirconium-doped Al2O3. Based on some classifications, the ceramic material used can be high temperature co-fired ceramic (HTCC) or low temperature co-fired ceramic (LTCC).

[0087] In some embodiments, the superconducting circuit layer 203 is made of a superconducting material with a high melting point (melting point greater than 600° C.), and the superconducting material includes aluminum, tantalum, tantalum nitride, titanium nitride or niobium. The use of a superconducting material with a high melting point is more conducive to manufacturing a circuit board with higher circuit accuracy and better flatness.

[0088] In some embodiments, the signal line 2033 in the superconducting circuit layer 203 may have different structural forms. For example, the superconducting circuit layer 203 includes at least one signal line 2033 and a ground plane ( Figure 1 and Figure 2 Not marked). In some examples, the superconducting circuit layer can be realized in the form of a coplanar waveguide transmission line. Therefore, the signal line 2033 can be a central conductor of the coplanar waveguide, and a ground plane is symmetrically distributed along the first direction of the central conductor (the length direction of the central conductor), and there is a gap between the central conductor and the ground plane, for example, it can be a spacer of a vacuum or air medium.

[0089] In some embodiments, the superconducting circuit layer 203 may include a single-layer superconducting plate layer. The single-layer superconducting plate layer includes at least one signal line 2033, and ground planes symmetrically arranged on both sides of the signal line 2033 along a first direction of the signal line 2033 (the first direction is the length direction of the signal line 2033), wherein the signal line 2033 and the ground plane are located in the same plane. In other words, the signal line 2033 is formed by a single-layer superconducting plate layer, and the ground plane is also formed by a single-layer superconducting plate layer.

[0090] In some embodiments, the superconducting circuit layer 203 may be composed of multiple layers of superconducting plate layers. For example, the number of superconducting plate layers may be 2, 3, 4, or 5, but is not limited to the above values.

[0091] In some embodiments, reference Figure 2 As shown, the superconducting circuit layer 203 may include a first superconducting plate layer 2031 and a second superconducting plate layer 2032 that are stacked and welded.

[0092] In the embodiment of the present invention, the signal line 2033 is formed by the first superconducting plate layer 2031 , and the ground plane is formed by the first superconducting plate layer 2031 and the second superconducting plate layer 2032 .

[0093] In some embodiments, the first superconducting plate layer 2031 is used to form a signal line 2033 and a first ground plane symmetrically arranged on both sides of the signal line 2033 along a first direction of the signal line 2033 (the first direction is the length direction of the signal line 2033), wherein the signal line 2033 and the first ground plane are located in the same plane.

[0094] In the embodiment of the present invention, the second superconducting plate layer 2032 has at least one strip groove extending therethrough and second ground planes symmetrically arranged on both sides of the strip groove along a first direction of the strip groove, and the second ground plane is welded to the first ground plane to form a ground plane.

[0095] In the embodiment of the present invention, the orthographic projection of the signal line 2033 on the first dielectric layer 201 is in the shape of a rectangle, and the orthographic projection of the strip groove on the first dielectric layer 201 is in the shape of a rectangle. The orthographic projection of the signal line 2033 on the first dielectric layer 201 is located within the orthographic projection region of the strip groove on the first dielectric layer 201.

[0096] That is, the width of the strip groove 404 along the second direction perpendicular to the first direction is greater than the width of the signal line 2033 along the second direction, and the projection of the center line of the signal line 2033 along the first direction on the first dielectric layer 201 is aligned with the projection of the center line of the strip groove 404 along the first direction on the first dielectric layer 201 to embed the signal line 2033 into the strip groove.

[0097] In some embodiments, the signal line 2033 may be formed by the first superconducting slab layer 2031 and the second superconducting slab layer 2032 , and the ground plane may be formed by the first superconducting slab layer 2031 and the second superconducting slab layer 2032 .

[0098] In an embodiment of the present invention, the ground planes provided by the multiple layers of superconducting plate layers can be connected by welding. Based on heat transfer considerations, the welding material can be selected from materials with a large thermal conductivity. And based on signal return considerations, in some examples, the welding material is conductive or can transmit electrical signals so that the ground planes of each layer are conductively connected.

[0099] In some embodiments, the solder material may be selected to be tin.

[0100] In some embodiments, the solder material may be a metal or alloy with a low melting point, such as a metal or alloy with a melting point below 300° C. For example, the solder material may be indium metal, tin-lead alloy, or tin-bismuth alloy.

[0101] In some embodiments, when the first dielectric layer 201 and the second dielectric layer 202 are made of ceramic materials, since ceramic materials have strong high temperature resistance, metals with higher temperatures, such as aluminum (melting point 660° C.), can be used as welding materials.

[0102] In some embodiments, the first heat-conducting layer 1011 and the second heat-conducting layer 1021 are constructed of the same material or different materials. The first heat-conducting layer 1011 and / or the second heat-conducting layer 1021 can be a non-metallic material. In some embodiments, the first heat-conducting layer 1011 and the second heat-conducting layer 1021 are preferably copper layers to achieve better thermal conductivity.

[0103] In some embodiments, the first metallized via 111 and the second metallized via 112 may be non-metallic columns or metal columns (such as copper columns). Considering the manufacturing of the metallized via, it may be further constructed as a multi-layer structure, such as multiple concentric columns. In the example, copper columns are selected because the process is relatively easier to implement.

[0104] In the embodiment of the present invention, the first shielding layer 1012 and the first heat-conducting layer 1011 can be in contact with each other to achieve heat transfer, and at the same time, the first metallized via 111 can also transfer the heat generated by the superconducting circuit layer 203 to the first heat-conducting layer 1011, and then conduct the heat out through the first heat-conducting layer 1011. The second shielding layer 1022 and the second heat-conducting layer 1021 can be in contact with each other to achieve heat transfer, and at the same time, the second metallized via 112 can also transfer the heat generated by the superconducting circuit layer 203 to the second heat-conducting layer 1021, and then conduct the heat out through the second heat-conducting layer 1021. In addition to being able to connect the ground plane for signal backflow and heat dissipation, the first metallized via 111 and the second metallized via 112 can also play a positive role in the isolation between the lines. Specifically, the metal vias between the signal lines weaken the electromagnetic interaction between adjacent signal lines, and the weaker the interaction, the higher the isolation. The use of a shielding layer and metalized vias increases the isolation between signal lines, thereby reducing crosstalk between signal lines.

[0105] In an embodiment of the present invention, the superconducting quantum chip can be packaged in a packaging box, and the first heat-conducting layer 1011 and the second heat-conducting layer 1021 of the circuit board carrying the superconducting quantum chip can be respectively connected to a heat sink (used to absorb and dissipate heat; conduct heat from a heat source such as an electronic component, and dissipate heat to the surrounding environment by increasing the surface area) in the packaging box to dissipate heat.

[0106] According to an exemplary embodiment of the present invention, the present invention provides a superconducting quantum computer, comprising the above-mentioned circuit board; and a superconducting quantum chip, wherein the superconducting quantum chip is mounted on the above-mentioned circuit board.

[0107] Figure 3 A schematic flow chart of a method for manufacturing a circuit board provided in an embodiment of the present invention.

[0108] According to an exemplary embodiment of the present invention, the present invention provides a method for manufacturing a circuit board, referring to Figure 3 As shown, it includes: operation S1 to operation S3.

[0109] In operation S1 , a first circuit sub-board 11 is provided.

[0110] Figure 4A schematic diagram of the isometric structure of a first circuit sub-board provided in an embodiment of the present invention.

[0111] Figure 5 for Figure 4 A cross-sectional schematic diagram of the first circuit sub-board is shown.

[0112] In some embodiments, reference Figure 4 , Figure 5 As shown, the first circuit sub-board 11 includes a first dielectric layer 201, and a first superconducting plate layer 2031 and a first shielding layer 1012 respectively located on both sides of the first dielectric layer 201, the first shielding layer 1012 is electrically connected to the first superconducting plate layer 2031 through a first metallized via 111, and a first thermal conductive layer 1011 is arranged on the surface of the first shielding layer 1012, wherein the first superconducting plate layer 2031 includes at least one signal line 2033, and a first ground plane 2034 symmetrically arranged on both sides of the signal line 2033 along a first direction of the signal line 2033.

[0113] refer to Figure 5 As shown, two ends of the first metallized via 111 are electrically connected to the first shielding layer 1012 and the first ground plane 2034 of the first superconducting plate layer 2031 respectively.

[0114] In operation S2, a second circuit sub-board 22 is provided.

[0115] Figure 6 This is a schematic diagram of the isometric structure of the second circuit sub-board provided in an embodiment of the present invention.

[0116] Figure 7 for Figure 6 A cross-sectional schematic diagram of the second circuit daughter board is shown.

[0117] In some embodiments, reference Figure 6 , Figure 7 As shown, the second circuit sub-board 22 includes a second dielectric layer 202 and a second superconducting plate layer 2032 and a second shielding layer 1022 respectively located on both sides of the second dielectric layer 202, the second shielding layer 1022 is electrically connected to the second superconducting plate layer 2032 through a second metallized via 112, and the second shielding layer 1021 is covered on the second shielding layer 1022, wherein the second superconducting plate layer 2032 includes at least one strip groove 2035 and a second ground plane 2036 symmetrically arranged on both sides of the strip groove 2035 along a first direction of the strip groove 2035.

[0118] refer to Figure 7 As shown, two ends of the second metallized via 112 are electrically connected to the second shielding layer 1022 and the second ground plane 2036 of the second superconducting plate layer 2032 respectively.

[0119] It should be noted that operation S1 and operation S2 can be performed simultaneously or sequentially, and the specific order is not particularly limited.

[0120] In operation S3 , the first circuit sub-board 11 and the second circuit sub-board 22 are aligned and welded so that the signal line 2033 is embedded in the strip groove 2035 , and the first ground plane 2034 and the second ground plane 2036 are electrically connected.

[0121] In the embodiment of the present invention, the orthographic projection of the signal line 2033 on the first dielectric layer 201 is located within the orthographic projection area of ​​the strip groove 2035 on the first dielectric layer 201, so that the signal line 2033 is embedded in the strip groove 2035. In addition, the first ground plane 2034 and the second ground plane 2036 are electrically connected to form a ground plane.

[0122] In the embodiment of the present invention, by manufacturing the first circuit sub-board and the second circuit sub-board separately and aligning and welding the first circuit sub-board and the second circuit sub-board, the difficulty of manufacturing the circuit board can be reduced. In addition, the problem of mismatch between layers due to inter-layer alignment errors or accumulation of errors that may exist when the circuit board is manufactured layer by layer can be solved.

[0123] Figure 8 A schematic diagram of a process flow for manufacturing a first metallized via provided in an embodiment of the present invention.

[0124] Fig. 9 A schematic diagram of the isometric structure of a first dielectric layer having a first metallized via provided in an embodiment of the present invention.

[0125] Fig.10 for Fig. 9 The cross-sectional schematic diagram of the first dielectric layer formed with the first metallized via is shown.

[0126] In the embodiments of the present invention, reference Figure 8 , Fig. 9 , Fig.10 As shown, the process flow of manufacturing the first metallized via 111 on the first dielectric layer 201 includes steps S10 to S40.

[0127] Step S10 , forming metal layers on the first surface of the first dielectric layer 201 and on a second surface opposite to the first surface.

[0128] In some embodiments, the metal layer may be, for example, a copper layer.

[0129] In some embodiments, the metal copper layer is deposited on the first surface and the second surface opposite to the first surface of the first dielectric layer 201 by electron beam evaporation or magnetron sputtering. The thickness of the metal copper layer may be 30 μm, for example.

[0130] Step S20 , forming a plurality of first through holes penetrating the first dielectric layer 201 .

[0131] In the embodiment of the present invention, laser is used to drill holes at preset positions of the first dielectric layer 201 to form a plurality of first through holes penetrating the first dielectric layer 201 . The aperture of the first through holes may be, for example, 0.1 mm.

[0132] Step S30 , depositing metal on the sidewall of the first through hole so that the metal in the first through hole is flush with the metal layer.

[0133] In the embodiment of the present invention, copper metal is deposited on the sidewall of the first through hole by copper electroplating, so that the copper metal in the first through hole is connected to the metal layers on both sides of the first dielectric layer 201 and is flush with the metal layers.

[0134] Step S40 , etching the metal layer on the first dielectric layer 201 so that the area of ​​the metal layer corresponding to the first through hole is retained and the remaining area of ​​the metal layer is removed to form a first metallized via hole 111 penetrating the first dielectric layer 201 .

[0135] In an embodiment of the present invention, photosensitive ink or photoresist is coated on one of the metal layers on the first dielectric layer 201, the designed area is exposed using a photomask and ultraviolet exposure, and then the metal layer is etched to leave only the area of ​​the metal layer corresponding to the first through hole. The area of ​​the metal layer corresponding to the first through hole is circular, and the diameter of the circle is larger than the aperture of the first through hole. The diameter of the circle is, for example, 0.3 mm.

[0136] In some embodiments, the preparation process of the first metallized via 111 and the preparation process of the second metallized via 112 may be the same.

[0137] Fig.11 A schematic diagram of an axonometric structure of etching a first superconducting plate layer on a first dielectric layer to form a signal line and a first ground plane provided in an embodiment of the present invention.

[0138] Fig.12 for Fig.11 Schematic cross-section of the components shown.

[0139] refer to Fig.11 , Fig.12 As shown, a first superconducting plate layer 2031 and a first shielding layer 1012 are formed on both sides of the first dielectric layer 201. Then, the first superconducting plate layer 2031 is etched to form at least one signal line 2033 and a first ground plane 2034.

[0140] In some embodiments, superconducting materials are deposited on both sides of the first dielectric layer 201 by atomic layer deposition, magnetron sputtering or electron beam evaporation to form the first superconducting plate layer 2031 and the first shielding layer 1012 .

[0141] In an embodiment of the present invention, before depositing the first superconducting plate layer 2031 and the first shielding layer 1012 , argon ion cleaning may be used to in-situ remove the oxide layer on the surface of the first metallized via 111 to reduce the contact resistance between the superconducting material and the first metallized via 111 .

[0142] In some embodiments, photosensitive ink or photoresist is coated on the first superconducting plate layer 2031 , and the designed circuit area is exposed by using a photomask and ultraviolet exposure, and then the first superconducting plate layer 2031 is etched to form at least one signal line 2033 and a first ground plane 2034 .

[0143] In some embodiments, the first superconducting plate layer 2031 is wet-etched, and the selectivity of the etching solution and the first metallized via 111 is controlled to avoid etching away the metal of the first metallized via 111. Exemplarily, when the superconducting material is aluminum, an alkaline etching solution that does not react with the metal of the first metallized via 111 (e.g., copper metal) can be used for etching, such as sodium hydroxide, potassium hydroxide, or tetramethylammonium hydroxide (TMAH).

[0144] In some embodiments, the first superconducting plate layer 2031 is etched by dry etching. In addition to improving the selectivity, the etching depth can also be controlled by the process until the etching reaches the first metallized via hole 111 and the etching is stopped.

[0145] Fig.13 A schematic diagram of an axonometric structure in which a first heat-conducting layer is disposed on a first shielding layer according to an embodiment of the present invention.

[0146] refer to Fig.13 As shown, a first heat conducting layer 1011 is deposited on the first shielding layer 1012 by magnetron sputtering or electron beam coating. The first heat conducting layer 1011 may be a metal copper layer, and the first heat conducting layer 1011 is directly connected to the first metallized via 111, which can enhance the heat dissipation capacity of the circuit board.

[0147] Fig.14 A schematic diagram of the structure of manufacturing a first solder joint on the surface of a first metallized via hole provided in an embodiment of the present invention.

[0148] Fig.15 A schematic diagram of the structure of manufacturing a second solder joint on the surface of a second metallized via hole provided by an embodiment of the present invention.

[0149] Fig.16A schematic structural diagram of a first circuit sub-board and a second circuit sub-board provided in an embodiment of the present invention being aligned and welded.

[0150] Fig.17 A cross-sectional schematic diagram of a first circuit sub-board and a second circuit sub-board being aligned and welded according to an embodiment of the present invention.

[0151] In the embodiments of the present invention, reference Fig.14 As shown, a first soldering point 113 is provided at one end of the first metallized via 111 close to the first superconducting plate layer 2031 .

[0152] In some embodiments, the first solder joint 113 may be manufactured on the surface of the first metallized via 111 by using a fixed-point laser ball implantation method or a screen ball implantation method.

[0153] In some embodiments, the first solder joint 113 may be manufactured on the surface of the first metallized via 111 by coating solder paste on a screen or spraying tin on the screen.

[0154] In the embodiments of the present invention, reference Fig.15 As shown, a second soldering point 114 is provided at one end of the second metallized via 112 close to the second superconducting plate layer 2032 .

[0155] In the embodiment of the present invention, aligning and welding the first circuit sub-board 11 and the second circuit sub-board 22 includes welding the first soldering point 113 and the second soldering point 114 .

[0156] In some embodiments, before the first circuit sub-board 11 and the second circuit sub-board 22 are aligned and welded, a first solder resist layer 204 is disposed on a non-welding point area of ​​the first superconducting plate layer 2031 away from the surface of the first dielectric layer 201 , so that the first solder joint 113 located on the first metallized via 111 is easier to form.

[0157] In some embodiments, before the first circuit sub-board 11 and the second circuit sub-board 22 are aligned and welded, a second solder resist layer 205 is disposed on a non-welding point area of ​​the second superconducting plate layer 2032 away from the surface of the second dielectric layer 202, so that the second solder joint 114 located on the second metallized via 112 is easier to form.

[0158] In some embodiments, the first solder resist layer 204 and / or the second solder resist layer 205 may be made of solder resist. In some examples, the first solder resist layer 204 and / or the second solder resist layer 205 may be solder resist ink (also known as green oil).

[0159] In some embodiments, the main components of the solder resist may include various chemical substances such as resin, solvent, filler and pigment.

[0160] Among them, resin is one of the main components of solder resist, and usually adopts epoxy resin, polyimide resin, acrylic resin, carboxylated epoxy acrylate and other types. Resin has excellent heat resistance and electrical insulation properties, which can effectively protect the areas on the circuit board that do not need to be soldered.

[0161] The solvent mixes the resin, filler and other materials evenly so that they can be evenly coated on the circuit board (thickness). The solvent can be an organic compound with a low boiling point, such as acetone, toluene, ethanol, etc.

[0162] Fillers are used to adjust the viscosity and fluidity of solder resist and increase impact resistance and wear resistance. Filler materials include but are not limited to silica, alumina, glass fiber, etc.

[0163] As the part of the superconducting metal that is not wettable with tin can naturally function as a soldering layer, there is no need to form a solder resist layer on the surface of the first superconducting plate layer 2031 and / or the second superconducting plate layer 2032 .

[0164] In some embodiments, the material of the first superconducting plate layer 2031 and / or the second superconducting plate layer 2032 is, for example, metal aluminum. Since an aluminum oxide layer is formed on the surface of the metal aluminum, the aluminum oxide layer is not wetted by tin, and the aluminum oxide layer can serve as a natural solder resist layer. In this case, there is no need to form a solder resist layer on the first superconducting plate layer 2031 and / or the second superconducting plate layer 2032.

[0165] In an embodiment of the present invention, the solder resist layer can realize electrical connection between the first shielding layer 1012 and the second shielding layer 1022 at the electronic level to reduce the ground impedance of the superconducting circuit layer 203, enhance the shielding of the signal line 2033, and reduce the crosstalk between adjacent lines.

[0166] refer to Fig.16 , Fig.17 As shown, after the first circuit sub-board 11 and the second circuit sub-board 22 are manufactured respectively, the second circuit sub-board 22 is mounted upside down on the first circuit sub-board 11 and welded after alignment.

[0167] In some embodiments, a flip chip bonding device is used, the temperature is controlled to keep the solder joints (solder balls) in a molten state, and alignment is forced to complete the assembly process.

[0168] In some embodiments, a method similar to the self-aligned soldering of BGA (Ball Grid Array) chips is used to completely melt the solder joints (tin balls) into liquid form, and the surface tension of the tin balls is used to complete the self-aligned soldering. This method saves costs and does not require expensive flip-chip soldering equipment.

[0169] The designed circuit board is schematically described below. It should be noted that the example description is only a specific embodiment of the present invention and cannot limit the protection scope of the present invention.

[0170] Example 1

[0171] refer to Fig.17 As shown, a circuit board is manufactured. Specifically, the circuit board includes: a signal sub-board, including a superconducting circuit layer 203 configured to transmit electrical signals of a superconducting quantum chip, and two dielectric layers arranged on both sides of the superconducting circuit layer 203; and two shielding layers and two thermal conductive layers arranged on both sides of the signal sub-board in sequence, wherein the shielding layer, the dielectric layer and the superconducting circuit layer are formed with a plurality of through metallized vias, and the spacing between two adjacent metallized vias is 300μm. The superconducting circuit layer 203 includes two signal lines 2033, and a ground plane symmetrically arranged on both sides of the signal line 2033 along the first direction of the signal line 2033; wherein the two ends of the metallized via are electrically connected to the shielding layer and the ground plane respectively.

[0172] The superconducting quantum chip is mounted on the circuit board manufactured in Example 1 through connecting wires, and the crosstalk (isolation) between the signal lines of the circuit board is simulated and calculated.

[0173] Comparative Example 1

[0174] The circuit board is manufactured by the same method as in Example 1, except that the circuit board does not have metallized vias.

[0175] The superconducting quantum chip is mounted on the circuit board manufactured in Comparative Example 1 through connecting wires, and the crosstalk (isolation) between the signal lines of the circuit board is simulated and calculated.

[0176] Fig.18 It is a comparison chart of the crosstalk simulation calculation results between the signal lines of the circuit boards provided in comparative example 1 and embodiment 1 of the present invention.

[0177] refer to Fig.18 As shown, the simulation calculation results show that the isolation of Example 1 is higher than that of Comparative Example 1. The shielding layer, dielectric layer and superconducting circuit layer of the circuit board provided in Example 1 are formed with through metallized vias, and the simulation calculation shows that the isolation between the signal lines of the circuit board at 7GHz is 38.8875 db. The circuit board provided in Comparative Example 1 does not have metallized vias, and the simulation calculation shows that the isolation between the signal lines of the circuit board at 7GHz is 36.4344 db. Compared with Comparative Example 1, Example 1 of the present invention improves the isolation between signal lines by about 2.45 db by forming through metallized vias in the shielding layer, dielectric layer and superconducting circuit layer, which indicates that the metallized vias have a certain effect on suppressing microwave crosstalk.

[0178] The ordinal numbers used in the specification and claims, such as "first", "second", "third", etc., to modify the corresponding elements, do not themselves mean that the elements have any ordinal numbers, nor do they represent the order of one element and another element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish a component with a certain name from another component with the same name.

[0179] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A circuit board for carrying a superconducting quantum chip, characterized in that: include: A signal sub-board, comprising a superconducting circuit layer configured to transmit electrical signals of a superconducting quantum chip, and two dielectric layers arranged on both sides of the superconducting circuit layer; as well as Two shielding layers and two heat-conducting layers are sequentially arranged on both sides of the signal sub-board, and the shielding layer, the dielectric layer and the superconducting circuit layer are formed with through metallized vias to electrically connect the shielding layer with the superconducting circuit layer, so that the shielding layer performs electromagnetic shielding on the superconducting circuit layer, and the heat-conducting layer conducts the heat generated by the superconducting circuit layer to the outside through the metallized vias, the dielectric layer and the shielding layer.

2. The circuit board according to claim 1, characterized in that: The dielectric layer is a ceramic layer; And / or, the shielding layer is a superconducting layer; And / or, the heat conductive layer is a copper layer; And / or, the metallized via is a copper column.

3. The circuit board according to claim 1, characterized in that: The superconducting circuit layer includes at least one signal line, and a ground plane symmetrically arranged on both sides of the signal line along a first direction of the signal line; Wherein, two ends of the metallized via are electrically connected to the shielding layer and the ground plane respectively; And / or, the superconducting circuit layer includes a first superconducting plate layer and a second superconducting plate layer which are stacked and welded together.

4. The circuit board according to claim 3, characterized in that: The signal line of the superconducting circuit layer is made of the first superconducting plate layer, and the ground plane of the superconducting circuit layer is made of the first superconducting plate layer and the second superconducting plate layer.

5. The circuit board according to claim 4, characterized in that: The second superconducting plate layer has at least one strip groove extending therethrough; The orthographic projection of the signal line on the dielectric layer is located within the orthographic projection region of the strip groove on the dielectric layer.

6. A method for manufacturing a circuit board according to any one of claims 1 to 5, characterized in that: include: A first circuit sub-board is provided, wherein the first circuit sub-board comprises a first dielectric layer, and a first superconducting plate layer and a first shielding layer respectively located on both sides of the first dielectric layer, and a first heat conducting layer is arranged on the surface of the first shielding layer, and the first shielding layer is electrically connected to the first superconducting plate layer through a first metallized via, wherein the first superconducting plate layer comprises at least one signal line, and a first ground plane symmetrically arranged on both sides of the signal line along a first direction of the signal line; A second circuit sub-board is provided, wherein the second circuit sub-board comprises a second dielectric layer, and a second superconducting plate layer and a second shielding layer respectively located on both sides of the second dielectric layer, and a second heat conducting layer is arranged on the surface of the second shielding layer, and the second shielding layer is electrically connected to the second superconducting plate layer through a second metallized via, wherein the second superconducting plate layer comprises at least one strip groove arranged through, and a second ground plane symmetrically arranged on both sides of the strip groove along a first direction of the strip groove; as well as The first circuit sub-board and the second circuit sub-board are welded in position so that the signal line is embedded in the strip groove, and the first ground plane and the second ground plane are electrically connected.

7. The manufacturing method according to claim 6, characterized in that: Also includes: A first soldering point is provided at one end of the first metallized via hole close to the first superconducting plate layer, and a second soldering point is provided at one end of the second metallized via hole close to the second superconducting plate layer; Aligning and welding the first circuit sub-board and the second circuit sub-board includes welding the first soldering point and the second soldering point.

8. The manufacturing method according to claim 7, characterized in that: Before the first circuit sub-board and the second circuit sub-board are aligned and welded, the method further includes: Disposing a first solder resist layer on a non-soldering point region of the first superconducting plate layer away from the surface of the first dielectric layer; And / or, a second solder resist layer is provided on a non-soldering point region of the second superconducting plate layer away from the surface of the second dielectric layer.

9. The manufacturing method according to claim 6, characterized in that: The formation process of the first metallized via includes: Forming metal layers on a first surface of the first dielectric layer and a second surface opposite to the first surface respectively; forming a plurality of first through holes penetrating the first dielectric layer; Depositing metal on the sidewall of the first through hole so that the metal in the first through hole is flush with the metal layer; and The metal layer on the first dielectric layer is etched so that a region of the metal layer corresponding to the first through hole is retained and a remaining region of the metal layer is removed.

10. A superconducting quantum computer, characterized in that: A circuit board comprising any one of claims 1 to 5; and A superconducting quantum chip is mounted on the circuit board.

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