Method for reducing operating voltage and improving read / write operation reliability of ferroelectric memory device

Abstract

The application belongs to the technical field of ferroelectric memory devices, and particularly relates to a method for reducing the working voltage of a ferroelectric memory device and improving the reliability of read-write operation. The ferroelectric memory device comprises a ferroelectric substrate, a ferroelectric bump, a first electrode and a second electrode on the ferroelectric substrate; the ferroelectric bump comprises a seed domain region and a ferroelectric storage layer region; by applying an electric field between the first electrode and the second electrode of the memory device unit, a stable seed domain region which is not easy to be erased is formed in a local region in the memory device unit; by using the seed domain region, the nucleation energy of the ferroelectric storage layer region domain inversion is reduced, the coercive field of the ferroelectric storage layer region domain is greatly reduced, and the stability and repeatability of the ferroelectric storage layer region domain inversion are improved, so that the stability and repeatability of the read-write operation of the nonvolatile ferroelectric memory device are enhanced, the read-write voltage and power consumption of the nonvolatile ferroelectric memory are reduced, and the memory read-write speed and service life are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of ferroelectric memory devices, and particularly relates to a method for reducing the working voltage of a ferroelectric memory device and improving the reliability of read-write operation. BACKGROUND

[0002] With the rapid development of 5G, Internet of Things, intelligent devices and other technologies, the amount of data is growing exponentially, and the storage device is required to not only have high storage density, but also have high speed access, long service life and low power consumption. In particular, in cloud computing, big data analysis, edge computing and other scenarios, the innovation of storage technology directly affects the application effect and development prospect of these emerging technologies. Future storage technology needs to make breakthroughs in improving read-write operation performance, reducing power consumption, increasing storage density and other aspects. Ferroelectric materials can be integrated with semiconductor materials, and under the action of an external electric field, the spontaneous polarization direction of the ferroelectric material can change, and the polarization state can be maintained without an external electric field, non-volatile storage of logic information "0" and "1". Non-volatile ferroelectric memory has the advantages of fast read-write speed, low power consumption, and compatibility with mainstream CMOS process, and is one of the important directions of storage technology development in recent years, especially in low power consumption, high speed and durability. However, the traditional ferroelectric memory uses a destructive data reading method based on charge integration, and the amount of charge that can be read out decreases linearly with the miniaturization of the memory cell area, causing difficulty in identifying the charge detection circuit, which limits the development of high-density ferroelectric memory. In order to overcome the bottleneck of high-density development of ferroelectric memory, in recent years, Jiang Anquan et al. designed a new type of ferroelectric domain wall memory based on the principle of generating erasable conductive domain walls in ferroelectric materials (CN201510036526.X, CN201510036586.1, CN201610098138.9, US10403348, JP2017-562045). This memory uses a non-destructive current reading method, which is different from the charge integration technology, and can identify the nanometer domain information written, so that the integration density of the memory is improved by 100 to 1000 times. They use electron beam direct writing and ion etching process to prepare storage units of different sizes on the surface of LiNbO3 ferroelectric single crystal thin film, and by applying an in-plane electric field, a parallel or anti-parallel domain structure is formed with a reference domain that does not reverse at the bottom, realizing non-volatile writing of information "0" or "1", and the readout current can reach 10 microamperes at 1V, the information retention time can be more than 10 years, and the on-off current ratio can be up to 10 5 The minimum unit can approach the atomic layer level, and the planar storage density is expected to be up to 2F 2 (F is the feature size of the semiconductor process), and the read-write operation has good reliability and consistency, so it has great industrialization prospects.

[0003] The memory principle is based on the domain reversal of ferroelectric material in the storage unit, thereby forming anti-parallel or parallel domain structure with the surrounding reference domain which is not reversed, and the anti-parallel or parallel domains form erasable conductive domain wall, by applying a small read voltage, an on or off state current is generated, thereby identifying the stored logic "0" and "1" information. And the ferroelectric domain reversal or information recording requires applying a voltage greater than a specific voltage, i.e. coercive voltage, so the writing electric field required for erasing and writing of the ferroelectric memory device must be higher than the coercive field of the ferroelectric material. For example, the coercive field of LiNbO3 ferroelectric single crystal is usually higher than 700kV / cm, when the device size is 100nm, a voltage of at least 7V or more is required to complete the writing operation, and the ferroelectric domain reversal speed is usually related to the size of the applied voltage, i.e. the greater the voltage, the faster the speed. However, too high a writing voltage will affect the power consumption and service life of the device. Therefore, how to reduce the working voltage of high-speed reading and writing ferroelectric memory is crucial. At the same time, the reversal of the domain starts from the reverse seed domain nucleation, which is strong in randomness, resulting in different coercive fields for each memory erasing and writing, i.e. random distribution within a large voltage range, i.e. poor repeatability of the erasing and writing operation, which affects the stability of the memory reading and writing operation. SUMMARY

[0004] In view of the problems of high working voltage and strong randomness of the erasing and writing operation of the current high-speed ferroelectric memory device, the purpose of the present application is to provide a method for significantly reducing the working voltage of the ferroelectric memory device and improving the reliability of the reading and writing operation.

[0005] The method for significantly reducing the working voltage of the ferroelectric memory device and improving the reliability of the reading and writing operation provided by the present application is to apply an electric field to the memory device unit, form a stable and not easily erased seed domain region in a local area of the memory device unit, use the seed domain region to reduce the nucleation energy of the domain reversal of the ferroelectric storage layer region, and greatly reduce the coercive field of the domain of the ferroelectric storage layer region, thereby reducing the reading and writing voltage and power consumption of the non-volatile ferroelectric memory, improving the reading and writing speed of the memory, and prolonging the information retention time. The existence of the seed domain can reduce the randomness of the nucleation of the ferroelectric storage layer domain, improve the reading and writing speed of the memory, enhance the stability and repeatability of the reading and writing operation of the device, and prolong the information retention time. The specific steps are as follows:

[0006] (1) Forming a ferroelectric bump or a groove isolated by ferroelectric material on the ferroelectric substrate by etching; the ferroelectric material of the ferroelectric bump or the isolated groove comprises a ferroelectric storage layer region and a seed domain region, and a first electrode and a second electrode are formed on both sides of the ferroelectric bump, or the first electrode and the second electrode are filled in the groove.

[0007] (2) the ferroelectric bump and the groove for filling the first electrode and the second electrode are both located on the ferroelectric substrate, the shape and relative position relationship of the first electrode and the second electrode on both sides of the ferroelectric bump or the groove for filling the first electrode and the second electrode satisfy the following conditions, that is, when an electric field is applied between the first electrode and the second electrode, there is a certain angle between the electric field and the polarization direction of the ferroelectric substrate, the angle range is greater than or equal to 0 degrees and less than 90 degrees, and the preferred range is greater than or equal to 0 degrees and less than or equal to 45 degrees.

[0008] (3) a first preset electric field is applied between the first electrode and the second electrode, the domain of the ferroelectric storage layer region between the two electrodes is reversed and nucleated and grows outward, thereby establishing a domain wall conductive channel connecting the first electrode and the second electrode, and the first preset electric field is greater than or equal to the coercive electric field of the domain of the ferroelectric storage layer region.

[0009] (4) under the preset electric field, the domain of the ferroelectric storage layer between the first electrode and the second electrode can be reversed to a region with a weaker electric field, which is the seed domain region. Because the seed domain region has a weaker electric field, the seed domain is not easy to be erased once it is formed, and the domain of the ferroelectric storage layer region can be normally reversed under the control of the electric field, forming an anti-parallel or parallel domain structure with the surrounding non-reversed domain, thereby forming an erasable domain wall conductive channel connected with the two electrodes, which can non-volatilely store logic "0" and "1" information. Because there is always a seed domain, the nucleation energy of the domain reversal in the ferroelectric storage layer can be reduced, and the randomness of the domain nucleation in the ferroelectric storage layer can be reduced, so that the stability and repeatability of the domain reversal of the ferroelectric storage layer can be controlled under a second preset electric field smaller than the first preset electric field. When a read electric field smaller than the second preset electric field is applied between the anti-parallel or parallel domains formed above, an on-state or off-state current is generated, which can identify the stored logic "0" and "1" information.

[0010] In the present application, the thickness of the ferroelectric bump in step (1) is greater than or equal to 1 nm and less than or equal to 1 μm; and the groove depth for generating the seed domain region is greater than or equal to 1 nm and less than or equal to 1 μm.

[0011] In the present application, the first preset electric field in step (3) can make the ferroelectric storage layer region domains between the lithium niobate type ferroelectric bumps first nucleate and reverse, and the reversed domains continue to grow under the driving of the depolarization field, expand to the region with weaker electric field, and form a seed domain region which is not easy to be erased. The formation principle of the seed domain region is that once formed in the region with weaker electric field of the bump, it is not easy to be erased. The region with weaker electric field is generally the edge region close to the ferroelectric storage layer or the partial electrostatic shielding region (weak electric field) in the storage layer. Generally, the reversal of the ferroelectric domain starts from the reverse nucleation growth of the domain, and the existence of the seed domain region can provide a nucleation seed for the domain reversal in the ferroelectric storage layer, greatly shorten the domain nucleation time, improve the memory read-write speed, reduce the write voltage, and improve the reliability of the read-write operation, including stability, repeatability and information retention time. The electrostatic shielding region can change the electric field distribution in the storage unit by designing different electrode structures to generate a partial low electric field region, and does not affect the information recording function of other regions.

[0012] In the present application, the ferroelectric material used in the ferroelectric substrate or ferroelectric bump can be selected from but not limited to one or more of the following: lithium niobate, lithium tantalate, bismuth ferrite, hafnium oxide, lead titanate zirconate; wherein the lithium niobate, lithium tantalate, bismuth ferrite, hafnium oxide, lead titanate zirconate are single crystal, thick film or thin film, including MgO, Mn2O5 or Fe2O3 doped lithium niobate salt, lithium tantalate salt or bismuth ferrite salt, or blackened lithium niobate salt, blackened lithium tantalate salt; the crystal direction of lithium niobate, lithium tantalate single crystal includes X cut, Z cut, Y cut and its inclined cut crystal.

[0013] In the present application, the material of the first electrode and the second electrode includes but is not limited to at least one of the following materials: tungsten, titanium, chromium, tantalum, copper, nickel, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide.

[0014] The present application has the following beneficial effects:

[0015] The present application forms a seed domain region which is not easy to be erased in the local region of the memory device unit by applying an electric field to the memory device unit, uses the seed domain region to reduce the nucleation energy of the domain reversal in the ferroelectric storage layer region, reduces the randomness of the domain nucleation, improves the memory read-write speed, greatly reduces the coercive electric field of the domain in the ferroelectric storage layer region; and the existence of the seed domain can stably control the repeated reversal of the domain in the ferroelectric storage layer, can enhance the stability and repeatability of the read-write operation of the device, and prolong the information retention time. The present application has great significance for reducing the read-write voltage and power consumption of the non-volatile ferroelectric memory, and can significantly improve the memory read-write speed and service life. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1A schematic diagram of the principle of the method for reducing the operating voltage of a ferroelectric memory device provided by the present application.

[0017] Figure 2 A plan view of a lithium niobate (LNO) ferroelectric memory device structure provided by Embodiment 2 of the present application.

[0018] Figure 3 A piezoelectric phase imaging diagram of a ferroelectric memory device provided by Embodiment 2 of the present application.

[0019] Figure 4 A current-voltage (I-V) curve diagram of a ferroelectric memory device provided by Embodiment 2 of the present application.

[0020] Figure 5 A coercive electric field fitting diagram of a ferroelectric memory device provided by Embodiment 2 of the present application.

[0021] Figure 6 A plan view of another lithium niobate (LNO) ferroelectric memory device structure provided by Embodiment 2 of the present application.

[0022] Figure 7 A plan view of another lithium niobate (LNO) ferroelectric memory device structure provided by Embodiment 2 of the present application.

[0023] Figure 8 A plan view of a lithium niobate (LNO) ferroelectric memory device structure provided by Embodiment 3 of the present application.

[0024] Figure 9 A piezoelectric phase imaging diagram of a ferroelectric memory device provided by Embodiment 3 of the present application.

[0025] Figure 10 A current-voltage (I-V) curve diagram of a ferroelectric memory device provided by Embodiment 3 of the present application.

[0026] Figure 11 A diagram showing the change of readout current with write-in time of a ferroelectric memory device provided by Embodiment 3 of the present application under different write voltages.

[0027] Figure 12 A hysteresis loop diagram of a ferroelectric memory device provided by the comparative example and the method embodiment of the present application.

[0028] Figure 13 A 500-time repeated scanning I-V curve diagram of a ferroelectric memory device provided by Embodiment 3 of the present application.

[0029] Figure 14 A plan view of another lithium niobate (LNO) ferroelectric memory device structure provided by Embodiment 3 of the present application.

[0030] Figure 15A plan view of another lithium niobate (LNO) ferroelectric memory device structure for Embodiment 3 of the present application.

[0031] Figure 16 A plan view of a lithium niobate (LNO) ferroelectric memory device structure for Embodiment 4 of the present application.

[0032] Figure 17 A piezoelectric phase imaging diagram of a ferroelectric memory device for Embodiment 4 of the present application.

[0033] Figure 18 An I-V curve diagram of a ferroelectric memory device for Embodiment 4 of the present application.

[0034] Figure 19 A plan view of another lithium niobate (LNO) ferroelectric memory device structure for Embodiment 4 of the present application.

[0035] Figure 20 A plan view of another lithium niobate (LNO) ferroelectric memory device structure for Embodiment 4 of the present application.

[0036] In the figure, 101 is a ferroelectric substrate, 102 is a ferroelectric bump formed by etching on the ferroelectric substrate, 103 is a first electrode and a second electrode formed on both sides of the ferroelectric bump, or the first electrode and the second electrode are filled in the groove, 1021 is a seed domain region in the ferroelectric bump, and 1022 is a ferroelectric storage layer region in the ferroelectric bump. DETAILED DESCRIPTION

[0037] The present application will be further described below by way of examples with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely a part of the embodiments of the present application, rather than all the embodiments. Based on the method proposed in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0038] In the embodiments, the terms "first electrode" and "second electrode" are used to illustrate the basic structure, but it should be noted that the two-electrode model in the embodiments of the present application is the most basic architecture, which is scalable and universal to realize local domain inversion of different area shapes or different numbers of domains.

[0039] In addition, in the embodiments, the "seed domain region" and the "ferroelectric storage layer region" are only used to distinguish the functions and effects, and do not limit the structure shape, number or other characteristics.

[0040] In the drawings, the thicknesses of the layers and regions are exaggerated for clarity, and the dimensional proportion relationship between the parts shown in the drawings does not reflect the actual dimensional proportion relationship.

[0041] In the embodiments, the exemplary electric domain direction or polarization direction is given, and the words such as "X-cut" or "Z-cut" describing the electric domain direction are used for representation as an example to facilitate the specific description of the principle. It should be understood that the electric domain direction or polarization direction is not limited to the direction shown in the embodiments of the present application.

[0042] In the embodiment 1, the principle of the method for reducing the working voltage of the ferroelectric memory device is described with reference to Figure 1 As shown in the figure, the ferroelectric bump 102 is formed by etching on the ferroelectric substrate 101, and the ferroelectric bump 102 includes the seed domain region 1021 and the ferroelectric storage layer region 1022; the first and second electrodes 103 are formed on both sides of the ferroelectric bump;

[0043] Further, when the first and second electrodes 103 are applied with the first preset electric field opposite to the polarization direction of the ferroelectric substrate 101, the electric domain of the ferroelectric storage layer region 1022 between the first and second electrodes 103 is reversed, and can be extended to the seed domain region 1021 with a weaker electric field. Since the electric field of the seed domain region 1021 is weak, the electric domain of the seed domain region 1021 is not easy to reverse under the electrostatic shielding effect, and the electric domain of the ferroelectric storage layer region 1022 can be normally reversed under the writing electric field, thereby forming a switchable domain wall conductive channel between the two electrodes. The domain wall conductive channel can be used to non-volatile store the logic "0" and "1" information.

[0044] Further, since the seed domain region 1021 with the electric domain opposite to the initial polarization direction always exists, the nucleation energy of the domain reversal of the ferroelectric storage layer region 1022 can be reduced; therefore, the stable reversal of the electric domain of the ferroelectric storage layer region can be controlled under the second preset electric field much smaller than the first preset electric field, thereby the working voltage of the ferroelectric memory device can be significantly reduced.

[0045] In the embodiment 2, a specific device design scheme for reducing the working voltage of the ferroelectric memory device is provided.

[0046] Figure 2 A planar schematic diagram of a lithium niobate (LNO) ferroelectric memory device structure provided for the embodiment 2 is shown in the figure. Figure 2 As shown in the figure, the lithium niobate ferroelectric bump 102 is formed on the X-cut lithium niobate ferroelectric substrate 101 doped with 5mol% MgO by the micro-nano processing method of photolithography, mask preparation, etching, etc., and the lithium niobate ferroelectric bump 102 includes the seed domain region 1021 and the ferroelectric storage layer region 1022; the first and second electrodes 103 are formed on both sides of the ferroelectric bump by thin film deposition and polishing technology;

[0047] Further, when a first electric field opposite to the polarization direction of the ferroelectric substrate 101 and greater than the coercive voltage is applied to the first and second electrodes 103, the domains of the ferroelectric storage layer region 1022 between the first and second electrodes 103 are reversed and extended to the seed domain region 1021 with a weaker electric field. Since the seed domain region 1021 has a weaker electric field, the domains of the seed domain region 1021 are not easy to reverse under the electrostatic shielding effect and can be stably maintained for a long time without changing with the application of read and write voltages; while the domains of the ferroelectric storage layer region 1022 can be normally reversed under the regulation of the write electric field to form a switchable domain wall conductive channel between the two electrodes, and the nonvolatile storage of information can be realized by using the domain wall conductive channel.

[0048] Further, since the seed domain region 1021 always exists, the domain reversal nucleation energy of the ferroelectric storage layer region 1022 can be reduced; therefore, the stable reversal of the ferroelectric storage layer region can be controlled under a second preset electric field much smaller than the first preset electric field, thereby reducing the working voltage of the ferroelectric memory device.

[0049] Figure 3 The piezoelectric phase imaging diagram of the lithium niobate ferroelectric memory device provided by the embodiment is shown, the arrow indicates the initial polarization direction, and the gap between the two electrodes is defined as the length dimension l of the device, which is 100 nm in this case; as Figure 3 (a) is the piezoelectric phase diagram of the lithium niobate ferroelectric memory in the original state.

[0050] Further, as shown in Figure 3 (b), when a +5V voltage opposite to the initial polarization direction is applied between the electrodes, the domains of the ferroelectric storage layer region between the first and second electrodes are reversed and extended to the seed domain region with a weaker electric field.

[0051] Further, as shown in Figure 3 (c), when a -5V voltage is applied between the electrodes, the domains of the ferroelectric storage layer region between the first and second electrodes are reversed to the same direction as the initial polarization direction, while the seed domain region does not change with the application of read and write voltages once it is formed and can be stably maintained for a long time due to the weaker electric field.

[0052] Further, as shown in Figure 3 (d) and (e), since the seed domain region always exists, the domain reversal nucleation energy of the ferroelectric storage layer region can be reduced; at this time, a voltage as low as ±3V can control the stable reversal of the domains of the ferroelectric storage layer region, thereby significantly reducing the working voltage of the ferroelectric memory device.

[0053] Figure 4 The I-V curve diagram of the lithium niobate ferroelectric memory device provided by the embodiment with a length dimension l of 100 nm is shown, as Figure 4As shown in (a) and (b), the device needs a voltage higher than 5V to complete the information writing in the seed-free domain region, while the device can complete the writing operation below 3V in the seed domain region.

[0054] Figure 5 A linear relationship diagram of the coercive voltage of the lithium niobate ferroelectric memory device with the device size is shown. The slope of the fitting straight line shows that the coercive field of the device in the seed-free domain region is 514kV / cm, and in comparison, the coercive field of the device in the seed domain region is significantly reduced to 167kV / cm. The low coercive field can reduce the electric domain reversal or information read-write electric field, improve the memory read-write life, and reduce the energy consumption.

[0055] Variablely, Figure 6 Another lithium niobate (LNO) ferroelectric memory device structure is provided for the embodiment 2 of the present application. Compared with Figure 2 Only the inclination direction of the lithium niobate ferroelectric bump 102 is changed, and the working principle can be referred to the example 2.

[0056] Variablely, Figure 7 Another lithium niobate (LNO) ferroelectric memory device structure is provided for the embodiment 2 of the present application. Compared with Figure 2 Only the shape of the lithium niobate ferroelectric bump 102 is changed, and the working principle can be referred to the example 2.

[0057] Embodiment 3, another specific device design scheme for reducing the working voltage of the ferroelectric memory device is provided.

[0058] Figure 8 A lithium niobate (LNO) ferroelectric memory device structure is provided for the embodiment 3 of the present application. A groove isolated by a ferroelectric material is formed on the lithium niobate ferroelectric substrate 101 by a micro-nano processing etching method, and the ferroelectric material for isolating the groove includes a seed domain region 1021 and a ferroelectric storage layer region 1022; the first and second electrodes 103 are formed in the groove by thin film deposition and chemical mechanical polishing technology.

[0059] Further, when a first electric field opposite to the polarization direction of the ferroelectric substrate 101 and greater than the coercive voltage is applied to the first and second electrodes 103, the domain of the ferroelectric storage layer region 1022 between the first and second electrodes 103 is reversed and expanded to the seed domain region 1021 with a weaker electric field. Due to the weaker electric field in the seed domain region 1021, the domain in the seed domain region 1021 is not easy to reverse under the electrostatic shielding effect and can be stably maintained for a long time, while the domain in the ferroelectric storage layer region 1022 can be normally reversed under the control of the writing electric field, forming a switchable domain wall conductive channel, and realizing the non-volatile storage of logic information "0" or "1".

[0060] Further, due to the existence of the seed domain region 1021, the nucleation energy of the domain switching of the ferroelectric storage layer region 1022 can be reduced; thus, the stable switching of the ferroelectric storage layer region can be controlled under a second preset electric field which is much lower than the first preset electric field, so that the write voltage of the ferroelectric memory device can be reduced.

[0061] Figure 9 The piezoelectric phase imaging of the lithium niobate ferroelectric memory device provided by the embodiment is shown, and the length dimension of the device is 100 nm, and the arrow indicates the initial polarization direction; as shown in Figure 9 (a), when a +7V voltage opposite to the initial polarization direction is applied to the device, the domains of the ferroelectric storage layer region between the first electrode and the second electrode are switched and expanded to the seed domain region with a weaker electric field.

[0062] Further, as shown in Figure 9 (b), when a -7V voltage is applied to the device, the domains of the ferroelectric storage layer region between the first electrode and the second electrode are switched to the same direction as the initial polarization direction, and the seed domain region does not switch due to the weaker electric field and the electrostatic shielding effect, and can be stably maintained for a long time.

[0063] Further, as shown in Figure 9 (c) and (d), due to the existence of the seed domain region, the nucleation energy of the domain switching of the ferroelectric storage layer region can be reduced; at this time, the stable switching of the ferroelectric storage layer region can be controlled by applying a voltage as low as +3V, which is significantly reduced compared with the initial polarization voltage of 7V.

[0064] Figure 10 The I-V curve diagram of the lithium niobate ferroelectric memory device provided by the embodiment corresponding to Figure 9 (d) is shown, and the device has a conduction domain wall current at 1.65V, which proves that the device can realize information writing below 3V, and the information can be non-volatile read by applying a voltage less than 3V.

[0065] Figure 11 The diagram showing the relationship between the read current and the write time of the lithium niobate ferroelectric memory device provided by the embodiment under different write voltages is shown. The write time of the device is below 10ns at 5.5V, which proves the ultrafast switching speed of the domain.

[0066] Figure 12 The hysteresis loop diagram of the lithium niobate ferroelectric memory device provided by the comparative example and the method embodiment of the present application is shown. Figure 12(a) and (b) respectively show the ferroelectric hysteresis loop of the domain switching in lithium niobate ferroelectric memory devices in the seed-free domain region and the seed domain region, it can be seen that the hysteresis loop of the present method has a more symmetrical trend about the voltage axis, the positive coercive voltage and the negative coercive voltage of the device in the seed domain region are respectively distributed at 2V and -2V, which confirms that the lithium niobate memory prepared by the method of the present application has greatly improved polarization retention characteristics.

[0067] Figure 13 The repeated scanning I-V curve diagram of the lithium niobate ferroelectric memory device provided by the present embodiment is shown. As shown in Figure 13 , the I-V curve of the device scanned 500 times is almost completely coincident, and the randomness of the electric domain nucleation in the ferroelectric storage layer is reduced due to the existence of the seed domain, which confirms that the device has extremely excellent stability and repeatability of read-write operation.

[0068] Variablely, Figure 14 The plane schematic diagram of another lithium niobate (LNO) ferroelectric memory device structure provided by the present embodiment is shown. As shown in Figure 14 , compared with Figure 8 , only the shape of the second electrode 103 is changed, and the working principle can refer to example 3.

[0069] Variablely, Figure 15 The plane schematic diagram of another lithium niobate (LNO) ferroelectric memory device structure provided by the present embodiment is shown. As shown in Figure 15 , compared with Figure 8 , only the position of the seed domain region 1021 is changed, and the working principle can refer to example 3.

[0070] Example 4 provides another specific device design scheme for reducing the working voltage of the ferroelectric memory device.

[0071] Figure 16 The plane schematic diagram of a lithium niobate (LNO) ferroelectric memory device structure provided by the present embodiment is shown. As shown in Figure 8 , a groove isolated by a ferroelectric material is formed on the lithium niobate ferroelectric substrate 101 by a micro-nano processing etching method, and the first and second electrodes 103 are formed in the groove by thin film deposition and polishing technology; the first and second electrodes 103 contain the seed domain region 1021 and the ferroelectric storage layer region 1022;

[0072] Further, when a first electric field opposite to the polarization direction of the ferroelectric substrate 101 and greater than the coercive voltage is applied to the first and second electrodes 103, the domains of the ferroelectric storage layer region 1022 between the first and second electrodes 103 are reversed and expanded to the seed domain region 1021 with a weaker electric field. Since the seed domain region 1021 has a weaker electric field, the domains of the seed domain region 1021 are not easily reversed and can be stably maintained for a long time under the electrostatic shielding effect, while the domains of the ferroelectric storage layer region 1022 can be normally reversed under the control of the writing electric field to form a switchable domain wall conductive channel, thereby realizing the nonvolatile storage of logic information "0" or "1".

[0073] Further, the presence of the seed domain region 1021 can reduce the domain reversal nucleation energy of the ferroelectric storage layer region 1022. Therefore, the stable reversal of the domains of the ferroelectric storage layer region can be controlled under a second preset electric field much smaller than the first preset electric field, thereby reducing the working voltage of the ferroelectric memory device.

[0074] Figure 17 The piezoelectric phase imaging and amplitude images of the lithium niobate ferroelectric memory device provided by the embodiment are shown. As shown in Figure 17 (a), when a +7V voltage opposite to the initial polarization direction is applied to the device, only the domains of the ferroelectric storage layer region between the first and second electrodes are reversed and expanded to the seed domain region with a weaker electric field.

[0075] Further, as shown in Figure 17 (b), when a +12V voltage is applied to the device, the domain reversal region of the ferroelectric storage layer is further expanded to the seed domain region with a weaker electric field, and the domains of the seed domain region are reversed.

[0076] Further, as shown in Figure 17 (c), when a -3V voltage is applied to the device, the domains of the ferroelectric storage layer region between the first and second electrodes are reversed to the same direction as the initial polarization direction, while the domains of the seed domain region do not reverse under the electrostatic shielding effect due to the weaker electric field and can be stably maintained for a long time.

[0077] Further, as shown in Figure 17 (d), the presence of the seed domain region can reduce the domain reversal nucleation energy of the ferroelectric storage layer region. At this time, a voltage as low as +3V can control the stable reversal of the domains of the ferroelectric storage layer region, which is significantly lower than the 7V polarization voltage in the initial state, thereby realizing the low-voltage control of the domain reversal of the ferroelectric storage layer region.

[0078] Figure 18 The I-V curve of the lithium niobate ferroelectric memory device provided by the embodiment is shown. As shown in Figure 18 (a), corresponding to Figure 17(a), the device needs 6.5V to appear conduction domain wall current, complete information writing; in contrast, as shown in Figure 18 (b), the corresponding Figure 17 (d), the device after forming a seed domain region, only need 3V to appear conduction domain wall current, complete information writing, so that the device write voltage is significantly reduced.

[0079] Variable, Figure 19 for another embodiment of the present application lithium niobate (LNO) ferroelectric memory device structure provided by the plane schematic diagram. As shown in Figure 19 compared with Figure 16 only the seed domain region 1021 position changes, the working principle can refer to example 4.

[0080] Variable, Figure 20 for another embodiment of the present application lithium niobate (LNO) ferroelectric memory device structure provided by the plane schematic diagram. As shown in Figure 20 compared with Figure 16 only the seed domain region 1021 position changes, the working principle can refer to example 4.

[0081] In summary, the present application provides a method for reducing the working voltage of ferroelectric memory device, greatly reduces the working voltage of ferroelectric memory device, can make the ferroelectric memory device write electric field at least 1 times, greatly reduces the read and write voltage and power consumption of nonvolatile ferroelectric memory, and has great significance, and can significantly improve the memory read and write speed and life, reduce energy consumption, at the same time, enhance the stability and retention characteristics of the device, can promote the development and application of new type of nonvolatile memory.

Claims

1. A method for reducing the operating voltage of ferroelectric storage devices and improving the reliability of read / write operations, characterized in that, This method involves applying an electric field to the memory cell to form stable and difficult-to-erase seed domain regions within a localized area. These seed domain regions reduce the nucleation energy for domain reversal in the ferroelectric storage layer, significantly lowering the coercive field of the domains and improving the stability and repeatability of domain reversal. This, in turn, reduces the read / write voltage and power consumption of the non-volatile ferroelectric memory, enhances the stability and repeatability of read / write operations, and improves the memory's read / write speed and lifespan. The specific steps are as follows: (1) Ferroelectric bumps or grooves isolated by ferroelectric material are formed on a ferroelectric substrate by etching; the ferroelectric material of the ferroelectric bumps or the isolated grooves includes a ferroelectric storage layer region and a seed domain region, and a first electrode and a second electrode are formed on both sides of the ferroelectric bumps, or the first electrode and the second electrode are filled in the grooves. (2) The shape and relative position of the first electrode and the second electrode satisfy the following condition: when an electric field is applied between the first electrode and the second electrode, there is a certain angle between the electric field and the polarization direction of the ferroelectric substrate, and the angle range is greater than or equal to 0 degrees and less than 90 degrees. (3) Apply a first preset electric field between the first electrode and the second electrode to cause the domains of the ferroelectric storage layer region between the two electrodes to nucleate and grow in reverse and expand outward, thereby establishing a domain wall conductive channel connecting the first electrode and the second electrode. The first preset electric field must be greater than or equal to the coercive electric field of the domain flipping in the ferroelectric storage layer region. (4) Under the first preset electric field, the domain reversal of the ferroelectric storage layer between the first electrode and the second electrode can be extended to the region with a weaker electric field, which is the seed domain region. Since the electric field of the seed domain region is weak, the seed domain is not easy to erase once it is formed. The domains of the ferroelectric storage layer region reverse normally under the control of the electric field, forming an antiparallel or parallel domain structure with the surrounding non-reversed domains, thereby forming an erasable domain wall conductive channel, which is connected to the two electrodes and can non-volatilely store logic "0" and "1" information. The stability and repeatability of the domain reversal of the ferroelectric storage layer are controlled under the second preset electric field which is smaller than the first preset electric field. A read electric field smaller than the second preset electric field is applied between the antiparallel or parallel domains formed above to generate an on-state or off-state current, which can identify the stored logic "0" and "1" information.

2. The method according to claim 1, characterized in that, The thickness of the ferroelectric bump in step (1) is greater than or equal to 1 nm and less than or equal to 1 μm; the depth of the groove in the seed domain region is greater than or equal to 1 nm and less than or equal to 1 μm.

3. The method according to claim 1, characterized in that, In step (2), there is an angle between the electric field between the first electrode and the second electrode and the polarization direction of the ferroelectric substrate, and the angle range is greater than or equal to 0 degrees and less than 90 degrees.

4. The method according to claim 1, characterized in that, In step (3), the first preset electric field can cause the ferroelectric storage layer domains between the ferroelectric bumps to first nucleate and reverse. The reversed domains continue to grow under the drive of the depolarization field, expanding to the region with a weaker electric field, forming a seed domain region that is not easy to erase.

5. The method according to any one of claims 1-4, characterized in that, The ferroelectric material used in the ferroelectric substrate or ferroelectric bump is selected from one or more of the following: lithium niobate, lithium tantalate, bismuth ferrite, hafnium oxide, and lead titanate zirconate.

6. The method according to any one of claims 1-4, characterized in that, The materials of the first electrode and the second electrode are selected from at least one of the following materials: tungsten, titanium, chromium, tantalum, copper, nickel, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

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