High-temperature resistant LED chip, its preparation method, and display screen

Abstract

The present invention discloses a high-temperature resistant LED chip, a preparation method thereof, and a display screen, relating to the field of LED manufacturing. The preparation method includes: etching an epitaxial wafer to form a conductive step; forming a first photoresist layer and a second photoresist layer; forming a photoresist opening; evaporating a reflective layer and a wire bonding layer; removing the first photoresist layer and the second photoresist layer; forming a passivation layer and opening holes. The photoresist opening includes a first opening and a second opening. The side wall of the cross-section of the first opening includes a first straight segment; the side wall of the cross-section of the second opening includes a second straight segment; the angles between the first straight segment and the second straight segment and the surface of the epitaxial wafer are α1 and α2 respectively, and α2 - α1 ≥ 65°; the angles between the side walls of the reflective layer and the wire bonding layer and the surface of the epitaxial wafer are β1 and β2 respectively; β2 - β1 ≥ 60°. The distance between the side wall of the wire bonding layer and the side wall of the reflective layer is ≥ 2 μm. Implementing the present invention can improve the high-temperature resistance performance of the LED chip and enhance its reliability.

Description

Technical Field

[0001] The present invention relates to the field of LED manufacturing, and particularly to a high-temperature resistant LED chip, a preparation method thereof, and a display screen. Background Art

[0002] In recent years, the display screen market based on red, green, and blue LED chips has expanded rapidly, and the demand is strong. Such LED chips for display screens need to be used under outdoor conditions in different regions and different environments, which puts forward higher requirements for their high-temperature resistance performance. Further, as the LED chips for display screens are gradually miniaturized, more and more LED chips are integrated in a single display screen device, and the heat generated by them is also increasing, which further puts forward higher requirements for the high-temperature resistance performance of a single LED chip.

[0003] On the other hand, in traditional LED chips, the electrode generally includes a reflective layer (generally Al) and a wire bonding layer (generally Au). Al metal is prone to expansion at high temperatures, contact with Au, and then react to form an Al-Au alloy. This alloy is a brittle solid solution and is prone to failure during use. Summary of the Invention

[0004] The technical problems to be solved by the present invention are to provide a high-temperature resistant LED chip and a preparation method thereof, which have strong high-temperature resistance performance and high reliability.

[0005] Another technical problem to be solved by the present invention is to provide a display screen with high reliability.

[0006] To solve the above technical problems, the present invention provides a preparation method of a high-temperature resistant LED chip, which includes the following steps:

[0007] S1. Provide an epitaxial wafer; wherein, the epitaxial wafer includes a substrate and a first semiconductor layer, an active layer, and a second semiconductor layer that are sequentially stacked on the substrate;

[0008] S2. Etch the epitaxial wafer to form a conductive step;

[0009] S3. Form a first photoresist layer on the epitaxial wafer obtained in step S2;

[0010] S4. Form a second photoresist layer on the first photoresist layer;

[0011] S5. Expose and develop the epitaxial wafer obtained in step S4 to remove the first photoresist layer and the second photoresist layer in the preset area, forming a photoresist opening; the photoresist opening includes a first opening and a second opening arranged in sequence from bottom to top, and the side wall of the cross-section of the first opening includes at least a first arc segment and a first straight segment connected thereto; the side wall of the cross-section of the second opening includes at least a second arc segment and a second straight segment connected thereto; the included angle between the first straight segment and the surface of the epitaxial wafer is α1, and the included angle between the second straight segment and the surface of the epitaxial wafer is α2, α2 - α1 ≥ 65°;

[0012] S6. Evaporate and deposit on the epitaxial wafer obtained in step S5 to form a reflective layer on the second photoresist layer and within the photoresist opening; the reflective layer includes a reflective sub-layer and a protective layer covering the reflective sub-layer; the included angle between the side wall of the reflective layer within the photoresist opening and the surface of the epitaxial wafer is β1;

[0013] S7. Evaporate and deposit on the epitaxial wafer obtained in step S6 to form a wire bonding layer on the reflective layer; the included angle between the side wall of the wire bonding layer within the photoresist opening and the surface of the epitaxial wafer is β2, β2 - β1 ≥ 60°; and there is a preset distance L between the side wall of the wire bonding layer within the photoresist opening and the side wall of the reflective layer within the photoresist opening, L ≥ 2 μm;

[0014] S8. Remove the first photoresist layer, the second photoresist layer, and the reflective layer and the wire bonding layer above them;

[0015] S9. Form a passivation layer on the epitaxial wafer obtained in step S8 and form a wire bonding hole above the wire bonding layer, thus obtaining a finished high-temperature resistant LED chip.

[0016] As an improvement of the above technical solution, the first photoresist layer is formed by a first photoresist, and the second photoresist layer is formed by a second photoresist; the viscosity of the first photoresist is less than that of the second photoresist;

[0017] The thickness of the first photoresist layer is less than that of the second photoresist layer.

[0018] As an improvement of the above technical solution, the first photoresist is a negative photoresist with a viscosity of 40 - 60 cP;

[0019] The second photoresist is a negative photoresist with a viscosity of 80 - 100 cP;

[0020] The thickness of the first photoresist layer is 1 / 3 - 1 / 2 of the thickness of the second photoresist layer.

[0021] As an improvement to the above technical solution, the reflective sub-layer is an Al layer with a thickness of 1200 - 3000 Å;

[0022] The protective layer includes a Ti layer, a first Pt layer, a Ni layer, and a second Pt layer that are sequentially stacked on the reflective sub-layer. The thickness of the Ti layer is 1000 - 2000 Å, the thickness of the first Pt layer is 500 - 1000 Å, the thickness of the Ni layer is 1000 - 2000 Å, and the thickness of the second Pt layer is 500 - 1000 Å;

[0023] The wire bonding layer is an Au layer with a thickness of 15000 - 20000 Å;

[0024] The passivation layer is an Al2O3 layer with a thickness of 600 - 1200 Å.

[0025] As an improvement to the above technical solution, in step S6, when depositing the reflective layer, the metal beam current has a first angle with the surface of the epitaxial wafer;

[0026] In step S7, when depositing the protective layer, the metal beam current has a second angle with the surface of the epitaxial wafer;

[0027] The second angle < the first angle.

[0028] As an improvement to the above technical solution, the first angle is 40° - 50°, and the second angle is 30° - 35°.

[0029] As an improvement to the above technical solution, the value range of α1 is 15° - 30°, and the value range of α2 is 85° - 90°;

[0030] The value range of β1 is 20° - 40°, and the value range of β2 is 80° - 88°;

[0031] The value range of L is 2 - 4 μm;

[0032] The thickness of the first photoresist layer is 1 - 3 μm, and the thickness of the second photoresist layer is 5 - 10 μm.

[0033] As an improvement to the above technical solution, step S5 includes:

[0034] S51. Expose the epitaxial wafer obtained in step S4 for 5 - 15 s using an exposure light source with a wavelength of 280 - 350 nm, and the light intensity is 100 - 150 mJ / cm 2 ;

[0035] S52. Expose the epitaxial wafer obtained in step S51 for 3 - 5 s using an exposure light source with a wavelength of 310 - 380 nm, and the light intensity is 150 - 200 mJ / cm 2 ;

[0036] S53. Spray the epitaxial wafer obtained in step S52 with a developer at a pressure of 0.5 - 0.9 bar for 30 - 40 s; wherein, the temperature of the developer is 18 - 20 °C;

[0037] S54. Spray the epitaxial wafer obtained in step S53 with a developer at a pressure of 1 - 1.3 bar for 50 - 90 s; wherein, the temperature of the developer is 25 - 28 °C;

[0038] S55. Bake the epitaxial wafer obtained in step S54 at 100 - 110 °C for 40 - 100 s, then bake it at 120 - 140 °C for 5 - 10 min, and finally bake it at 115 - 125 °C for 5 - 10 min.

[0039] Correspondingly, the present invention also discloses a high-temperature resistant LED chip, which is prepared by the preparation method of the high-temperature resistant LED chip described above.

[0040] Correspondingly, the present invention also discloses a display screen, which includes the high-temperature resistant LED chip described above.

[0041] Implementing the present invention has the following beneficial effects:

[0042] In the preparation method of the high-temperature resistant LED chip in an embodiment of the present invention, a first photoresist layer and a second photoresist layer are sequentially formed on the epitaxial wafer, a photoresist opening with a specific shape is formed through exposure and development, then a reflective layer and a protective layer are sequentially evaporated, and finally a passivation layer is formed and opened to obtain a finished high-temperature resistant LED chip. Specifically, the photoresist opening includes a first opening and a second opening arranged sequentially from bottom to top. The side wall of the cross-section of the first opening includes at least a first arc segment and a first straight segment connected thereto; the side wall of the cross-section of the second opening includes at least a second arc segment and a second straight segment connected thereto; the angle between the first straight segment and the surface of the epitaxial wafer is α1, the angle between the second straight segment and the surface of the epitaxial wafer is α2, and α2 - α1 ≥ 65°. Based on the photoresist opening with this specific morphology, the angles β1 and β2 between the side walls of the reflective layer and the wire bonding layer formed later and the surface of the epitaxial wafer satisfy the relationship of β2 - β1 ≥ 60°, and a preset distance L, L ≥ 2 μm, is provided between the side wall of the wire bonding layer and the side wall of the reflective layer; with such a setting, the service life of the LED chip under high-temperature conditions is greatly extended, and the reliability of the LED chip is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a schematic structural diagram of the epitaxial wafer after step S2 in an embodiment of the present invention;

[0044] Figure 2It is a schematic structural diagram of an epitaxial wafer after step S5 in an embodiment of the present invention;

[0045] Figure 3 It is a schematic structural diagram of an epitaxial wafer after step S7 in an embodiment of the present invention;

[0046] Figure 4 It is a schematic structural diagram of a high-temperature resistant LED chip in an embodiment of the present invention;

[0047] In the figure, 1 is an epitaxial wafer, 11 is a substrate, 12 is a first semiconductor layer, 13 is an active layer, 14 is a second semiconductor layer, 15 is a conductive step, 16 is an isolation groove, 2 is a transparent conductive layer, 3 is a first photoresist layer, 4 is a second photoresist layer, 5 is a photoresist opening, 51 is a first opening, 511 is a first arc segment, 512 is a first straight segment, 52 is a second opening, 521 is a second arc segment, 522 is a second straight segment, 6 is a reflective layer, 61 is a reflective sub-layer, 62 is a protective layer, 621 is a Ti layer, 622 is a first Pt layer, 623 is a Ni layer, 624 is a second Pt layer, 63 is a side wall of the reflective layer, 7 is a wire bonding layer, 71 is a side wall of the wire bonding layer, 8 is a passivation layer, 81 is a wire bonding hole. Detailed implementation manners

[0048] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals indicate the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present application and cannot be understood as a limitation to the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application.

[0049] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present application.

[0050] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the described features.

[0051] The present invention discloses a method for preparing a high-temperature resistant LED chip, which comprises the following steps:

[0052] S1. Provide an epitaxial wafer;

[0053] Among them, the epitaxial wafer 1 includes a substrate 11 and an epitaxial layer. Among them, the epitaxial layer includes a first semiconductor layer 12, an active layer 13, and a second semiconductor layer 14 that are sequentially stacked on the substrate 11. The substrate 11 is a sapphire substrate, a silicon substrate, or a SiC substrate, but not limited thereto. The first semiconductor layer 12 can be an N-type GaN layer, an N-type AlGaN layer, an N-type GaAs layer, but not limited thereto. The active layer 13 can be an InGaN-GaN type MQW layer, an InGaN-AlGaN type MQW layer, or an AlGaN-AlGaN type MQW layer, but not limited thereto. The second semiconductor layer 14 can be a P-type GaN layer, a P-type AlGaN layer, a P-type GaAs layer, but not limited thereto.

[0054] Preferably, in an embodiment of the present invention, the epitaxial layer may further include one or more of a buffer layer, an intrinsic semiconductor layer, a stress buffer layer, an electron blocking layer, and an ohmic contact layer that are common in the art, but not limited thereto.

[0055] S2. Etch the epitaxial wafer to form a conductive step;

[0056] Specifically, a mask (such as a photoresist layer, a SiO2 layer, etc.) may be first formed on the epitaxial wafer 1 obtained in step S1, and then the second semiconductor layer 14, the active layer 13, and a part of the first semiconductor layer 12 in a preset area are removed by wet etching or dry etching to form a conductive step 15, but not limited thereto.

[0057] Preferably, in some embodiments, a photoresist layer is first formed on the epitaxial wafer 1 obtained in step S1. After it is exposed, developed, and patterned, the second semiconductor layer 14, the active layer 13, and a part of the first semiconductor layer 12 are etched away by inductively coupled plasma etching process (ICP) to obtain a conductive step 15. Further, in some embodiments, refer to Figure 1 , continue to etch at a preset position until the substrate 11 is exposed to form an isolation groove 16 for isolating multiple LED chips, and finally remove the photoresist layer.

[0058] Preferably, in some embodiments, step S2 includes:

[0059] S21. Etch the epitaxial wafer obtained in step S1 to form a conductive step;

[0060] Specifically, in this step, only the conductive step 15 is etched and formed, and the isolation groove 16 is not formed.

[0061] S22. Form a transparent conductive layer on the epitaxial wafer obtained in step S21;

[0062] Among them, the transparent conductive layer 2 can be a common ITO layer, IZO layer, AZO layer, ATO layer or FTO layer in the art, but not limited thereto. Preferably, the transparent conductive layer 2 is an ITO layer. The thickness of the transparent conductive layer 2 is 5 - 150 nm, preferably 50 - 150 nm.

[0063] The transparent conductive layer 2 can be formed by processes such as magnetron sputtering method, electron beam evaporation method, etc., but not limited thereto. Preferably, in one embodiment, after forming the transparent conductive layer 2, annealing is performed on it. The annealing temperature is 500 - 600 °C, and the annealing time is 3 - 10 min. Through annealing, its light transmittance can be optimized, and the ohmic contact between it and the second semiconductor layer 14 can be optimized.

[0064] S23. Etch and remove the transparent conductive layer in the preset area, and retain the transparent conductive layer on the second semiconductor layer;

[0065] Specifically, a mask (such as a photoresist layer, SiO2 layer, etc.) can be first formed on the epitaxial wafer 1 obtained in step S22, and then the transparent conductive layer 2 in the preset area is removed by wet etching or dry etching, and only the transparent conductive layer 2 on the second semiconductor layer 14 is retained, but not limited thereto.

[0066] Preferably, in some embodiments, a photoresist layer is first formed on the epitaxial wafer 1 obtained in step S22. After it is exposed, developed and patterned, the transparent conductive layer 2 in the preset area is etched and removed using an etching solution, and then the photoresist layer is removed.

[0067] S24. Etch to form isolation grooves;

[0068] Specifically, a mask (such as a photoresist layer, SiO2 layer, etc.) can be first formed on the epitaxial wafer 1 obtained in step S23, and then the conductive step 15 in the preset area is removed by wet etching or dry etching to form an isolation groove 16 exposing the substrate 11, but not limited thereto.

[0069] Preferably, in some embodiments, a photoresist layer is first formed on the epitaxial wafer 1 obtained in step S23. After it is exposed, developed and patterned, the conductive step 15 is etched through ICP process to form an isolation groove 16.

[0070] It should be noted that in some embodiments, before forming the conductive step 15, a transparent conductive layer 2 is first formed on the epitaxial wafer 1, and then the patterning of the transparent conductive layer 2, the formation of the conductive step 15 and the formation of the isolation groove 16 are achieved through photolithography and etching processes.

[0071] S3. Form a first photoresist layer on the epitaxial wafer obtained in step S2;

[0072] Among them, the first photoresist layer 3 is formed by the first photoresist. The first photoresist is a common positive photoresist or negative photoresist in the art, but is not limited thereto. Preferably, in one embodiment, the first photoresist is a negative photoresist, which has high resolution and large aspect ratio, and can lay a good foundation for forming the photoresist opening 5 with a specific shape of the present invention. The viscosity of the first photoresist is 40-80 cP, exemplarily 45 cP, 50 cP, 60 cP, 72 cP or 78 cP, but is not limited thereto. Preferably it is 40-60 cP.

[0073] Specifically, the first photoresist can be coated on the epitaxial wafer 1 by a spin coating process, and then baked and cured to form the first photoresist layer 3. Specifically, the thickness of the first photoresist layer 3 is 1-5 μm, exemplarily 1.5 μm, 2 μm, 3.5 μm or 4 μm, but is not limited thereto. Preferably it is 1-3 μm.

[0074] S4. Form a second photoresist layer on the first photoresist layer;

[0075] Among them, the second photoresist layer 4 is formed by the second photoresist. The second photoresist is a common positive photoresist or negative photoresist in the art, but is not limited thereto. Preferably, in one embodiment, the second photoresist is a negative photoresist, which has high resolution and large aspect ratio, and lays a good foundation for forming the photoresist opening 5 with a specific shape of the present invention. The viscosity of the second photoresist is 60-100 cP, exemplarily 70 cP, 80 cP, 90 cP or 95 cP, but is not limited thereto. Preferably it is 80-100 cP.

[0076] Specifically, the first photoresist can be coated on the epitaxial wafer 1 by a spin coating process, and then baked and cured to form the first photoresist layer 3. Specifically, the thickness of the second photoresist layer 4 is 3-15 μm, exemplarily 4.5 μm, 6 μm, 7.5 μm, 9 μm, 10.5 μm or 13 μm, but is not limited thereto. Preferably it is 5-10 μm.

[0077] Preferably, in some embodiments, in order to enhance the connection between the first photoresist layer 3 and the second photoresist layer 4, a tackifier is coated on the first photoresist layer 3 before forming the second photoresist layer 4.

[0078] Preferably, in some embodiments, when both the first photoresist and the second photoresist are negative photoresists, the viscosity of the first photoresist is controlled to be less than that of the second photoresist. Based on this control, on the one hand, it can ensure that when the thickness of the second photoresist layer 4 is greater than that of the first photoresist layer 3, both are relatively uniform; on the other hand, it makes the developer diffusion in the second photoresist layer 4 slower, which is beneficial to increasing α2 - α1. Correspondingly, in the photoresist layer formed based on the first photoresist and the second photoresist, the thickness of the first photoresist layer 3 is less than that of the second photoresist layer 4. More specifically, the thickness of the first photoresist layer 3 is 1 / 3 - 1 / 2 of the thickness of the second photoresist layer 4. By controlling the thickness ratio of the two, α2 - α1 can be further increased, thereby increasing the distance L between the sidewall 71 of the wire bonding layer and the sidewall 63 of the reflective layer in the subsequent finished electrode, and further improving the high-temperature resistance performance of the LED chip.

[0079] S5. Expose and develop the epitaxial wafer obtained in step S4 to remove the first photoresist layer and the second photoresist layer in a preset area to form a photoresist opening.

[0080] Specifically, exposure is performed using an exposure light source, and then development is performed using a developer to remove a part of the first photoresist layer 3 and the second photoresist layer 4 on the conductive step 15 and the second semiconductor layer 14, thus obtaining the photoresist opening 5. The wavelength of the exposure light source is 280 - 380 nm, the light intensity is 100 - 200 mJ / cm 2 , and the exposure time is 5 - 20 s. The development time is 50 - 150 s, and post-baking is performed after development, but it is not limited thereto.

[0081] Specifically, referring to Figure 2 , after the exposure and development process, a photoresist opening 5 is formed, which includes a first opening 51 and a second opening 52 arranged in sequence from bottom to top. The sidewall of the cross-section of the first opening 51 includes at least a first arc segment 511 and a first straight segment 512 connected thereto; the sidewall of the cross-section of the second opening 52 includes at least a second arc segment 521 and a second straight segment 522 connected thereto; the angle between the first straight segment 512 and the surface of the epitaxial wafer 1 is α1, and the angle between the second straight segment 522 and the surface of the epitaxial wafer 1 is α2, and α2 - α1 ≥ 65°. More specifically, α2 - α1 = 65° - 75°.

[0082] Specifically, the value range of α1 is 10° - 35°, for example, 12°, 18°, 24°, 30° or 33°, but it is not limited thereto. Preferably, it is 15° - 30°.

[0083] Specifically, the value range of α2 is 80° - 90°, for example, 82°, 84°, 86° or 88°, but it is not limited thereto. Preferably, it is 85° - 90°.

[0084] Preferably, in some embodiments, step S5 includes:

[0085] S51. Expose the epitaxial wafer obtained in step S4 for 5 - 15 s using an exposure light source with a wavelength of 280 - 350 nm, and the light intensity is 100 - 150 mJ / cm 2 ;

[0086] S52. Expose the epitaxial wafer obtained in step S51 for 3 - 5 s using an exposure light source with a wavelength of 310 - 380 nm, and the light intensity is 150 - 200 mJ / cm 2 ;

[0087] S53. Spray the epitaxial wafer obtained in step S52 with a developer at a pressure of 0.5 - 0.9 bar for 30 - 40 s; wherein, the temperature of the developer is 18 - 20 °C;

[0088] S54. Spray the epitaxial wafer obtained in step S53 with a developer at a pressure of 1 - 1.3 bar for 50 - 90 s; wherein, the temperature of the developer is 25 - 28 °C;

[0089] S55. Bake the epitaxial wafer obtained in step S54 at 100 - 110 °C for 40 - 100 s, then bake it at 120 - 140 °C for 5 - 10 min, and finally bake it at 115 - 125 °C for 5 - 10 min.

[0090] Based on the above - mentioned specific exposure - development - post - bake process, α2 - α1 can be increased to 68° - 75°, further optimizing the high - temperature resistance performance of the LED chip.

[0091] S6. Evaporate and deposit on the epitaxial wafer obtained in step S5 to form a reflective layer on the second photoresist layer and within the photoresist opening;

[0092] Specifically, when evaporating and depositing the reflective layer 6, the metal beam has a first angle with the surface of the epitaxial wafer 1. It should be noted that in the present invention, the surface of the epitaxial wafer 1 refers to the plane where the substrate 11 is located. By controlling the first angle and cooperating with the photoresist opening 5 with a specific shape, a reflective layer 6 with a relatively large width and a relatively small thickness can be formed at the bottom of the photoresist opening 5, reducing the risk of the reflective layer 6 contacting the subsequent wire - bonding layer 7 due to high - temperature expansion, and improving the high - temperature resistance performance of the LED chip. Specifically, the first angle is 35° - 50°, exemplarily 38°, 40°, 43°, 46° or 49°, but not limited thereto. Preferably, it is 40° - 50°.

[0093] Specifically, the reflective layer 6 includes a reflective sub-layer 61 and a protective layer 62 stacked in sequence. The reflective sub-layer 61 can be an Al layer, an Al-Cu alloy layer, or an Ag layer, but is not limited thereto. Preferably, in some embodiments, the reflective sub-layer 61 is an Al layer. The thickness of the reflective sub-layer 61 is 1000 - 3000 Å, exemplarily 1200 Å, 1500 Å, 1800 Å, 2100 Å, 2400 Å, or 2700 Å, but is not limited thereto. Preferably, it is 1200 - 3000 Å.

[0094] Specifically, the protective layer 62 is a metal layer that can coat the reflective sub-layer 61. Specifically, it can be a Pt layer, a Ti layer, a TiN layer, or a Ni layer, but is not limited thereto. This protective layer 62 can enhance the ability of the electrode to resist moisture corrosion and can block metal diffusion, improving the reliability of the LED chip. Specifically, the thickness of the protective layer 62 is 2000 - 10000 Å, exemplarily 3000 Å, 4500 Å, 6000 Å, 7500 Å, or 9000 Å, but is not limited thereto. Preferably, in some embodiments, the protective layer 62 includes a Ti layer 621, a first Pt layer 622, a Ni layer 623, and a second Pt layer 624 stacked in sequence. Among them, the thickness of the Ti layer 621 is 1000 - 2000 Å, the thickness of the first Pt layer 622 is 500 - 1000 Å, the thickness of the Ni layer 623 is 1000 - 2000 Å, and the thickness of the second Pt layer 624 is 500 - 1000 Å.

[0095] Specifically, the included angle between the side wall 63 of the reflective layer and the surface of the epitaxial wafer 1 is β1, and the value range of β1 is 18° - 40°, exemplarily 22°, 26°, 32°, or 36°, but is not limited thereto. Preferably, it is 20° - 40°.

[0096] S7. Evaporate and deposit on the epitaxial wafer obtained in step S6 to form a wire bonding layer on the reflective layer;

[0097] Specifically, referring to Figure 3 , when evaporating and depositing the wire bonding layer 7, the metal beam current has a second angle with the surface of the epitaxial wafer 1. It should be noted that in the present invention, the surface of the epitaxial wafer 1 refers to the plane where the substrate 11 is located. By controlling the second angle and cooperating with the photoresist opening 5 with a specific shape, a wire bonding layer 7 with a larger thickness and a smaller width can be formed on the reflective layer 6, such that the side wall 71 of the wire bonding layer has a preset distance L from the side wall 63 of the reflective layer, and L ≥ 2 μm, effectively preventing the reflective layer 6 from contacting the wire bonding layer 7 after thermal expansion at high temperature, and greatly improving the high-temperature performance of the LED chip. Specifically, the second angle is 25° - 40°, exemplarily 28°, 31°, 34°, or 37°, but is not limited thereto. Preferably, it is 30° - 35°.

[0098] Preferably, in some embodiments, the second angle < the first angle to further increase L and improve the high-temperature resistance. Specifically, the value range of L is 2 - 5 μm. If L is too large, the width of the wire bonding layer 7 will be too narrow, affecting the subsequent wire bonding process. Exemplarily, L is 2.3 μm, 3 μm, 3.4 μm or 4.5 μm, but not limited thereto. Preferably, it is 2 - 4 μm.

[0099] Specifically, the wire bonding layer 7 is an Au layer or an Ag layer, but not limited thereto. Preferably, it is an Au layer. The thickness of the wire bonding layer 7 is 10000 - 20000 Å. Exemplarily, it is 12000 Å, 14000 Å, 16000 Å or 18000 Å, but not limited thereto. Preferably, it is 15000 - 20000 Å.

[0100] Specifically, the included angle between the side wall 71 of the wire bonding layer and the surface of the epitaxial wafer 1 is β2, and the value range of β2 is 75° - 90°. Exemplarily, it is 78°, 83°, 85° or 87°, but not limited thereto. Preferably, it is 80° - 88°.

[0101] Specifically, β2 - β1 ≥ 60°. More specifically, β2 - β1 = 60° - 70°.

[0102] S8. Remove the first photoresist layer, the second photoresist layer, and the reflection layer and wire bonding layer above them;

[0103] Specifically, the first photoresist layer 3, the second photoresist layer 4, and the reflection layer 6 and wire bonding layer 7 thereon can be removed by a cleaning solution, but not limited thereto. Preferably, in some embodiments, the reflection layer 6 and wire bonding layer 7 on the first photoresist layer 3 and the second photoresist layer 4 are removed by a blue film peeling process, and then the first photoresist layer 3 and the second photoresist layer 4 are removed by cleaning with a cleaning solution.

[0104] S9. Form a passivation layer 8 on the epitaxial wafer 1 obtained in step S8, and form a wire bonding hole above the wire bonding layer 7, thereby obtaining a high-temperature resistant LED chip product.

[0105] Specifically, step S9 includes:

[0106] S91. Form a passivation layer on the epitaxial wafer 1 obtained in step S8;

[0107] Among them, referring to Figure 4 , the passivation layer 8 can be made of SiO2, Al2O3, SiN x , SiO x N ymade from one or more of the above, but not limited thereto. Preferably, in some embodiments, the passivation layer 8 is an Al2O3 layer. The thickness of the passivation layer 8 is 500 - 3000 Å, exemplarily 800 Å, 1400 Å, 2100 Å or 2600 Å, but not limited thereto. Preferably it is 500 - 1200 Å.

[0108] Among them, the passivation layer 8 can be formed by PECVD, ALD or MOCVD, but not limited thereto. Preferably, the Al2O3 layer is formed by ALD as the passivation layer 8.

[0109] S92. Etch the passivation layer to form a wire bonding hole above the wire bonding layer;

[0110] Specifically, the passivation layer 8 in the preset area can be removed by a dry etching process or a wet etching process to obtain the wire bonding hole 81, but not limited thereto. Preferably, in one embodiment, the wire bonding hole 81 is etched and formed by an ICP etching process.

[0111] In summary, in the preparation method of the high-temperature resistant LED chip in this embodiment, a first photoresist layer 3 and a second photoresist layer 4 are sequentially formed on the epitaxial wafer 1, and a photoresist opening 5 with a specific shape is formed through exposure and development. Then, a reflective layer 6 and a protective layer 62 are sequentially evaporated, and finally a passivation layer 8 is formed and opened to obtain the finished high-temperature resistant LED chip. Specifically, the photoresist opening 5 includes a first opening 51 and a second opening 52 arranged in sequence from bottom to top. The side wall of the cross-section of the first opening 51 at least includes a first arc segment 511 and a first straight segment 512 connected thereto; the side wall of the cross-section of the second opening 52 at least includes a second arc segment 521 and a second straight segment 522 connected thereto; the included angle between the first straight segment 512 and the surface of the epitaxial wafer 1 is α1, and the included angle between the second straight segment 522 and the surface of the epitaxial wafer 1 is α2, and α2 - α1 ≥ 65°. Based on the photoresist opening 5 with this specific morphology, the included angles β1 and β2 between the side walls 63 of the reflective layer and the side walls 71 of the wire bonding layer formed later and the surface of the epitaxial wafer 1 satisfy the relationship of β2 - β1 ≥ 60°, and a preset distance L, L ≥ 2 μm is provided between the side walls 71 of the wire bonding layer and the side walls 63 of the reflective layer; with such a setting, the service life of the LED chip in a high-temperature environment is greatly extended; the reliability of the LED chip is improved.

[0112] Specifically, based on the technical solution in this embodiment and a conventional LED chip, their high-temperature aging times are shown in the following table:

[0113]

[0114] Specifically, the high-temperature experiment process is as follows: First, record the working voltage value of the LED chip before the start of high-temperature aging, which is defined as the initial voltage value; after the start of high-temperature aging, record the voltage value of the LED chip every 24 hours, which is defined as the current voltage value; when the difference between the current voltage value and the initial voltage value exceeds 0.1V, the LED chip fails, and record the time node of the current high-temperature aging. Among them, the temperature of high-temperature aging is 95°C, and the humidity is 50%RH.

[0115] It can be seen from the table that the high-temperature aging time of the LED chip in this technical solution is greatly extended.

[0116] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0117] Although the embodiments of this application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principle and purpose of this application, and the scope of this application is defined by the claims and their equivalents.

Claims

1. A preparation method of a high-temperature resistant LED chip, characterized in that, It includes the following steps: S1. Provide an epitaxial wafer; wherein, the epitaxial wafer includes a substrate and a first semiconductor layer, an active layer, and a second semiconductor layer that are sequentially stacked on the substrate; S2. Etch the epitaxial wafer to form a conductive step; S3. Form a first photoresist layer on the epitaxial wafer obtained in step S2; S4. Form a second photoresist layer on the first photoresist layer; S5. Expose and develop the epitaxial wafer obtained in step S4 to remove the first photoresist layer and the second photoresist layer in a preset area, forming a photoresist opening; the photoresist opening includes a first opening and a second opening arranged in sequence from bottom to top, and the side wall of the cross-section of the first opening includes at least a first arc segment and a first straight segment connected thereto; the side wall of the cross-section of the second opening includes at least a second arc segment and a second straight segment connected thereto; the included angle between the first straight segment and the surface of the epitaxial wafer is α1, the included angle between the second straight segment and the surface of the epitaxial wafer is α2, and α2 - α1 ≥ 65°; S6. Evaporate and deposit on the epitaxial wafer obtained in step S5 to form a reflective layer on the second photoresist layer and within the photoresist opening; the reflective layer includes a reflective sub-layer and a protective layer coating the reflective sub-layer; the side wall of the reflective layer within the photoresist opening forms an included angle β1 with the surface of the epitaxial wafer; S7. Evaporate and deposit on the epitaxial wafer obtained in step S6 to form a wire bonding layer on the reflective layer; the side wall of the wire bonding layer within the photoresist opening forms an included angle β2 with the surface of the epitaxial wafer, and β2 - β1 ≥ 60°; and there is a preset distance L between the side wall of the wire bonding layer within the photoresist opening and the side wall of the reflective layer within the photoresist opening, and L ≥ 2 μm; S8. Remove the first photoresist layer, the second photoresist layer, and the reflective layer and the wire bonding layer above them; S9. Form a passivation layer on the epitaxial wafer obtained in step S8 and form a wire bonding hole above the wire bonding layer, thus obtaining a finished high-temperature resistant LED chip.

2. The preparation method of the high-temperature resistant LED chip according to claim 1, wherein, The first photoresist layer is formed by a first photoresist, and the second photoresist layer is formed by a second photoresist; the viscosity of the first photoresist is less than that of the second photoresist; The thickness of the first photoresist layer is less than that of the second photoresist layer.

3. The manufacturing method of the high temperature resistant LED chip according to claim 2, characterized in that, The first photoresist is a negative photoresist with a viscosity of 40 - 60 cP; The second photoresist is a negative photoresist with a viscosity of 80 - 100 cP; The thickness of the first photoresist layer is 1 / 3 - 1 / 2 of the thickness of the second photoresist layer.

4. The preparation method of the high-temperature resistant LED chip according to claim 1, characterized in that, The reflective sub-layer is an Al layer with a thickness of 1200 - 3000 Å; The protective layer includes a Ti layer, a first Pt layer, a Ni layer, and a second Pt layer that are sequentially stacked on the reflective sub-layer. The thickness of the Ti layer is 1000 - 2000 Å, the thickness of the first Pt layer is 500 - 1000 Å, the thickness of the Ni layer is 1000 - 2000 Å, and the thickness of the second Pt layer is 500 - 1000 Å; The wire bonding layer is an Au layer with a thickness of 15000 - 20000 Å; The passivation layer is an Al2O3 layer with a thickness of 600 - 1200 Å.

5. The preparation method of the high-temperature resistant LED chip according to claim 1, characterized in that, In step S6, when depositing the reflective layer, the metal beam current has a first angle with the surface of the epitaxial wafer. In step S7, when depositing the protective layer, the metal beam current has a second angle with the surface of the epitaxial wafer. The second angle < the first angle.

6. The manufacturing method of the high-temperature resistant LED chip according to claim 5, characterized in that, The first angle is 40° - 50°, and the second angle is 30° - 35°.

7. The preparation method of the high-temperature resistant LED chip according to claim 1, wherein, The value range of α1 is 15° - 30°, and the value range of α2 is 85° - 90°. The value range of β1 is 20° - 26°, and the value range of β2 is 80° - 88°. The value range of L is 2 - 4 μm. The thickness of the first photoresist layer is 1 - 3 μm, and the thickness of the second photoresist layer is 5 - 10 μm.

8. The preparation method of the high-temperature resistant LED chip according to claim 1, wherein, Step S5 includes: S51. Expose the epitaxial wafer obtained in step S4 for 5 - 15 s using an exposure light source with a wavelength of 280 - 350 nm, and the light intensity is 100 - 150 mJ / cm 2 ; S52. Expose the epitaxial wafer obtained in step S51 for 3 - 5 s using an exposure light source with a wavelength of 310 - 380 nm, and the light intensity is 150 - 200 mJ / cm 2 ; S53. Spraying the epitaxial wafer obtained in step S52 with a developer at a pressure of 0.5 - 0.9 bar for 30 - 40 s; wherein, the temperature of the developer is 18 - 20 °C. S54. Spraying the epitaxial wafer obtained in step S53 with a developer at a pressure of 1 - 1.3 bar for 50 - 90 s; wherein, the temperature of the developer is 25 - 28 °C. S55. Baking the epitaxial wafer obtained in step S54 at 100 - 110 °C for 40 - 100 s, then baking at 120 - 140 °C for 5 - 10 min, and finally baking at 115 - 125 °C for 5 - 10 min.

9. A high-temperature resistant LED chip, characterized in that, Prepared by the preparation method of the high-temperature resistant LED chip according to any one of claims 1 - 8.

10. A display screen, characterized in that, Including the high-temperature resistant LED chip according to claim 9.

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