Improvement of adhesion between low-k material and capping layer

Abstract

An exemplary semiconductor processing method may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber. A semiconductor substrate may be disposed within the processing region. The method may include forming a low dielectric constant material layer on a semiconductor substrate. The method may include purifying one or more treatment regions where precursors are deposited. The plasma power is maintained at less than or about 750 W while purifying the treatment region. The method may include forming an interface layer on a low dielectric constant material layer. The method may include forming a capping layer on an interface layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority under patent law to U.S. patent application No. 17 / 896,716, filed on August 26, 2022, entitled "ADHESION IMPROVEMENT BETWEEN LOW-K MATERIALS AND CAP LAYERS," which is incorporated herein by reference in its entirety. Technical Field

[0002] The present technology relates to semiconductor processing and materials, and more particularly to improving adhesion between low dielectric constant materials and capping layers. Background Art

[0003] Integrated circuits are made through processes that produce intricately patterned layers of material on a substrate surface. Producing patterned materials on a substrate requires controlled methods for forming and removing materials. Material properties can affect the operation of the device and can also affect how films are removed relative to each other. Plasma enhanced deposition can produce films with certain properties. The desired properties in a film may vary depending on its application.

[0004] Therefore, there is a need for improved systems and methods that can be used to produce high quality devices and structures. The present technology can meet these and other needs. Summary of the invention

[0005] An exemplary semiconductor processing method may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber. A semiconductor substrate may be disposed within the processing region. The method may include forming a low dielectric constant material layer on the semiconductor substrate. The method may include purging the processing region of the one or more deposition precursors. Maintaining a plasma power of less than or about 750 W while purging the processing region. The method may include forming an interface layer on the low dielectric constant material layer. The method may include forming a cap layer on the interface layer.

[0006] In some embodiments, during a semiconductor processing method, a semiconductor substrate may be maintained at a temperature of less than or about 550°C. The method may include: purifying a processing area of ​​one or more deposition precursors. Maintaining a plasma power of less than or about 750W while purifying the processing area. The method may include: interrupting the flow of one or more deposition precursors before forming the interface layer. The method may include: providing an oxygen-containing precursor to the processing area before forming the interface layer. The flow rate of the oxygen-containing precursor may be less than or about 750sccm. The method may include: densifying a low dielectric constant material layer while purging a processing area of ​​one or more deposition precursors. The adhesion value between the low dielectric constant material layer and the cap layer may be greater than or about 3.0J / m 2 .

[0007] Some embodiments of the present technology may include semiconductor processing methods. The method may include: forming a low dielectric constant material layer on a semiconductor substrate, the substrate being disposed in a processing region of a semiconductor processing chamber. The plasma power may be maintained at a first plasma power level while the low dielectric constant material layer is formed. The method may include: purifying the processing region. The plasma power may be maintained at a second plasma power level while the processing region is purged. The second plasma power level may be less than or equal to the first plasma power level. The method may include: forming an interface layer on the low dielectric constant material layer. The method may include: forming a cap layer on the interface layer.

[0008] In some embodiments, the semiconductor substrate may include silicon. The low dielectric constant material layer may be formed by plasma enhanced chemical vapor deposition. The interface layer may be characterized by lower methyl incorporation than the low dielectric constant material layer. The method may include providing molecular oxygen to the processing area while purging the processing area. The method may include reducing the flow rate of one or more precursors used to form the low dielectric constant material layer before purging the processing area. While forming the interface layer, the temperature and pressure in the processing area when forming the low dielectric constant material layer may be maintained. The method may include reducing the flow rate of the carrier gas before purging the processing area.

[0009] Some embodiments of the present technology include semiconductor structures. The structure may include a semiconductor substrate. The structure may include: a low dielectric constant material layer disposed on the semiconductor substrate. The structure may include: a cap layer formed above the low dielectric constant material layer. The structure may include: an interface layer disposed between the low dielectric constant material layer and the cap layer. The adhesion value between the low dielectric constant material layer and the cap layer is greater than or about 4.0 J / m 2 .

[0010] In some embodiments, the interface layer may be a portion of the low dielectric constant material layer. The interface layer may be characterized by lower methyl incorporation than the low dielectric constant material layer. The interface layer may be characterized by higher oxygen concentration than the low dielectric constant material layer.

[0011] Such techniques can provide many benefits over conventional systems and techniques. For example, such processes and structures can form an interface layer between the low dielectric constant material and the cap layer. In addition, the formation of the interface layer can substantially not affect device performance while increasing the adhesion between the low dielectric constant material and the cap layer. The increased adhesion can reduce and / or eliminate the possibility of the cap layer delaminating from the low dielectric constant material during subsequent processing. These and other embodiments and their many advantages and features are described in more detail in conjunction with the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The nature and advantages of the technology disclosed in this article can be further understood by referring to the remaining parts of the specification and the drawings.

[0013] Figure 1 A top plan view of an exemplary processing system in accordance with some embodiments of the present technology is shown.

[0014] Figure 2 A schematic cross-sectional view of an exemplary plasma system according to some embodiments of the present technology is shown.

[0015] Figure 3 Selected operations in a method of forming according to some embodiments of the present technology are shown.

[0016] FIG. 4A to FIG. 4C The figures illustrate exemplary schematic cross-sectional structures in which material layers are included and produced according to some embodiments of the present technology.

[0017] Several drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes only and should not be considered to be drawn to scale unless otherwise specified. In addition, as schematic diagrams, the drawings are used to aid understanding and may not include all aspects or information compared to realistic representations and may include exaggerated material for illustrative purposes.

[0018] In the accompanying drawings, similar components and / or features may have the same reference numeral. In addition, components of the same type may be distinguished by adding a letter after the reference numeral that distinguishes the similar components. If only the first reference numeral is used in the specification, the description applies to any similar component having the same first reference numeral regardless of the letter. DETAILED DESCRIPTION

[0019] During back-end-of-line (BEOL) semiconductor processing, low-k films can perform a variety of functions in the fabrication of metallization layers in integrated circuits. These functions can include bonding electrically insulating low-k films between conductive metal-containing structures, such as interconnects, contact holes, and vias. They can also include partially removing low-k films after the formation of metal structures. A common removal process in BEOL processing is chemical mechanical polishing (CMP), which uses a combination of chemical etching and physical abrasion to remove low-κ materials from the surface of a substrate. In some applications, a capping layer can be formed over the low-k film to further protect the low-k film.

[0020] However, capping layers may face many problems that may be exacerbated as feature sizes are reduced. For example, capping layers may make it difficult to adhere to the underlying low-k materials. In addition, during BEOL processing, capping layers may delaminate and / or separate from the low-k film. Due to these and other problems, conventional techniques are limited in their ability to further reduce feature sizes or prevent capping layers from delaminating from low-k films.

[0021] The present technique overcomes these problems by subjecting the low dielectric constant film to post-deposition processing. Multiple operations can process the deposited low dielectric constant film together or separately to form an interfacial layer, which can be part of the low dielectric constant film and more easily adhere to the cap layer. In addition, the processing can be performed in the same chamber as the deposition, avoiding the need to break the vacuum or expose the structure to the atmosphere. Finally, the processing does not substantially affect the underlying low dielectric constant film, thereby maintaining the integrity of the previously formed structure.

[0022] Although the remainder of the disclosure will routinely identify specific deposition processes and post-deposition treatments that utilize the disclosed techniques, and will describe one type of semiconductor processing chamber, it will be readily understood that the treatments are equally applicable to other deposition chambers, and that the treatments may be performed in any number of semiconductor processing chambers. Therefore, the techniques should not be viewed as limited to techniques for use with only these specific deposition processes or chambers. Prior to describing semiconductor processing methods in accordance with the present technique, the present disclosure will discuss one possible chamber that may be used to perform treatments in accordance with embodiments of the present technique.

[0023] Figure 1A top plan view of one embodiment of a processing system 100 of deposition, etching, baking and hardening chambers according to an embodiment is shown. In the figure, a pair of front start standard chambers 102 supply substrates of various sizes, which are received by a robot 104 and placed into a low pressure holding area 106, and then placed into one of the substrate processing chambers 108a to 108f, which are arranged in series blocks 109a to 109c. A second robot 110 can be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a to 108f and back. Each substrate processing chamber 108a to 108f can be equipped to perform a number of substrate processing operations, including the formation of stacks of semiconductor materials described herein, as well as plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation and other substrate processing (including annealing, ashing, etc.).

[0024] The substrate processing chambers 108a to 108f may include one or more system components for depositing, annealing, hardening and / or etching dielectric or other films on a substrate. In one configuration, two pairs of processing chambers (e.g., 108c and 108d and 108e and 108f) may be used to deposit dielectric materials on a substrate, and a third pair of processing chambers (e.g., 108a and 108b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a to 108f) may be configured to deposit alternating stacks of dielectric films on a substrate. Any one or more of the described processes may be performed in separate chambers of the manufacturing system shown in different embodiments. It will be appreciated that other configurations of chambers for deposition, etching, annealing and hardening of dielectric films are contemplated.

[0025] Figure 2 A schematic cross-sectional view of an exemplary plasma system 200 according to some embodiments of the present technology is shown. The plasma system 200 can illustrate a pair of processing chambers 108 that can be installed in one or more tandem blocks 109 described above and can include a lid stack component according to embodiments of the present technology and further explained below. The plasma system 200 can generally include a chamber body 202 having a sidewall 212, a bottom wall 216, and an inner sidewall 201 that define a pair of processing regions 220A and 220B. Each processing region 220A-220B can be configured in a similar manner and each processing region 220A-220B can include the same components.

[0026] For example, the processing region 220B (components of which may also be included in the processing region 220A) may include a pedestal 228 disposed in the processing region through a passage 222 formed in the bottom wall 216 of the plasma system 200. The pedestal 228 may provide a heater adapted to support a substrate 229 on an exposed surface of the pedestal (e.g., a body portion). The pedestal 228 may include a heating element 232 (e.g., a resistive heating element) that may heat and control the temperature of the substrate at a desired processing temperature. The pedestal 228 may also be heated by a remote heating element such as a lamp assembly or any other heating element.

[0027] The body of the pedestal 228 may be coupled to the shaft 226 by the flange 233. The shaft 226 may electrically couple the pedestal 228 to the power output or power box 203. The power box 203 may include a drive system that controls the lifting and movement of the panel pedestal 228 within the processing area 220B. The shaft 226 may also include an electrical power interface to provide power to the pedestal 228. The power box 203 may also include an interface for power and temperature indicators, such as a thermal coupling interface. The shaft 226 may include a base assembly 238 suitable for removably coupling the power box 203. A circumferential ring 235 is shown above the power box 203. In some embodiments, the circumferential ring 235 may be a shoulder suitable for acting as a mechanical stop, or a platform configured to provide a mechanical interface between the base assembly 238 and the upper surface of the power box 203.

[0028] A rod 230 may be included that passes through a channel 224 formed in the bottom wall 216 of the processing region 220B, and the rod 230 may be utilized to position substrate lift pins 261 disposed through the body of the pedestal 228. The substrate lift pins 261 may selectively separate the substrate 229 from the pedestal to facilitate exchanging the substrate 229 using a robot that transfers the substrate 229 into and out of the processing region 220B via the substrate transfer port 260.

[0029] The chamber lid 204 can be coupled to the top portion of the chamber body 202. The lid 204 can house one or more precursor distribution systems 208 coupled to the lid 204. The precursor distribution system 208 can include a precursor inlet channel 240 that can deliver reactants and cleaning precursors to the processing region 220B via a dual channel showerhead 218. The dual channel showerhead 218 can include an annular base plate 248 having a baffle plate 244 disposed in the middle of a face plate 246. A radio frequency ("RF") source 265 can be coupled to the dual channel showerhead 218, and the RF source 265 can power the dual channel showerhead 218 to help generate a plasma region between the face plate 246 and the pedestal 228 of the dual channel showerhead 218. The dual channel showerhead 218 and / or the faceplate 246 may include one or more openings to allow precursors to flow from the precursor distribution system 208 to the processing regions 220A and / or 220B. In some embodiments, the openings may include at least one of a straight-shaped opening and a conical opening. In some embodiments, the RF source may be coupled to other portions of the chamber body 202, such as the pedestal 228, to facilitate plasma generation. A dielectric insulator 258 may be disposed between the lid 204 and the dual channel showerhead 218 to prevent RF power from being conducted to the lid 204. A shield ring 206 may be disposed on the periphery of the pedestal 228, with the shield ring 206 being coupled to the pedestal 228.

[0030] An optional cooling channel 247 may be formed in the annular base plate 248 of the precursor distribution system 208 to cool the annular base plate 248 during operation. A heat transfer fluid (such as water, glycol, gas, etc.) may be circulated through the cooling channel 247 so that the base plate 248 may be maintained at a predetermined temperature. The liner assembly 227 may be disposed in the processing region 220B adjacent to the sidewalls 201, 212 of the chamber body 202 to prevent the sidewalls 201, 212 from being exposed to the processing environment in the processing region 220B. The liner assembly 227 may include a circumferential pumping chamber 225 that may be coupled to a pumping system 264 that is configured to exhaust gases and byproducts from the processing region 220B and control the pressure in the processing region 220B. A plurality of exhaust ports 231 may be formed on the liner assembly 227. Exhaust port 231 may be configured to allow gas to flow from processing region 220B to circumferential pumping chamber 225 in a manner that facilitates processing within system 200 .

[0031] Although plasma-processing chambers may be used for one or more aspects of film processing according to the present technology, in some embodiments, carbon films may not be formed using plasma enhanced processing. Using plasma may limit the conformality of the film produced by further liberating carbon from the precursor, and this may limit carbon incorporation in the film produced by allowing carbon to recombine with other radical species and flow out of the chamber. In some embodiments, the present technology may form a film at least without generating a plasma. Figure 3 Operations of an exemplary method 300 of semiconductor processing according to some embodiments of the present technology are illustrated. The method may be performed in a variety of processing chambers, including the semiconductor processing system 200 described above, as well as any other chamber in which plasma deposition may be performed. The method 300 may include several optional operations that may or may not be specifically associated with some embodiments of the method according to the present technology. It should be understood that the method 300 may be performed on any number of semiconductor structures or substrates, including FIG. 4A to FIG. 4C The exemplary structure 400 or substrate 405 is shown, wherein a material layer may be formed on the structure 400 or substrate 405. It should be understood that FIG. 4A to FIG. 4C Only partial schematics are shown, and the substrate may contain any number of structural blocks having the aspects shown in the figures, as well as alternative structural aspects that may still benefit from operation of the present technology.

[0032] As shown, method 300 may include several optional operations that may or may not be specifically associated with some embodiments of methods according to the present technology. For example, many operations are described to provide a wider range of structure formation, but these operations are not critical to the technology or can be performed by alternative methods that will be further described below. As discussed above, method 300 may describe FIG. 4A to FIG. 4C The operations schematically shown in FIG. 3 will be described with reference to the operations of method 300. FIG. 4A to FIG. 4C .

[0033] Prior to the first operation of method 300, substrate 405 may be processed in one or more ways before being placed into a processing region of a semiconductor processing system in which method 300 may be performed. Some or all of these operations may be performed in the chambers or systems described above, or may be performed in different chambers on the same system tool, which may include a semiconductor processing chamber in which method 300 may be performed.

[0034] The method may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber at operation 305. A substrate 405 may be disposed within the processing region of the semiconductor processing chamber. In an embodiment, the substrate 405 may have a substantially flat surface or an uneven surface. The substrate may be a material such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, silicon on insulator, carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, or sapphire. The substrate 405 may have various sizes, such as 200 mm or 300 mm diameter wafers, as well as rectangular or square panels.

[0035] One or more deposition precursors may include a silicon-containing precursor. The silicon-containing precursor that can be used in the deposition may be any number of silicon-containing precursors, or include any number of silicon-containing precursors. The silicon-containing precursor may be any conventional semiconductor processing silicon compound used to form a silicon-containing material. For example, the silicon-containing precursor may be a cyclic precursor, a linear precursor, a Si—O—Si precursor, or a Si—C—Si precursor. Exemplary cyclic precursors may include, but are not limited to: octamethylcyclotetrasiloxane, 2,4,6,8-tetramethyl-2,4,6,8-tetravinylcyclotetrasiloxane, or 2,4,6,8-tetramethylcyclotetrasiloxane. Example linear precursors may include, but are not limited to: dimethyldimethoxysilane, ethoxydimethylsilane, isobutylmethyldimethoxysilane, or vinylmethyldimethoxysilane. Exemplary Si—O—Si precursors may include, but are not limited to: 1,1,3,3-tetramethyl-1,3-dimethoxydisiloxane, or 1,3-dimethyl-1,1,3,3-tetramethoxydisiloxane. Exemplary Si—C—Si precursors may include, but are not limited to: methoxy(dimethyl)silylmethane, or methyl(dimethoxy)silylmethane.

[0036] The flow rate of the silicon-containing precursor to a processing region of a semiconductor processing chamber may be less than or about 2,500 mg / min, and may be less than or about 2,250 mg / min, less than or about 2,000 mg / min, less than or about 1,750 mg / min, less than or about 1,500 mg / min, less than or about 1,400 mg / min, less than or about 1,300 mg / min, less than or about 1,200 mg / min, less than or about 1,100 mg / min, less than or about 1,000 mg / min, less than or about 900 mg / min, less than or about 800 mg / min, less than or about 700 mg / min, less than or about 600 mg / min, less than or about 500 mg / min, less than or about 400 mg / min, less than or about 300 mg / min, less than or about 200 mg / min, or less.

[0037] In addition to the silicon-containing precursor, an oxygen-containing precursor may also be provided to the processing region of the semiconductor processing chamber. The flow rate of the oxygen-containing precursor to the processing region of the semiconductor processing chamber may be less than or about 1,000 sccm, and may be less than or about 900 sccm, less than or about 800 sccm, less than or about 700 sccm, less than or about 600 sccm, less than or about 500 sccm, less than or about 450 sccm, less than or about 400 sccm, less than or about 350 sccm, less than or about 300 sccm, less than or about 250 sccm, less than or about 200 sccm, less than or about 150 sccm, less than or about 100 sccm, or less. In an embodiment, the oxygen-containing precursor may be molecular oxygen (O2) or may include molecular oxygen (O2).

[0038] In some embodiments, in addition to the silicon-containing precursor and the oxygen-containing precursor (if present), additional precursors may be provided. For example, the deposition precursors may also include one or more carrier gases, such as helium (He), nitrogen (N2), and argon (Ar). Although the one or more carrier gases may be delivered with the other deposition precursors, the carrier gases may be considered inert gases that do not react to form part of the deposited low dielectric constant material 410.

[0039] At operation 310, method 300 may include forming a low dielectric constant material 410. Low dielectric constant material 410 may be formed covering substrate 405. Low dielectric constant material 410 may include, but is not limited to, oxide materials such as silicon oxide, or doped oxides with fluorine, carbon, or other low-k materials that may be used for processing. In an embodiment, the low dielectric constant material may be characterized by Si—O—Si bonding. The low dielectric constant material may be characterized by a dielectric constant of less than or about 6.0, less than or about 5.5, less than or about 5.0, less than or about 4.5, less than or about 4.0, less than or about 3.5, less than or about 3.0, less than or about 2.7, less than or about 2.5, less than or about 2.3, or less.

[0040] The low dielectric constant material may be formed by various deposition methods, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or any other deposition method. In an embodiment, a low dielectric constant material layer may be formed by plasma enhanced chemical vapor deposition. A plasma may be formed at a plasma power of less than or about 1,500 W. A plasma may be formed at a plasma power of less than or about 1,400 W, less than or about 1,300 W, less than or about 1,200 W, less than or about 1,100 W, less than or about 1,000 W, less than or about 900 W, less than or about 800 W, less than or about 700 W, less than or about 600 W, less than or about 500 W, less than or about 400 W, less than or about 300 W, or less. When the low dielectric constant material layer 410 is formed by plasma enhanced chemical vapor deposition, the material may contain a large number of methyl groups (—CH3 groups). The methyl groups may reduce adhesion between the low dielectric constant material 410 and subsequent materials (eg, a capping layer) formed on the low dielectric constant material 410. Therefore, the method 300 may include a post-deposition treatment to increase adhesion between the low dielectric constant material 410 and subsequent materials formed on the low dielectric constant material 410.

[0041] The temperature in the semiconductor processing chamber can be maintained at less than or about 550° C. while forming the low dielectric constant material layer 410. For example, the temperature in the semiconductor processing chamber can be maintained at less than or about 525° C., such as less than or about 500° C., less than or about 475° C., less than or about 450° C., less than or about 425° C., less than or about 400° C., less than or about 375° C., less than or about 350° C., less than or about 325° C., less than or about 300° C., less than or about 275° C., less than or about 250° C., less than or about 225° C., or lower while forming the material layer.

[0042] The pressure in the semiconductor processing chamber can be maintained at less than or about 100 Torr while forming the low dielectric constant material layer 410. For example, the pressure in the semiconductor processing chamber can be maintained at less than or about 90 Torr, such as less than or about 80 Torr, less than or about 70 Torr, less than or about 60 Torr, less than or about 50 Torr, less than or about 40 Torr, less than or about 30 Torr, less than or about 20 Torr, less than or about 15 Torr, less than or about 12.5 Torr, less than or about 10 Torr, less than or about 9 Torr, less than or about 8 Torr, or less while forming the material layer.

[0043] At optional operation 315, method 300 may include reducing or interrupting the flow of a deposition precursor, such as a silicon-containing precursor, an oxygen-containing precursor, and / or any carrier gas or inert precursor. In some embodiments, method 300 may alternatively include reducing the flow of a deposition precursor. For example, the flow rate of the silicon-containing precursor may be reduced to less than or about 100 mg / min, less than or about 90 mg / min, less than or about 80 mg / min, less than or about 70 mg / min, less than or about 60 mg / min, less than or about 50 mg / min, less than or about 40 mg / min, less than or about 30 mg / min, less than or about 20 mg / min, less than or about 10 mg / min, or less. Reducing the flow rate of the silicon-containing precursor may reduce the amount of deposition that occurs and allow processing of an existing low dielectric constant material layer 410.

[0044] While or after reducing or interrupting the flow of the deposition precursors, the processing area of ​​the semiconductor processing chamber may be purged at optional operation 320. Therefore, the flow rate of the carrier gas and / or the inert gas may be maintained to purge the one or more deposition precursors of the processing area. However, it may be considered to maintain and / or reduce the flow rate of the carrier gas and / or the inert gas. During the purge, a plasma power may be provided. The plasma power may increase the bombardment of the carrier gas and / or the inert gas to the deposited low dielectric constant material 410. While purging the one or more deposition precursors of the processing area, the bombardment may densify the low dielectric constant material layer 410. In an embodiment, the plasma power at operations 315 to 320 may be reduced from the plasma power level maintained during deposition to reduce the bombardment of the carrier gas and prevent any sputtering or damage to the film. For example, the plasma power at operations 315 to 320 can be maintained at less than or about 700 W, less than or about 600 W, less than or about 500 W, less than or about 400 W, less than or about 300 W, less than or about 200 W, less than or about 100 W, less than or about 75 W, or less.

[0045] At optional operation 325, method 300 may include providing an oxygen-containing precursor to the processing region. That is, in some embodiments, the oxygen-containing precursor may be provided while purging the processing region of other deposition precursors. By providing the oxygen-containing precursor while purging the processing region, the upper surface of the low dielectric constant material layer 410 opposite to the substrate 405 may be treated with the oxygen-containing precursor and / or the oxygen-containing plasma effluent. The oxygen-containing precursor and / or the oxygen-containing plasma effluent may reduce the amount of methyl groups at the upper surface of the low dielectric constant material layer 410 and increase the oxygen concentration in the low dielectric constant material layer 410, thereby forming an interfacial layer 415 (e.g., a dielectric layer 415) on the low dielectric constant material layer at operation 330. Figure 4B). The interface layer 415 may be an upper portion of the low dielectric constant material 410. It is contemplated that the terminal methyl groups at the upper surface of the low dielectric constant material layer 410 may be treated to replace the methyl groups with oxygen-containing groups (such as -CH2OH, -CHO and / or -COOH, etc.), which may increase adhesion to subsequently formed materials. As further described below, oxygen-containing groups (such as -CH2OH, -CHO and / or -COOH, etc.) may more easily interface and / or bond with a capping layer formed above the low dielectric constant material 410.

[0046] In other embodiments, method 300 may not include purging the process area at optional operation 320 and / or reducing or interrupting the flow of the deposition precursor at optional operation 315. Instead, one or more deposition precursors, such as silicon-containing precursors and / or oxygen-containing precursors, may be continuously provided. However, it is conceivable to modify the flow rate of one or more deposition precursors. For example, the flow rate of the silicon-containing precursor may be maintained or reduced while maintaining or increasing the flow rate of the oxygen-containing precursor. When the flow rate of the silicon-containing precursor is reduced, the low dielectric constant material layer 410 may be treated in a manner similar to the previously discussed method of providing an oxygen-containing precursor while purging the process area, thereby forming an interface layer 415 on the low dielectric constant material layer 410. Specifically, the low dielectric constant material layer 410 may be treated with an oxygen-containing precursor and / or an oxygen-containing plasma effluent to reduce the amount of methyl groups and / or increase the oxygen concentration at the top surface of the low dielectric constant material layer 410. On the contrary, if the flow rate of the silicon-containing precursor is maintained or only slightly reduced, an oxygen-rich silicon oxide material may be formed on the low dielectric constant material layer 410 as the interface layer 415. The oxygen-rich material may lead to better adhesion with subsequently formed oxygen-containing materials (eg, oxygen-containing capping layer).

[0047] The operations of method 300, such as operations 310 and 330, may be formed under the same or similar process conditions. For example, the temperature and / or pressure may be maintained for both the formation of the low dielectric constant material layer 410 and the formation of the interface layer 415. Conversely, the temperature and / or pressure may be modified or adjusted between the formation of the low dielectric constant material layer 410 and the formation of the interface layer 415. However, in an embodiment, the plasma power may be reduced from a first plasma power level when forming the low dielectric constant material layer 410 to a second plasma power level lower than the first plasma power level when forming the interface layer 415 (as discussed above). As discussed above, the reduction in the plasma power level may protect the low dielectric constant material layer 410 and not damage the material.

[0048] like Figure 4CAs shown, after forming the interface layer 415, a capping layer 420 may be formed at operation 335. The capping layer 420 may be an oxide capping layer, such as a layer formed of a silicon and oxygen-containing material (e.g., tetraethyl orthosilicate or TEOS). The capping layer 420 may also be an anti-reflective coating, such as a dielectric anti-reflective coating. The anti-reflective coating may be a silicon oxide film. The anti-reflective coating may additionally include carbon and / or nitrogen. In conventional operations, an interface layer may not be formed, and adhesion problems between the two films may result in delamination of the capping layer from the low dielectric constant material layer. For example, in the absence of an interface layer, the adhesion value of the low dielectric constant material layer to the capping layer may be less than 3.0 J / m 2 However, by forming the interface layer 415 according to the embodiments of the present disclosure, the adhesion value between the low dielectric constant material layer 410 and the cap layer 420 through the interface layer 415 can be greater than or about 3.0 J / m 2 The adhesion layer may be greater due to the oxygen concentration in the interface layer 415, which may more easily interact with the oxygen in the cap layer 420. In an embodiment, the adhesion value may be greater than or about 3.5 J / m 2 , greater than or about 4.0 J / m 2 , greater than or about 4.5 J / m 2 , greater than or about 5.0 J / m 2 , greater than or about 5.5 J / m 2 , greater than or about 6.0 J / m 2 or greater. These adhesion values ​​(such as greater than 3.0 J / m 2 The adhesion value of 410 may indicate sufficient adhesion between the low dielectric constant material layer 410 and the capping layer 420 such that minimal or zero delamination may occur during subsequent processing.

[0049] Figure 4C A final structure 400 that can be formed according to method 300 is shown. Structure 400 can include any of the features discussed above with reference to method 300. For example, structure 400 can include a semiconductor substrate 405. Structure 400 can include: a low dielectric constant material layer 410 disposed on semiconductor substrate 405. Structure 400 can include: a cap layer 420 formed over low dielectric constant material layer 410. Structure 400 can include: an interface layer 415 disposed between low dielectric constant material layer 410 and cap layer 420. As discussed, the adhesion value between low dielectric constant material layer 410 and cap layer 420 can be greater than or about 4.0 J / m 2 .

[0050] In an embodiment, the interface layer 415 may be a portion of the low dielectric constant material layer 410. For example, an upper portion of the low dielectric constant material 410 may be processed to form the interface layer 415. Alternatively, the interface layer 415 may be an oxygen-rich material formed clearly above the low dielectric constant material layer 410. In an embodiment, the interface layer 415 may be characterized by lower methyl incorporation and / or higher oxygen concentration than the low dielectric constant material layer 410.

[0051] By utilizing one or more of the described processes, controlled and discrete material formation can be provided, resulting in improved material layers, and thus a structure 400 can be provided, wherein one layer (e.g., low dielectric constant material layer 410) can be treated to form an interface layer 415, which can improve adhesion between the low dielectric constant material layer 410 and the cap layer 420, all in the same chamber without exposing the structure to the atmosphere. Thus, the present technique can provide an improved structure, which can produce a structure with improved adhesion between the low dielectric constant material and the cap layer compared to conventional techniques.

[0052] In the foregoing description, for the purpose of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0053] After several embodiments have been disclosed, those of ordinary skill in the art will recognize that various modifications, alternative configurations, and equivalents may be used without departing from the spirit of the embodiments. In addition, in order to avoid unnecessary confusion of the present technology, several well-known processes and elements are not described. Therefore, the above description should not be considered to limit the scope of the present technology. In addition, methods or processes may be described as being performed sequentially or in steps, but it should be understood that the operations may be performed simultaneously or in an order different from the order listed.

[0054] In the case of providing a range of values, unless otherwise expressly specified herein, it is understood that each intermediate value between the upper and lower limits of that range is also specifically disclosed, with an accuracy to the smallest quantile of the lower limit unit. Any narrower range between any stated value or unstated intermediate value in the stated range and any other stated value or intermediate value in that stated range will be included. The upper and lower limits of such smaller ranges may be independently included in the range or excluded from the range, and each range in which any one, no one, or both limits are included in the smaller range is also included in the present technology, and each range is governed by any specific excluded limits in the stated range. In the case where the stated range includes one or both of the limitations, the range excluding one or both of the limitations included is also included.

[0055] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a deposition precursor" includes a plurality of such precursors, and reference to "the low dielectric constant material layer" includes reference to one or more low dielectric constant material layers and equivalents thereof known to those of ordinary skill in the art, and so forth.

[0056] Furthermore, when the words “comprise,” “comprising,” “contain,” “include,” and “including” are used in the specification and the claims below, they are intended to specify the presence of stated features, integers, components, or operations, but the words do not exclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

Claims

1. A semiconductor processing method comprising the following steps: providing one or more deposition precursors to a processing region of a semiconductor processing chamber, wherein a semiconductor substrate is disposed within the processing region; forming a low dielectric constant material layer on the semiconductor substrate; forming an interface layer on the low dielectric constant material layer; as well as A capping layer is formed on the interface layer.

2. The semiconductor processing method of claim 1, wherein the semiconductor substrate is maintained at a temperature of less than or about 550°C during the semiconductor processing method.

3. The semiconductor processing method according to claim 1, further comprising the following steps: The processing region is purged of the one or more deposition precursors, wherein a plasma power is maintained at less than or about 750 W while purging the processing region.

4. The semiconductor processing method according to claim 1, further comprising the following steps: Prior to forming the interfacial layer, the flow of the one or more deposition precursors is interrupted.

5. The semiconductor processing method according to claim 1, further comprising the steps of: Before forming the interface layer, an oxygen-containing precursor is provided to the processing region.

6. The semiconductor processing method of claim 5, wherein the flow rate of the oxygen-containing precursor is less than or about 750 seem.

7. The semiconductor processing method according to claim 1, further comprising the steps of: The layer of low dielectric constant material is densified while purging the processing region of the one or more deposition precursors.

8. The semiconductor processing method of claim 1, wherein the adhesion value between the low dielectric constant material layer and the cap layer is greater than or about 3.0 J / m 2 .

9. A semiconductor processing method comprising the following steps: forming a layer of low dielectric constant material on a semiconductor substrate disposed in a processing region of a semiconductor processing chamber, wherein plasma power is maintained at a first plasma power level while forming the layer of low dielectric constant material; purging the processing region, wherein the plasma power is maintained at a second plasma power level while purging the processing region, and wherein the second plasma power level is less than or equal to the first plasma power level; forming an interface layer on the low dielectric constant material layer; and A capping layer is formed on the interface layer.

10. The semiconductor processing method of claim 9, wherein the semiconductor substrate comprises silicon.

11. The semiconductor processing method according to claim 9, wherein the low dielectric constant material layer is formed by plasma enhanced chemical vapor deposition.

12. The semiconductor processing method of claim 9 wherein said interfacial layer is characterized by lower methyl incorporation than said low dielectric constant material layer.

13. The semiconductor processing method of claim 9, further comprising the steps of: Molecular oxygen is provided to the processing region while purging the processing region.

14. The semiconductor processing method of claim 9, further comprising the steps of: Prior to purging the processing region, a flow rate of one or more precursors used to form the low dielectric constant material layer is reduced. 15 . The semiconductor processing method according to claim 9 , wherein while forming the interface layer, the temperature and pressure in the processing region when forming the low dielectric constant material layer are maintained.

16. The semiconductor processing method of claim 9, further comprising the steps of: Prior to purging the process region, the flow rate of the carrier gas is reduced.

17. A semiconductor structure comprising: Semiconductor substrates; A low dielectric constant material layer is disposed on the semiconductor substrate; a capping layer formed on the low dielectric constant material layer; and An interface layer is disposed between the low dielectric constant material layer and the cover layer, wherein the adhesion value between the low dielectric constant material layer and the cover layer is greater than or about 4.0 J / m 2 . The semiconductor structure of claim 17 , wherein the interface layer is a portion of the low dielectric constant material layer.

19. The semiconductor structure of claim 17 wherein said interfacial layer is characterized by lower methyl incorporation than said low dielectric constant material layer.

20. The semiconductor structure of claim 17 wherein said interfacial layer is characterized by a higher oxygen concentration than said low dielectric constant material layer.

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