Dynamically controlling secondary switches to achieve zero voltage switching

Abstract

Zero voltage switches using secondary switches (e.g., synchronous rectifiers) are described herein. The method allows the secondary side controller to calculate the required secondary switch hold time. By measuring the forward pin voltage while the primary switch is conducting, the required secondary switch hold time can be determined without the need for primary-to-secondary communication.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 391,082, filed on July 21, 2022, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present invention relates to zero voltage switching (zero voltage switching) using a secondary switch, and more particularly, to achieving zero voltage switching in a flyback converter using a secondary switch. Background Art

[0004] Many electronic devices, such as cell phones, laptop computers, etc., are powered by direct current (dc) power from a power source. Conventional wall sockets typically deliver high voltage alternating current (ac) power that needs to be converted to regulated dc power to be used as a power source for consumer electronic devices. Switched mode power converters, also known as switched mode power supplies (SMPS), are widely used due to their high efficiency, small size, and low weight.

[0005] Many electronic devices have multiple loads and require more than one source of DC power in order to operate. For example, an audio electronic device may have a system component that operates at five volts and an audio component that operates between twelve and twenty volts. In these applications, a multi-output power converter converts AC power to multiple DC power outputs to provide regulated DC power to each of the multiple loads (i.e., system components and audio components). In some applications, the regulated DC power output is a regulated constant current (CC) output and / or a regulated constant voltage (CV) output. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Non-limiting and non-exhaustive embodiments of dynamically controlling a secondary switch to achieve zero voltage switching are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0007] Figure 1A A power converter system according to a single output implementation is illustrated.

[0008] Figure 1B A power converter system according to another embodiment is illustrated.

[0009] Figure 1C A power converter system according to another embodiment is illustrated.

[0010] Figure 1D A power converter system according to another embodiment is illustrated.

[0011] Figure 1E A power converter system according to a multiple output implementation is illustrated.

[0012] Figure 1F A power converter system according to another embodiment is illustrated.

[0013] Figure 1G A power converter system according to another embodiment is illustrated.

[0014] Figure 1H A power converter system according to another embodiment is illustrated.

[0015] Figure 2A The waveforms during a switching cycle are illustrated.

[0016] Figure 2B Waveforms during a switching cycle are illustrated according to one embodiment.

[0017] Figure 2C Waveforms during a switching cycle are illustrated according to one embodiment.

[0018] Figure 2D Waveforms during a switching cycle according to another embodiment are illustrated.

[0019] Figure 3A A conceptual flow chart for zero voltage switching in a power converter system according to an embodiment is illustrated.

[0020] Figure 3B A conceptual flow chart for zero voltage switching in a power converter system according to another embodiment is illustrated.

[0021] Figure 4 Two switching cycles of a primary switch according to an embodiment are compared.

[0022] In all several views of the drawings, corresponding reference characters indicate corresponding parts. The skilled person will understand that the elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help improve the understanding of the various embodiments of the teachings herein. In addition, common but easily understood elements that are useful or necessary in commercially feasible embodiments are generally not depicted so as to less obstruct the viewing of these various embodiments of dynamically controlling the secondary switch to achieve zero voltage switching. DETAILED DESCRIPTION

[0023] In the following description, many specific details are set forth to provide a thorough understanding of dynamically controlling the secondary switch to achieve zero voltage switching. However, it will be apparent to one of ordinary skill in the art that the specific details need not be employed to practice the teachings herein. In other cases, well-known materials or methods are not described in detail to avoid obscuring the present disclosure.

[0024] References throughout this specification to "one embodiment", "anembodiment", "one example" or "an example" mean that the specific features, structures or characteristics described in conjunction with the embodiment or example are included in at least one embodiment of the (multi-output) switch-mode power converter system. Therefore, the phrases "in one embodiment", "in an embodiment", "one example" or "an example" appearing in various places throughout this specification do not necessarily all refer to the same embodiment or example. In addition, specific features, structures or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. Specific features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a logic circuit or other suitable components that provide the described functions. In addition, it should be understood that the drawings provided herewith are used for the purpose of explanation to ordinary technicians in the field, and the drawings are not necessarily drawn to scale.

[0025] In the context of the present application, when a transistor is in an "off-state" or "off", the transistor blocks current and / or substantially does not conduct current. Conversely, when a transistor is in an "on-state" or "on", the transistor is substantially capable of conducting current. By way of example, in one embodiment, the high voltage transistor comprises an N-channel metal oxide semiconductor (NMOS) field effect transistor (FET), wherein a high voltage is supported between a first terminal (drain) and a second terminal (source). In some embodiments, an integrated controller circuit can be used to drive a power switch when regulating the energy provided to a load. In addition, for the purposes of the present disclosure, "ground" or "ground potential" refers to a reference voltage or potential relative to which all other voltages or potentials of an electronic circuit or integrated circuit (IC) are defined or measured. In addition, according to power electronics theory, "power" transfer may be indicated by "energy" transfer; conversely, "energy" transfer may be indicated by "power" transfer (i.e., power is related to the rate of change of energy).

[0026] A multi-output power converter can be used to provide regulated DC power to multiple loads. The load can be a passive and / or active load, including discrete semiconductor devices, microprocessors, controllers, mixed signal circuit components, etc. When providing regulated DC power, the multi-output power converter can adjust the output current to a constant current (CC) output and / or adjust the output voltage to a constant voltage (CV) output. In addition, the system voltage can be defined relative to how the multi-output power converter provides power. For example, a multi-output power converter can provide a CC output operating at approximately fifty volts, a CV output adjusted to twelve volts, and a CV output adjusted to five volts.

[0027] Power may be transferred from the primary side to the secondary side via an energy transfer element (e.g., a transformer) according to a switching cycle. For example, the primary switch may be switched according to a switching cycle, whereby the primary winding receives input power during a portion of the switching cycle and one or more secondary windings provide power during another portion of the switching cycle. When power is transferred such that the current in the secondary side winding (i.e., the secondary current) decreases to substantially zero before the switching cycle is completed, then the operating mode may be referred to as a discontinuous conduction mode (DCM). Alternatively, when power (i.e., energy) is transferred such that the current in the secondary side winding does not decrease to zero before the switching cycle is completed, then the operating mode may be referred to as a continuous conduction mode (CCM).

[0028] Furthermore, during a single switching cycle (ie, a single switching period), power (ie, energy) may be delivered to a selected one of a plurality of outputs.

[0029] In power converters, power converter systems, multi-output (multiple output) power converters, and multi-output power converter systems, efficiency can be improved by reducing switching losses. For example, switching losses can be improved (i.e., reduced) by switching the primary switch according to a zero voltage switching (ZVS) switching cycle.

[0030] Zero voltage switching (ZVS) can advantageously reduce the voltage of the primary switch during switching. Ideally, ZVS can control the voltage on the primary switch to be substantially zero (e.g., close to zero volts) when the primary switch is turned on. For example, when the primary switch is implemented as a power field effect transistor (FET), ZVS can be achieved by controlling the drain-source voltage of the FET to become substantially zero when the FET is turned on.

[0031] Attempts to switch the primary side switch according to a ZVS cycle are limited to systems that assume primary to secondary communication. For example, based on information related to the primary switch (e.g., state condition, primary voltage, primary current), the synchronous rectifier (SR) field effect transistor (FET) may be strategically switched. Unfortunately, in modern state-of-the-art power converters and power converter systems, primary to secondary communication may not be available.

[0032] Therefore, there is a need to use ZVS in power converters and power converter systems without the constraints of primary to secondary communication.

[0033] This article describes dynamically controlling a secondary switch (e.g., synchronous rectifier and / or SR FET) to achieve zero voltage switching. The method allows the secondary side controller to calculate the required secondary switch hold time (i.e., secondary switch conduction time). By measuring the forward pin voltage when the primary switch is conducting, the required secondary switch hold time can be determined without the need for primary to secondary communication.

[0034] Figure 1A A power converter system 100 according to a single output implementation is illustrated. Power converter system 100 includes energy transfer element 102, secondary switch block 104, load circuit 106, secondary controller 108, primary controller 109, clamp 110, and primary switch 152. Energy transfer element 102 includes primary winding 112 and secondary winding 99. Secondary switch block 104 includes N-channel field effect transistor (NFET) 126.

[0035] The output power converter system 100 can be used to convert the rectified AC line voltage V IN The input power is converted and an output voltage V is provided. O1 and the secondary current I S1 Alternatively and additionally, the input power may be obtained from a high voltage power source. The load circuit 106 includes a feedback network 140, a filter capacitor C1 and a first load 142.

[0036] As illustrated, the feedback network 140, the filter capacitor C1, and the first load 142 are electrically coupled. The feedback network 140 can provide a feedback signal FB to the secondary controller 108. In steady state, Figure 1A The power converter system 100 can be configured to deliver power (eg, output voltage V O1 ) is regulated. For example, the secondary controller 108 may adjust the output voltage V based at least in part on the feedback signal FB. O1 Make adjustments.

[0037] Primary controller 109 provides a primary control signal V to a control terminal (eg, gate) of primary switch 152. CS In this way, the primary controller 109 controls the primary current I SW The primary sensing element 54 can provide a sensing signal SENS to the primary controller to locally regulate the primary current I SW In addition, the clamp 110 can be connected in parallel with the primary winding 112 to limit (ie, clamp) the switch voltage V SW As illustrated, the primary controller 109 may be configured to use a signal (eg, a switch voltage V SW and the primary control signal V CS ) to perform the operation.

[0038] As discussed above, secondary controller 108 may receive feedback signal FB1 from load circuit 106 (ie, from feedback network 140 ). Additionally, as illustrated, secondary controller 108 may communicate with primary controller 109 via signal FL.

[0039] The power converter system 100 can be configured as a flyback converter, whereby the primary switch 152 undergoes switching according to a switching cycle. Thus, during the switching cycle, energy can be transferred via the secondary current I on the circuit path 115. S1 To transfer.

[0040] According to the teachings herein, secondary controller 108 may include a zero voltage switching (ZVS) on-time calculator 153. Secondary controller 108 may calculate a holding time (i.e., on-time) for controlling a secondary switch (e.g., a synchronous rectifier (SR)) during a switching cycle (i.e., a switching cycle of primary switch 152).

[0041] The theory of operation and equations associated with the ZVS on-time calculator 153 may be based at least in part on an oscillating (i.e., ringing) behavior at the primary node NSW, where the primary switch 152 is electrically coupled to the primary winding 112. According to switch-mode power supply theory, ringing (i.e., oscillation) may occur at the primary node NSW, which is at least partially due to the primary capacitance Cpri and the primary inductance Lpri at the primary node NSW. The resonant oscillation period (i.e., ringing period) may generally be referred to as an idle ringing period TIR.

[0042] The primary capacitance Cpri may include the capacitance of the primary switch 152. For example, when the primary switch 152 is implemented using an N-channel field effect transistor (NFET), the primary capacitance Cpri may include the capacitance associated with the NFET output capacitance.

[0043] The primary inductance Lpri may include the inductance associated with the primary winding 112. For example, it may include the magnetizing inductance of the primary winding.

[0044] From circuit theory, a simple approximation relating the idle ringing period TIR to the primary capacitance Cpri and the primary inductance Lpri can be given by equation EQ.1.

[0045]

[0046] According to the teachings herein, the secondary switch holding time T can be determined based on energy storage considerations. CHR_ZVS Alternatively and additionally, without departing from the scope of the present application, the secondary switch holding time T CHR_ZVS It can also be called the secondary switch on time T CHR_ZVS In this context, the secondary switch is kept on for a time T CHR_ZVS During this time, the synchronous rectifier (SR) and / or the secondary switch may be operated in an “on state”.

[0047] Based at least in part on the principles of energy storage, the inductive energy can be equated with the capacitive energy to determine the peak inductor current Ipk.

[0048]

[0049] Then, based on equation EQ.1 and equation EQ.2, the secondary switch holding time T can be determined by equation EQ.3 CHR ZVS Approximate value of .

[0050]

[0051] Here, equation EQ.3 introduces the turns ratio N of the winding and the output voltage Vout. In the case of a single output flyback converter, as given by Figure 1A As shown in the example, the output voltage Vout is the output voltage V O1 ; and the turns ratio N can be determined by the winding ratio of the primary winding 112 to the secondary winding 99.

[0052] Equation EQ.3 can be generalized by removing the dependence on the turns rating N and introducing the concept of reflected output voltage Vor. By introducing the reflected output voltage Vor and using equation EQ.1, equation EQ.3 can be rewritten as equation EQ.4.

[0053]

[0054] For comparison, the secondary switch holding time T CHR_ZVS A more precise relationship for can be given by equation EQ.5.

[0055]

[0056] refer to Figure 1A , the forward pin voltage V at node 123 FWD can be obtained by equation EQ.6 with the input voltage V IN , the output voltage Vout is related to the turns ratio N of the winding.

[0057]

[0058] Then, the forward pin voltage V at the node 123 can be FWD Determine the input voltage V by using equation EQ.7 IN The relationship with the ratio of the reflected output voltage Vor.

[0059]

[0060] In addition, as in Figure 1A As illustrated in FIG. 1 , the secondary winding 99 is electrically coupled to the resistor R at a node 123 (ie, the positive pin node 123 ). W and the drain of NFET 126 .

[0061] According to the teachings herein, the ZVS on-time calculator 153 may dynamically (eg, dynamically as the primary switch 152 switches cycles) calculate the secondary switch holding time T CHR_ZVS According to equation EQ.7, the ZVS on-time calculator 153 can use a quantity that can be easily and dynamically measured, namely the forward pin voltage V at node 123. FWD and output voltage Vout (e.g., output voltage V O1 ).

[0062] Therefore, equations EQ.1 to EQ.7 can also be time-dependent equations, whereby a value (e.g., the forward pin voltage V at node 123) FWD The value of the output voltage Vout) is the time sampling value. For example, the forward pin voltage V at the node 123 is FWD Sampling may be performed at discrete times during a switching cycle of the primary switch 152 .

[0063] Thus, as will be appreciated by one of ordinary skill in the art, digital methods, analog methods, and / or algorithm-based methods may be used to implement the ZVS on-time calculator 153. For example, the calculation may be programmed into the controller 108.

[0064] As illustrated, NFET 126 may be configured to operate as a synchronous rectifier, and secondary controller 108 may provide a control signal Vcr to gate (control) NFET 126 (ie, gate SR). NFET 126 may also be configured to facilitate zero voltage switching (ZVS) in accordance with the teachings herein.

[0065] although Figure 1A NFET 126 can be configured to operate as a synchronous rectifier, but other configurations are possible. For example, Figure 1B and Figure 1C A power converter system 100 is illustrated according to another embodiment using a diode 126d in parallel with a secondary switch 127. The diode 126d may be configured to operate as a rectifier, and the secondary switch 127 may be configured to facilitate ZVS.

[0066] As in Figure 1C As illustrated in , secondary switch 127 may be implemented using NFET 127c. Additionally, diode 126d may be separate (e.g., isolated) from the body diode of NFET 127c; and diode 126d may be implemented to maintain a current similar to that of NFET 126, while NFET 127c may be implemented to have a current rating much lower than that of diode 126d. For example, diode 126d may be implemented using a discrete high current diode separate from NFET 127c.

[0067] Therefore, NFET 127c can be advantageously implemented with a smaller device area (e.g., a smaller semiconductor chip area) than the device area of ​​NFET 126. Therefore, NFET 127c can also be referred to as auxiliary NFET 127c without departing from the scope of the present disclosure. For example, during a switching cycle, auxiliary NFET 127c can be turned on only once to facilitate zero voltage switching (ZVS).

[0068] Furthermore, in accordance with the teachings herein, secondary controller 108 may use a forward pin voltage V at slave node 123 (ie, forward pin node 123 ) to determine the forward pin voltage V FWD For example, the secondary controller 108 may receive information from a resistor R coupled to the node 123. WThe forward pin signal FW is provided. The ZVS on-time calculator 153 may perform calculations based at least in part on the forward pin signal FW and / or the feedback signal FB1.

[0069] As disclosed herein, the ZVS on-time calculator 153 and the secondary controller 108 may include digital and / or analog circuits configured to calculate the secondary switch holding time T for achieving ZVS. CHR_ZVS For example, Figure 1D A power converter system 100 is illustrated that uses a secondary controller 108 having both digital and analog features.

[0070] Figure 1D The secondary controller 108 includes a ZVS on-time calculator 153, an output control block 154, a comparator 155, an idle ringing period calculator 156, edge detection blocks 157-158, delay blocks 159-160, a sample and hold circuit 161, analog-to-digital converters 162-163, an AND gate 164, and an AND gate 165. The secondary controller 108 receives a forward pin signal FW and a feedback signal FB1. As illustrated, the feedback signal FB1 can be directly obtained from the output voltage V O1 Get (for example, equal to the output voltage V O1 ). In other embodiments (e.g., Figure 1A In the embodiment of the present invention, the feedback signal FB1 can be related to the output voltage V O1 proportional (for example, to the output voltage V O1 )

[0071] As illustrated, the comparator 155 can convert the feedback signal FB1 (ie, the output voltage V O1 ) is compared with the positive pin signal FW. In response, the comparator 155 can provide a comparator output signal L1; and as described herein with respect to Figure 2A-2D As discussed, the idle ringing period TIR may be calculated in response to transitions of the comparator output signal L1.

[0072] Edge detection block 157 may receive comparator output signal L1 and trigger delay block 159 when comparator output signal L1 transitions from high to low. Delay block 159 may provide delayed output signal L2 after one quarter of idle ringing period TIR has elapsed in accordance with the teachings herein.

[0073] Similarly, edge detection block 158 may receive comparator output signal L1 and trigger delay block 160 when comparator output signal L1 transitions from low to high. Delay block 160 may provide delayed output signal L3 after one quarter of the idle ringing period TIR has elapsed in accordance with the teachings herein.

[0074] The output control block 154 may provide a request signal REQ based on the feedback signal FB1 and the delayed output signal L2. For example, the output control block 154 may determine that there is a demand for power delivery to the load 142 based on the feedback signal FB1 (e.g., the value of the feedback signal FB1 decreases). In addition, the output control block 154 may enable the request signal REQ in response to the demand and in response to the delayed output signal L2.

[0075] Sample and hold circuit 161 may sample the forward pin signal FW and provide the sample to an analog-to-digital converter (ADC) 162. ADC 162, in turn, may provide a digital forward pin signal DFW (ie, a digital representation of the forward pin signal FW).

[0076] Similarly, ADC 163 may convert feedback signal FB1 and provide a digital output voltage signal DVO (ie, a digital representation of feedback signal FB1 ).

[0077] As illustrated, the ZVS on-time calculator 153 may receive the digital output voltage signal DVO, the digital forward pin signal DFW, and the idle ringing period TIR. In response, the ZVS on-time calculator 153 may assert the ZVS calculator signal L4.

[0078] According to the teachings herein, ZVS on-time calculator 153 may perform calculations based at least in part on one or more of equations EQ.1-EQ.7. For example, ZVS on-time calculator 153 may calculate secondary switch holding time T according to equation EQ.8 derived from equation EQ.4 and equation EQ.7. CHR_ZVS .

[0079]

[0080] In addition, as illustrated, the AND gate 164 receives the request signal REQ, the ZVS calculator signal L4, and the delayed output signal L2. As shown, the control signal V may be applied based on a logical AND function of the request signal REQ, the ZVS calculator signal L4, and the delayed output signal L2. CR to drive the gate of NFET 126. As will be appreciated by one of ordinary skill in the art, additional components and / or buffer stages may be present between the output of AND gate 164 and the gate of NFET 127c. Alternatively and additionally, Figure 1D The secondary controller 108 can be used with embodiments using NFET 126 (e.g., Figure 1A implementation scheme) together with.

[0081] Additionally, AND gate 165 receives request signal REQ and delayed output signal L3 . As shown, signal FL may be applied and coupled to primary controller 109 to close primary switch 152 based at least in part on a logical AND function of request signal REQ and delayed output signal L3 .

[0082] although Figures 1A to 1D Power converter system 100 is shown according to a single output implementation; however, other implementations are possible.

[0083] For example, Figure 1E A power converter system 100 is illustrated according to a multiple output (ie, multi-output) implementation. Figure 1E The power converter system 100 may be configured similar to Figure 1A The power converter system, except as described below, Figure 1E The power converter system 100 has multiple outputs.

[0084] As illustrated, power converter system 100 includes energy transfer element 102, secondary switch block 104, load circuit 106, secondary controller 108, primary controller 109, clamp 110, and primary switch 152. Energy transfer element 102 includes primary winding 112 and secondary windings 114, 116, 118. Secondary switch block 104 includes NFET 126 and secondary switches 119, 122, 125.

[0085] The multi-output power converter system 100 can convert the rectified AC line voltage V IN The input power is converted into multiple output voltages including V O1 -V O3 and the secondary current I S1 -I S3 Alternatively and additionally, the input power may be obtained from a high voltage power source. The load circuit 106 includes a CC / CV3 port, a CC / CV2 port, a CC / CV1 port (which may be a regulated DC power port) and a secondary ground return port SRTN.

[0086] In addition, depending on the load condition at the CC / CV3 port, the CC / CV3 port can be a constant current (CC) port (i.e., the secondary current I S3 is controlled to be constant) and / or a constant voltage (CV) port (i.e., the output voltage V O3 Depending on the load condition at the CC / CV2 port, the CC / CV2 port can be a constant current (CC) port (i.e., the secondary current I S2is controlled to be constant) and / or a constant voltage (CV) port (i.e., the output voltage V O2 is controlled to be constant); and depending on the load condition at the CC / CV1 port, the CC / CV1 port may be a constant current (CC) port (ie, the secondary current I S1 is controlled to be constant) and / or a constant voltage (CV) port (i.e., the output voltage V O1 is controlled to be constant).

[0087] For example, in one embodiment, the CC / CV3 port may be a CC port, and the secondary current I S3 The load current can be regulated, while the output voltage V O3 At least partially determined by the load of the CC / CV3 port. In addition, the CC / CV1 port and the CC / CV2 port can be CV ports, thereby regulating the output voltage V O1 and output voltage V O2 The secondary ground return port SRTN may be electrically coupled to the secondary ground RTN.

[0088] In one embodiment, the output voltage V O1 -V O3 The voltage V of the secondary windings 114, 116, 118 to the primary winding 112 may be determined at least in part by the energy transfer element 102. For example, the turns ratio of the secondary windings 114, 116, 118 to the primary winding 112 and the transformer configuration (e.g., stacked secondary windings) may be configured for the highest voltage CC / CV3 port (e.g., a voltage greater than forty volts). The CC / CV1 port and the CC / CV2 port may be regulated to a lower voltage (e.g., a voltage between three volts and forty volts). In one embodiment, the CC / CV2 port may be a voltage having an output voltage V regulated to a lower voltage (e.g., twenty volts). O2 and the CC / CV1 port may be an output voltage V regulated to a minimum voltage (eg, five volts) O1 CV port.

[0089] Alternatively and additionally, the output voltage V O1 -V O3 The output voltage V O3 Greater than the output voltage V O2 .

[0090] As illustrated, secondary windings 114, 116, and 118 are electrically coupled in a stacked (i.e., series) configuration according to a transformer "dot" symbol. As shown, secondary switch 119 is electrically coupled on circuit path 111 between the "dot" terminal of secondary winding 118 and the CC / CV3 port. Secondary switch 122 is electrically coupled on circuit path 113 between the "dot" terminal of secondary winding 116 and the CC / CV2 port; and secondary switch 125 is electrically coupled on circuit path 115 between the "dot" terminal of secondary winding 114 and the CC / CV1 port.

[0091] As shown, an N-type FET (NFET) 126 is coupled between the secondary winding 114 and the secondary RTN in the circuit path 117. Figure 1A As discussed, NFET 126 can be configured to operate as a synchronous rectifier and be switched on and off by control signal Vcr. Figure 1B and Figure 1C As discussed, a diode 126d and a secondary switch 127 connected in parallel may be used in place of the NFET 126.

[0092] Furthermore, as illustrated, the primary winding 112 and the primary switch 152 may be connected between the input terminals 101, 103 to receive a rectified AC line voltage V relative to the primary ground GND. IN During a switching cycle (ie, switching period), when the primary switch 152 is closed (ie, turned on), the primary winding 112 may be electrically connected to the primary winding 112 by an increasing (ie, ramping) primary current I SW According to magnetics and transformer theory, when the primary switch 152 is opened (ie, changes from a conducting state to a blocking state), energy in the primary winding 112 can be transferred to one or more of the secondary windings 114, 116, 118.

[0093] The secondary controller 108 receives feedback signals FB1-FB3 from the load circuit 106, communicates with the primary controller 109 via the signal FL, and provides control signals SEL1-SEL3 to the secondary switch block 104. As illustrated, the secondary controller 108 can be configured to use signals referenced to the secondary ground RTN (e.g., the feedback signals FB1-FB3 and the plurality of output voltages V O1 -V O3 Thus, the signal FL may be an optically coupled, magnetically coupled and / or capacitively coupled signal FL to allow communication with the primary controller 109, which is referenced to the primary ground GND.

[0094] As described herein, the secondary controller 108 may provide one or more control signals SEL1-SEL3 to selectively control (i.e., switch) the transfer of energy (i.e., power) to the load circuit 106 by selecting a circuit path (e.g., circuit path 111, circuit path 113, and / or circuit path 115). As illustrated, the secondary controller 108 provides control signals SEL1, SEL2, SEL3 to the secondary switches 125, 122, 119, respectively. The control signals SEL1, SEL2, SEL3 may in turn gate the switches 125, 122, 119, respectively, to operate in an on state or an off state.

[0095] During a switching cycle, when the secondary switch 119 is closed (ie, operating in the on state) and both the secondary switches 125, 122 are open (ie, both operating in the off state), energy can be transferred via the secondary current I on the circuit path 111. S3 As illustrated, circuit path 111 is a switch circuit path that includes secondary switch 119 and is electrically coupled to the CC / CV3 port of load circuit 106. Alternatively, when secondary switch 122 is closed (i.e., operating in the on state) and secondary switches 125, 119 are open (i.e., operating in the off state), energy can be transferred via the secondary current I on circuit path 113. S2 As illustrated, circuit path 113 is a switch circuit path that includes secondary switch 122 and is electrically coupled to CC / CV2 port of load circuit 106. Alternatively, when secondary switch 125 is closed (i.e., operating in the on state) and secondary switches 122, 119 are open (i.e., operating in the off state), energy can be transferred via secondary current I on circuit path 115. S1 As illustrated, circuit path 115 is a switched circuit path that includes secondary switch 125 and is electrically coupled to the CC / CV1 port of load circuit 106 .

[0096] As discussed above, the secondary controller 108 may include a zero voltage switching (ZVS) on-time calculator 153. According to the teachings herein, the secondary controller 108 may calculate a holding time (e.g., a secondary switch holding time T) for controlling a synchronous rectifier (SR) during a switching cycle (i.e., a switching cycle of the primary switch 152) based in part on the forward pin signal FW and the select output. CHR_ZVS ).

[0097] exist Figure 1E In the multi-output embodiment of the present invention, the selected output can refer to the output that is activated and / or selected during the switching cycle. For example, during the switching cycle, when the secondary switch 125 is closed, the selected output will be connected to the output voltage V O1Alternatively, when the secondary switch 122 is closed, the selected output will be consistent with the output voltage V O2 Therefore, the output voltage V O Re-state equation EQ.7 by replacing the output voltage Vout. For example, when the output and output voltage V O2 Correspondingly, the output voltage V O is the output voltage V O2 .

[0098] Figure 1F Illustrated based on Figure 1E The embodiment of the multiple output (ie, multi-output) power converter system 100. The primary switch 152 is implemented using an N-type field effect transistor (FET) 152b. The secondary switch 119 is replaced by a diode 120. As illustrated, the diode 120 is electrically coupled between the "point" terminal of the secondary winding 118 and the CC / CV3 port on the circuit path 111. At the output voltage V O3 It is necessary for multiple output voltages V O1 -V O3 In applications where the maximum of , the secondary switch 119 may be replaced by a diode 120 to advantageously simplify the switch block 104 and eliminate the need for the control signal SEL3.

[0099] Secondary switch 122 is implemented using an N-type FET 122b; as illustrated, secondary switch 122 is electrically coupled to diode 121 between the "point" terminal of secondary winding 116 and CC / CV2 port on circuit path 113. Secondary switch 125 is implemented using an N-type FET 125b; secondary switch 125b is electrically coupled between the "point" terminal of secondary winding 114 and CC / CV1 port on circuit path 115.

[0100] The N-type FETs 152b, 122b, 125b, 126 may be integrated power FETs and / or discrete power FETs. In one embodiment, the N-type FETs 152b, 122b, 125b, 126 may be enhancement mode FETs.

[0101] The load circuit 106 includes feedback networks 140, 136, 132, which can provide feedback signals FB1, FB2, FB3 to the secondary controller 108, respectively. In addition, the load circuit 106 includes filter capacitors C1-C3, which are electrically coupled to the first load 142, the second load 138, and the third load 148, respectively. In steady state, Figure 1F The multiple-output power converter system 100 may be configured to regulate power delivered to the first load 142 , the second load 138 , and the third load 148 .

[0102] For example, the feedback networks 140, 136, and 132 may include voltage divider networks to provide voltages V O1 、V O2 、V O3 The feedback signals FB1, FB2, and FB3 of the closed-loop regulation are respectively O1 、V O2 、V O3 In this way, the power delivered to the first load 142 can be regulated as a CV output (ie, a regulated output voltage V O1 The power delivered to the second load 138 may be regulated as a CV output (ie, a regulated output voltage V O2 ); and the power delivered to the third load 148 can be regulated as a CV output (ie, a regulated output voltage V O3 ).

[0103] As discussed above, the secondary controller 108 can communicate with the primary controller 109 via a signal FL (e.g., a magnetic coupling signal FL). For example, using the signal FL, the primary controller 109 can transmit a handshake to the secondary controller 108 to indicate a good power condition. Alternatively and additionally, using the signal FL, the secondary controller 108 can transmit a request for more energy transfer. In response to the request, the primary controller 109 can change the primary control signal V CS to close the primary switch 152 and energize the primary winding 112 .

[0104] As illustrated, the secondary controller 108 may receive the forward pin signal FW and the feedback signals FB1-FB3; and the secondary controller 108 may provide the control signals SEL1, SEL2 and V Cr As discussed herein, control signals SEL1, SEL2 may be used to selectively control (i.e., switch) the transfer of energy (i.e., power) to load circuit 106 by selecting a circuit path (e.g., circuit path 111, circuit path 113, and / or circuit path 115). In addition, control signal V Cr Can be used to drive the gate of N-type FET 126 to operate as a synchronous rectifier.

[0105] As discussed above, the feedback signals FB1-FB3 may be sampled (i.e., measured) signals used for closed-loop control of the CV output within the secondary controller 108. However, as will be appreciated by one of ordinary skill in the art, other configurations are possible. For example, as discussed herein, the secondary controller 108 may also be configured to provide closed-loop control of the CC output.

[0106] As shown, the forward pin voltage V FWD may be present at node 123; and an optional passive component (ie, resistor R W ) can be electrically coupled between the secondary winding 114 at node 123 to provide a forward pin signal FW to the secondary controller 108. In some embodiments, the forward pin signal FW can be equivalent to the forward pin voltage V FWD , while in other embodiments, the positive pin signal FW can be relative to the positive pin voltage V FWD is attenuated.

[0107] Figure 1G Illustrated based on Figure 1E A multiple output power converter system 100 according to another embodiment of the present invention is provided. Figure 1G An implementation similar to Figure 1F Embodiment, except that the load 148 is replaced by the LED string 183-184; and the current sensing element 182 is sensitive to the load current I L3 Sampling is performed to provide feedback signal FB3. In steady state, Figure 1G The multi-output power converter system 100 can be configured to regulate the power delivered to the LED strings 183-184 to a CC output (ie, a regulated load current I L3 ).

[0108] In addition, the load circuit 106 includes a plurality of light emitting diode (LED) strings 183-184 connected in parallel, a first load 142, and a second load 138. As illustrated, the LED strings 183-184 require (ie, receive) a load current I L3 ; and although the feedback signal FB3 is shown as directly responding to the load current I L3 For example, the LED string current I L3A -I L3B Instead of sampling the load current I L3 Sampling is performed to adjust the load current I L3 ; and the LED string current I L3A -I L3B can be used by the secondary controller 108 to regulate the total load current I L3 .

[0109] In one embodiment, the LED string current I L3A -I L3B can be used by the secondary controller 108 to regulate the output voltage V O3 , as the control total load current I L3Furthermore, although the load circuit 106 is shown as having two LED strings 183 , 184 , other configurations having more or less than two LED strings 183 , 184 are possible.

[0110] As discussed above, a diode 126d and a secondary switch 127 connected in parallel may be used in place of NFET 126. For example, Figure 1H Illustrated based on Figure 1G and Figure 1D A multiple output power converter system 100 according to another embodiment of the present invention is provided. Figure 1H An implementation similar to Figure 1G Implementation of Figure 1D , NFET 126 may be replaced with a parallel connected diode 126d and secondary switch 127. As illustrated, secondary switch 127 includes an auxiliary NFET 127c.

[0111] In addition, as can be understood by those skilled in the art, Figure 1A-Figure 1H The embodiments are non-limiting, and other configurations can be implemented using integrated semiconductor components and / or discrete semiconductor components (including bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), and / or opposite polarity FETs (e.g., P-channel FETs). In addition, active devices can be implemented using material processes based on silicon, silicon germanium, gallium nitride, etc.

[0112] Figure 2A Waveforms 202-205 during a discontinuous mode (DCM) over a switching cycle with a period T1 are illustrated. Waveform 202 may correspond to the forward pin voltage V as a function of time. FWD and / or the forward pin signal FW. Waveform 203 may be related to the switch voltage V as a function of time. SW The waveform 204 can be related to the primary control signal V as a function of time. CS and waveform 205 may correspond to the control signal Vcr as a function of time.

[0113] As depicted by waveform 204, the primary control signal V that drives the primary switch (eg, primary switch 152) is CS The period T1 may be periodic. For example, as shown at time 211, the primary control signal V CS The primary control signal V CS The control signal may transition from low to high, thereby turning on the primary switch 152 ; and at time 214 , the control signal may transition from high to low again, thereby turning off the primary switch 152 .

[0114] As depicted by waveform 205, the signal Vcr driving the gate of the SR (eg, NFET 126) may transition after the turn-off transition of the primary switch 152. For example, as shown at time 211, the signal V CR The signal Vcr may transition from low to high at time 211 and remain high until time 212. At time 212, the signal Vcr may transition from high to low and remain low until a new cycle begins at time 214.

[0115] As depicted by waveform 202 relative to waveforms 204 - 205 , the forward pin voltage V at node 123 FWD The voltage V may be changed periodically according to the switching transitions of the primary switch 152 and the SR (eg, NFET 126). For example, from time 211 to time 212, the SR (NFET 126) may be in conduction and the forward pin voltage V FWD Time 212 may depict when energy from secondary windings 114, 116, 118 and / or winding 99 becomes depleted to the point where ringing may occur at node 123. For example, as shown by waveform 202, there is ringing (i.e., oscillation) between time 212 and time 213.

[0116] In addition, as shown, the ringing at the output voltage V OUT According to the teachings of this article, the output voltage V OUT Can be used with Figure 1A Output V O1 and / or Figure 1E-1H The output voltage V O1 -V O3 Corresponding.

[0117] As depicted by waveform 203 relative to waveforms 202, 204, 205, the switch voltage V SW It can also be changed periodically according to the switching transition of the primary switch 152 and the SR (eg, NFET 126). For example, from time 211 to time 212, when the forward pin voltage V FWD When forced to be less than and / or equal to zero volts (0V), the switch voltage V SW reaches a voltage exceeding the rectified AC line voltage V IN In addition, after time 212, when the energy from the secondary windings 114, 116, 118 and / or winding 99 becomes exhausted, the switch node voltage V SWThe ringing may be due at least in part to capacitance (e.g., parasitic capacitance of primary switch 152) and inductance (e.g., inductance of primary winding 112). According to switch-mode power converter theory and as illustrated by waveforms 202, 203, the ringing of waveform 202 and the ringing of waveform 203 may be out of phase. When the primary control signal V CS When the primary switch 152 is turned on at time 213, the ringing may stop.

[0118] According to the teaching of this article, the voltage V FWD The information can advantageously provide information without the need for additional communications from the primary to the secondary.

[0119] Figure 2B Waveforms 222-225 during a switching cycle according to the teachings herein are illustrated. Waveform 222 may correspond to the forward pin voltage V as a function of time. FWD and / or forward pin signal FW. Waveform 223 may correspond to control signal Vcr as a function of time. Waveform 224 may correspond to signal FL transmitted by secondary controller 108 as a request for energy; and waveform 225 may correspond to primary control signal Vcr as a function of time. CS Corresponding.

[0120] In contrast to waveform 204, waveform 223 shows a transition from low to high at time 241 and a transition from high to low at time 242. According to the teachings herein, by turning on the SR (e.g., NFET 126) during interval T2 (i.e., from time 241 to time 242), primary switch 152 may experience ZVS; and as discussed herein, the duration of interval T2 (also referred to as a hold time (e.g., secondary switch hold time T2) may be calculated using information available to secondary controller 108. CHR_ZVS )).

[0121] As illustrated by waveforms 223-225, after interval T2, signal FL transitions from low to high at time 244, and then transitions from high to low at time 245. Then, in response to signal FL, primary control signal V CS At time 246, the primary switch 152 is turned on. At time 247, the primary switch 152 is turned on due to the primary control signal V CS Switching from high to low shuts down.

[0122] Relative to waveforms 223-225, waveform 222 illustrates the forward pin voltage V FWD How does it change after interval T2? For example, during interval T3 from time 242 to time 243, the forward pin voltage V FWDfrom zero volt (0V) to the output voltage Vout and / or the selected output voltage V O During the interval T4 from time 243 to time 246, the forward pin voltage V FWD From the output voltage Vout and / or the selected output voltage V O The determined value is converted to the value V FON As shown, the value V FON can be compared with the forward pin voltage V when the primary switch 152 is turned on. FWD and / or the value of the positive pin signal FW.

[0123] Although waveform 222 will forward pin voltage V FWD For example, the value V FON , but other variations are possible. For example, as will be appreciated by one of ordinary skill in the art, in other configurations, the forward pin voltage V FWD may not reach (i.e., may not ring or transition to) a value V FON .

[0124] As discussed herein, the duration of interval T2 (also referred to as hold time T2 (ie, secondary switch hold time T2)) CHR_ZVS )) can be compared with the value V FON And the output voltage V OUT and / or select the output voltage V O Therefore, we can replace the value V FON To rewrite equation EQ.7, the value V FON The forward pin voltage V FWD The sampling value of .

[0125] Figure 2C Waveforms 252-255 are illustrated during a switching cycle from time 270 to time 279 according to one embodiment. Waveform 252 may correspond to the forward pin voltage V as a function of time. FWD and / or forward pin signal FW. Waveform 253 may correspond to control signal Vcr as a function of time. Waveform 254 may correspond to signal FL transmitted by secondary controller 108 at time 275 as a request for energy; and waveform 255 may correspond to primary control signal Vcr as a function of time. CS Corresponding.

[0126] Referring to waveform 255, the primary control signal V CS The time 270 when the control signal V CSThe switching cycle is at time 279 when FL transitions low again. Additionally, as illustrated by waveform 254, during the switching cycle from time 270 to time 279, signal FL sends a request for energy between time 276 and time 277.

[0127] As depicted by waveform 252 relative to waveforms 253 - 255 , the forward pin voltage V at node 123 FWD The voltage V may be changed periodically according to the switching transition of the primary switch 152 and the switching transition of the SR switch (eg, NFET 126). For example, from time 270 to time 272, the SR (NFET 126) may be conducting and the forward pin voltage V FWD Time 272 may depict when energy from secondary windings 114, 116, 118 and / or winding 99 becomes depleted to the point where ringing may occur at node 123. For example, as shown by waveform 252, during interval T5 between time 272 and time 273, there may be an initial onset of ringing (i.e., oscillation).

[0128] According to the teachings herein, the SR switch (NFET 126) may be turned on at time 273. In addition, according to the teachings herein, the output voltage V OUT Can be used with Figure 1A Output V O1 and / or Figure 1E-1H The output voltage V O1 -V O3 Corresponding.

[0129] As described herein, the control signal V CR The secondary switch T may be kept high during interval T6 (ie, from time 273 to time 274). Interval T6 may also be referred to as the secondary switch T CHR_ZVS Referring to waveforms 252-255, the secondary switch holding time T CHR_ZVS The forward pin voltage V sampled at time 269 can be FWD (For example, the value V FON ) to determine (i.e., calculate).

[0130] Furthermore, as explained above, the value V FON can be compared with the forward pin voltage V when the primary switch 152 is turned on. FWD and / or the value of the positive pin signal FW.

[0131] As discussed herein, interval T6 (eg, secondary switch holding time T CHR_ZVS ) can also be determined (i.e., calculated) as the output voltage V OUTAccording to the teaching of this article, the output voltage V OUT It can also be a selected output voltage V that is readily available to the secondary controller 108. O For example, refer to Figure 1H , can provide a selected output voltage V to the secondary controller 108 according to any one of the feedback signals FB1-FB3 O .

[0132] Referring to waveforms 253-255, waveform 252 also illustrates the forward pin voltage V FWD How does it change after interval T6? For example, during interval T7 from time 274 to time 275, the forward pin voltage V FWD From zero volts (0V) to the output voltage and / or the selected output voltage V O Subsequently, during the interval T8 from time 275 to time 278, the forward pin voltage V FWD from the output voltage and / or by selecting the output voltage V O The determined value is converted to the value V FON According to the teachings herein, interval T8 may be one quarter (ie, one fourth) of the idle ringing period TIR as given by equation EQ. 9.

[0133]

[0134] In addition, according to the teaching of this article, it is also possible to use the sampling value V FON and select the output voltage V O Equation EQ.8 is restated using equation EQ.10.

[0135]

[0136] Figure 2D Waveforms 252 - 255 are illustrated during a switching cycle from time 270 to time 279 according to another embodiment. Figure 2D The implementation scheme can be similar to Figure 2C 270 and 272, except that waveform 253 does not transition high between time 270 and time 272 nor does it transition high at time 279. Instead, waveform 253 transitions high only from time 273 to time 274 during interval T6.

[0137] For example, Figure 2D The waveform 253 can be compared with Figure 1C and / or Figure 1H The power converter system 100 using NFET 127c corresponds to; and Figure 2C The implementation scheme can be Figure 1A The power converter system 100 using the NFET 126 corresponds to FIG.

[0138] Figure 3A A conceptual flow chart 300 is illustrated for zero voltage switching in the power converter system 100 according to an embodiment.

[0139] Step 301 may correspond to closing (ie, turning on) primary switch 152 at time 278 .

[0140] Step 302 can be related to the forward pin voltage V at time 269. FWD Referring to waveform 252, when the primary switch 152 is turned on (ie, conducting), the forward pin voltage V at time 269 is FWD The positive pin signal value V FON .

[0141] Step 304 may correspond to opening (ie, turning off) the primary switch at time 270 .

[0142] Step 306 may correspond to closing the SR switch (eg, NFET 126 ) at time 270 ; and step 308 may correspond to opening the SR switch (eg, NFET 126 ) at time 272 .

[0143] Step 310 may correspond to calculating the SR holding duration T6 (eg, calculating the interval T6). The SR holding duration T6 may be determined by the secondary switch holding time T as obtained herein. CHR_ZVS Given.

[0144] Step 312 may correspond to closing the synchronous rectifier for the hold duration T6. For example, step 312 may correspond to closing the SR switch (eg, NFET 126) for the interval T6 from time 273 to time 274 (ie, the hold duration T6).

[0145] Step 313 may correspond to turning off the synchronous rectifier after the hold duration T6 and before time 278 .

[0146] Figure 3B A conceptual flow chart 350 is illustrated for zero voltage switching in the power converter system 100 according to another embodiment. The conceptual flow chart 350 is similar to the conceptual flow chart 300, except that it does not include steps 306-308; and steps 312-313 are replaced by steps 352-353, respectively.

[0147] Step 352 may correspond to closing the secondary switch (eg, NFET 127c) during the hold duration T6. Step 352 may correspond to opening the secondary switch (eg, NFET 127c) after the hold duration T6 and before time 278.

[0148] Dynamic operation during switching cycles

[0149] Figure 4 The waveforms 403-407 are compared during two switching cycles 401-402 of the primary switch 152. For comparison, during the switching cycle 401, the control signal Vcr may be disabled; while during the switching cycle 402, the control signal Vcr may be enabled.

[0150] Waveform 405 may correspond to the forward pin voltage V as a function of time. FWD and / or the forward pin signal FW. Waveform 407 may be related to the switch voltage V as a function of time. SW The waveform 403 can be related to the primary control signal V as a function of time. CS and waveform 404 may correspond to the control signal Vcr as a function of time. In addition, waveform 406 may correspond to the output voltage V OUT (For example, Figure 1D The output voltage V O1 ) corresponding to.

[0151] The primary switch 152 can respond to the primary control signal V CS And operate in the "on" state. Figure 4 , the primary switch 152 is closed (i.e., “ON”) at times 410, 411, and 421. A switching cycle 401 (i.e., switching period 401) is depicted from time 410 to time 411, while a switching cycle 402 is depicted from time 411 to time 421. As discussed above, the switching cycle 402 may be Figure 1D corresponds to the switching cycle of the primary switch 152 in the implementation scheme of .

[0152] At time 412, the sample and hold circuit 161 may detect the forward pin signal FW and / or the forward pin voltage V FWD For example, the sample and hold circuit 161 can sample the forward pin voltage V at point 427 on the waveform 405. FWD Thus, ADC 162 can further provide a digital forward pin signal DFW as a digital representation of waveform 405 at time 412 (eg, value V FON ).

[0153] At time 413, primary switch 152 may be opened (ie, "turned off"). Figure 1D In the embodiment of FIG. 4 , from time 413 to time 414, diode 126d may conduct. Therefore, waveform 404 (i.e., control signal Vcr) remains low from time 413 to time 414. However, as will be appreciated by one of ordinary skill in the art, in other embodiments (e.g., Figure 1A In an embodiment of the present invention, waveform 404 (ie, control signal Vcr) may transition high at time 413 and then transition low at time 414 to drive the gate of NFET 126.

[0154] At time 414, power converter system 100 may enter discontinuous conduction mode (DCM). Therefore, waveform 405 and waveform 407 exhibit ringing. Comparator 155 may be used to distinguish waveform 405 (ie, forward pin voltage V FWD and / or the forward pin signal FW) and waveform 406 (ie, the output voltage V OUT ) intersect (i.e., cross) at points 433-436. Figure 1D , the comparator output signal L1 can therefore change (i.e., transition) according to the ringing of the waveform 405; further, the idle ringing period calculator 156 can calculate the idle ringing period TIR according to the transition of the comparator output signal L1. In addition, the edge detection blocks 157-158 can be triggered according to the transition edge of the comparator output signal L1.

[0155] During the switching cycle 402, the ZVS on-time calculator 153 can dynamically calculate the holding time (eg, the secondary switch holding time T ) based on the idle ringing period T IR , the digital forward pin signal DFW , and the digital output voltage signal DVO . CHR_ZVS ).like Figure 1D As illustrated in FIG. 1 , the hold time may be provided via the ZVS calculator signal L4; and in response to the AND gate 165, the waveform 404 (i.e., the control signal Vcr) transitions high at time 415 and transitions low at time 416. According to the teachings herein, the time duration from time 415 to time 416 may be determined at least in part by the ZVS on-time calculator 153.

[0156] In addition, the comparator output signal L1 can also be in waveform 405 (ie, the forward pin voltage V FWD and / or the forward pin signal FW) and waveform 406 (ie, the output voltage V OUT ) intersects (ie, crosses) at point 437. Subsequently, delay block 159 may be changed so that at time 421 the primary control signal V CS(ie, waveform 403) turns on primary switch 152. The delay from point 437 to time 421 when primary switch 152 turns on may be referred to as the "off ringing duration."

[0157] According to the teachings of this document, the disconnected ringing duration may be one quarter of the idle ringing period TIR. Figure 1D , the delay block 160 can provide a delayed output signal L3 after a quarter of the idle ringing period TIR has passed. This in turn can result in a delay of a quarter of the idle ringing period TIR, so that the duration from time 416 to time 421 is substantially equal to a quarter of the idle ringing period TIR.

[0158] When the control signal Vcr is enabled during the switching cycle 402, the switch is relatively "soft" (ie, improved) at time 421. As illustrated by waveform 407, at time 421, the switch voltage V SW At point 438, the switch voltage V SW The transition is made from point 431 which has a relatively higher voltage than point 438 .

[0159] Although the multiple output power converter system 100 is illustrated as a system for providing multiple selected output voltages V O1 -V O3 and the secondary current I S1 -I S3 The invention relates to a switch mode configuration (e.g., a flyback configuration), but other configurations with more or fewer multiple outputs are possible. For example, the teachings herein may also be applied to a forward converter (forward converter) using a transformer with multiple secondary windings and / or other converter topologies.

[0160] It should be understood that in the description and example drawings, the concept of independently controlled CC / CV multiple outputs is primarily illustrated using the series coupling of secondary windings on energy transfer elements (e.g., transformers). However, it should not be considered limiting, and it should be understood that, according to the teachings herein, based on the application and the load power requirements of each of the multiple outputs, the independently regulated CV / CC outputs can be arranged as any coupling combination of the following windings with a common return line for all independently controlled and regulated outputs: series windings, parallel windings, or both series windings and parallel windings.

[0161] The proposed converter topology is an embodiment of a single-stage, multiple-output flyback converter that targets applications with multiple independently regulated constant voltage and / or constant current outputs. Example targets for such products may include monitor and television applications that include CC control outputs for parallel strings (e.g., arrays) of backlight LEDs, requiring regulated adjustable (e.g., dimming) constant current outputs, such as with a voltage drop of 40V-50V, and one or more CV control outputs for powering logic, Universal Serial Bus (USB), and audio, and the CV control outputs should meet stringent regulation accuracy requirements for each output.

[0162] in conclusion

[0163] The above description of the illustrated embodiments of the present disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the precise form disclosed. Although specific embodiments and embodiments for dynamically controlling the secondary switch to achieve zero voltage switching are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present disclosure. Indeed, it should be understood that specific example voltages, currents, frequencies, power range values, times, etc. are provided for purposes of explanation, and other values ​​may also be employed in other embodiments and examples in accordance with the teachings herein.

[0164] The foregoing description may involve referring to elements or features as being "connected," "electrically connected," and / or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element / feature is directly or indirectly connected to another element / feature, and not necessarily mechanically connected. Likewise, unless expressly stated otherwise, "coupled" means that one element / feature is directly or indirectly coupled to another element / feature, and not necessarily mechanically coupled. Thus, although the various schematic diagrams shown in the accompanying drawings depict example arrangements of elements and components, in an actual embodiment, there may be additional intermediate elements, devices, features, or components (assuming that the functionality of the depicted circuits is not adversely affected).

[0165] Furthermore, conditional language used herein, such as, among others, “can, may,” “could,” “might,” “may,” “eg,” “for example,” “such as,” and the like, is generally intended to convey that certain embodiments include and other embodiments do not include certain features, elements, and / or states, unless expressly stated otherwise or otherwise understood in the context as used. Thus, such conditional language is generally not intended to imply that one or more embodiments require features, elements, and / or states in any way, or that one or more embodiments must include logic for determining whether such features, elements, and / or states are included in any particular embodiment or are to be performed in any particular embodiment.

[0166] Although certain embodiments have been described, these embodiments are presented only by way of example and are not intended to limit the scope of the present disclosure. In fact, the novel devices, methods, and systems described herein may be embodied in various other forms; in addition, various omissions, substitutions, and changes to the forms of the methods and systems described herein may be made without departing from the spirit of the present disclosure. For example, although the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and may delete, move, add, subdivide, combine, and / or modify some elements. Each of these elements may be implemented in a variety of different ways. Any suitable combination of the elements and actions of the embodiments described above may be combined to provide other embodiments. Therefore, the scope of the present invention is limited only by reference to the appended claims.

[0167] Although the claims presented herein are in a single dependent format for filing with the United States Patent and Trademark Office (USPTO), it should be understood that any claim may be dependent on any prior claim of the same type unless that is clearly technically infeasible.

Claims

1. A method of dynamically switching during a switching cycle of a primary switch in a power converter, the method comprising: initiating the switching cycle by closing the primary switch; receiving a forward pin voltage at a forward pin node; disconnecting the primary switch; Receive selected output voltage; Determine the idle ringing period; calculating a hold duration associated with the forward pin voltage, the selected output voltage, and the idle ringing period; as well as The secondary switch is closed during the holding time period. 2 . The method of claim 1 , wherein the secondary switch is a synchronous rectifier.

3. The method of claim 1, wherein the secondary switch is an auxiliary N-channel field effect transistor (NFET).

4. The method of claim 1, wherein the secondary switch is an auxiliary bipolar junction transistor (BJT). The method of claim 1 , wherein the power converter is a flyback converter. The method of claim 1 , wherein the power converter is a multiple output flyback converter.

7. The method according to claim 1, further comprising: Energy is delivered to the selected output to maintain the selected output voltage.

8. The method according to claim 1, further comprising: The idle ringing period is determined using a comparator.

9. The method according to claim 1, further comprising: determining an off-ringing duration associated with the idle-ringing period; as well as The switching cycle is completed after the off-ringing duration.

10. The method of claim 9, wherein the off-ringing duration is substantially equal to one quarter of the idle ringing period.

11. A multi-output power converter comprising: an energy transfer element including a primary winding configured to receive energy from a first power source and at least one secondary winding configured to transfer energy to a selected output; a primary switch electrically coupled to the primary winding and configured to switch according to a switching cycle; Secondary controller, including: an idle ringing period calculator configured to calculate an idle ringing period during the switching cycle; and a zero voltage switching (ZVS) calculator configured to calculate a hold duration based at least in part on the idle ringing period; and A secondary switch is electrically coupled to the at least one secondary winding and is configured to close for the hold-up duration in response to a control signal from the secondary controller.

12. The multi-output power converter of claim 11, wherein the multi-output power converter is a multi-output flyback converter.

13. The multi-output power converter of claim 11, wherein the selected output is a constant current (CC) output.

14. The multi-output power converter of claim 11, wherein the selected output is a constant voltage (CV) output.

15. The multiple output power converter of claim 11, wherein the idle ringing period depends at least in part on a primary capacitance and a primary inductance.

16. The multiple-output power converter of claim 11, wherein the select output is configured to provide a select output voltage, and wherein the hold duration depends at least in part on the select output voltage.

17. The multiple output power converter of claim 11, wherein the secondary switch is a synchronous rectifier.

18. The multiple-output power converter of claim 11, wherein the secondary switch is an auxiliary N-channel field effect transistor (NFET).

19. The multi-output power converter of claim 18, further comprising: A diode is connected in parallel with the auxiliary NFET and is separated from the auxiliary NFET.

20. A multi-output power converter system comprising: a primary switch electrically coupled to the primary winding and configured to switch during a first switching cycle; a select output configured to provide a select output voltage during said first switching cycle; a forward pin node electrically coupled to the secondary winding and configured to provide a forward pin voltage; a secondary switch electrically coupled to the forward pin node and configured to conduct current during a hold duration of the first switching cycle; as well as Secondary controller, including: an idle ringing period calculator configured to provide an idle ringing period of the first switching cycle; as well as A zero voltage switching (ZVS) calculator is configured to calculate the hold-up duration associated with the idle ringing period of the first switching cycle such that the primary switch undergoes zero voltage switching during a second switching cycle.

21. The multi-output power converter system of claim 20, wherein the multi-output power converter system is a multi-output flyback power converter system.

22. The multiple output power converter system of claim 20, wherein the secondary switch is a synchronous rectifier (SR).

23. The multiple output power converter system of claim 20, wherein the secondary switch is an auxiliary N-channel field effect transistor (NFET).

24. The multiple output power converter system of claim 20, wherein the selected output is a constant current (CC) output.

25. The multiple output power converter system of claim 20, wherein the selected output is a constant voltage (CV) output.

26. The multiple output power converter system of claim 20, wherein the secondary controller further comprises: A sample and hold circuit is configured to sample a value of the forward pin voltage when the primary switch is operated in an on state.

27. The multi-output power converter system of claim 26, wherein the ZVS calculator is further configured to calculate the hold-up duration associated with values ​​of the selected output voltage and the forward pin voltage such that the primary switch experiences zero voltage switching during the second switching cycle.

28. A method for dynamically switching a primary switch in a power converter, the method comprising: initiating a first switching cycle by closing the primary switch; receiving a forward pin voltage at a forward pin node; disconnecting the primary switch; Receive selected output voltage; Determine the idle ringing period; calculating a hold duration associated with the forward pin voltage, the selected output voltage, and the idle ringing period; as well as The secondary switch is closed during the hold time duration such that the primary switch experiences zero voltage switching during a second switching cycle.

29. The method of claim 28, wherein the secondary switch is a synchronous rectifier.

30. The method of claim 28, wherein the secondary switch is an auxiliary N-channel field effect transistor (NFET).

31. The method of claim 28, wherein the secondary switch is an auxiliary bipolar junction transistor (BJT).

32. The method of claim 28, wherein the power converter is a flyback converter.

33. The method of claim 28, wherein the power converter is a multiple output flyback converter.

34. The method of claim 28, further comprising: Energy is delivered to the selected output to maintain the selected output voltage.

35. The method of claim 28, further comprising: The idle ringing period is determined using a comparator.

36. The method of claim 28, further comprising: determining an off-ringing duration associated with the idle-ringing period; as well as The first switching cycle is completed after the off-ringing duration.

37. The method of claim 36, wherein the off-ringing duration is substantially equal to one quarter of the idle ringing period.

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