Multi-chip stacking packaging structure and packaging method

Abstract

The invention relates to the technical field of chip packaging, in particular to a multi-chip stacked packaging structure and a packaging method. Comprising a rewiring layer, a dry film is arranged on the surface of the rewiring layer, a chip is mounted on the surface of the other side of the dry film, an exposure hole is formed in the dry film, electroplated SnAg is arranged in the exposure hole, and the electroplated SnAg is electrically connected with a metal layer of the rewiring layer and a chip bonding pad. Compared with the prior art, an adhesion layer is formed through a dry film material when the chip FC is carried out, and the use of an Underfill material is avoided. Through SnAg backflow, interconnection between a metal layer in a rewiring layer and a chip bonding pad is realized, Bumps are prevented from being formed on the upper side and the lower side of an FC, the height of a packaging body is reduced, the technological process is simplified, and warping of the packaging body is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, in particular to a multi-chip stacking packaging structure and a packaging method. Background Art

[0002] like Figure 3 As shown, in the existing 2.5D packaging, the chip integration mostly adopts FC+MR technology, which requires the bump production on the Interposer and SoC Chip to be completed in advance, and FC welding to be performed, and then Underfill to fill the Gap between the SoC and the Interposer. Summary of the invention

[0003] In order to overcome the shortcomings of the prior art, the present invention provides a multi-chip stacking packaging structure and a packaging method, in which a SnAg prefabricated layer is formed in a dry film, and only a SnAg layer needs to be formed on a transfer board once, and then the SnAg and the chip pad are interconnected by reflow, and there is no need to use Underfill material, thereby reducing the warping of the package body.

[0004] To achieve the above-mentioned purpose, a multi-chip stacked packaging structure is designed, including a redistribution layer, a dry film is provided on the surface of the redistribution layer, a chip is mounted on the other side of the dry film, an exposure hole is provided in the dry film, and electroplated SnAg is provided in the exposure hole. The electroplated SnAg forms an electrical connection with the metal layer of the redistribution layer and the chip pad.

[0005] The other side surface of the redistribution layer is connected with bumps.

[0006] The outer side of the chip is provided with a plastic seal.

[0007] To achieve the above purpose, a multi-chip stacking packaging method is designed, comprising the following steps: S1, providing a carrier board and coating a release layer on one surface of the carrier board; S2, forming a redistribution layer on the surface of one side of the peeling layer; S3, performing dry film lamination, and exposing after lamination to expose the metal layer of the redistribution layer; S4, dry film curing; S5, performing SnAg electroplating on the exposed surface of the redistribution layer metal layer; S6, performing secondary dry film lamination and exposure to expose SnAg; S7, performing chip bonding, and the chip pad corresponds to the exposure position formed in step S6; S8, plastic sealing and curing; S9, removing the carrier board and peeling layer; S10, bumping is performed on the back side of the redistribution layer.

[0008] In the step S4, the thickness of the dry film after curing is 20±10 um.

[0009] In the step S5, the thickness of the electroplated SnAg is just enough to fill the dry film.

[0010] In the step S6, the CD of the secondary exposure is smaller than the CD of SnAg.

[0011] In the step S6, the dry film is made of a sticky dry film material or a BCB material with a thickness of less than 5 um.

[0012] In the step S8, the curing temperature is less than 160°C.

[0013] In the step S10, after the bumps are electroplated, when they are reflowed into balls, the SnAg in the dry film is also reflowed at the same time, so as to realize the welding between the chip pad and the metal layer of the redistribution layer and realize the electrical connection.

[0014] Compared with the prior art, the present invention forms an adhesion layer during chip FC by using dry film material, thus avoiding the use of underfill material. The metal layer in the redistribution layer is interconnected with the chip pad by SnAg reflow, thus avoiding the formation of bumps on both the upper and lower sides of FC, reducing the height of the package, simplifying the process flow, and reducing the warping of the package. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural schematic diagram of the present invention.

[0016] Figure 2 It is a schematic diagram of the process of the present invention.

[0017] Figure 3 It is a schematic diagram of the prior art before the improvement of the present invention. DETAILED DESCRIPTION

[0018] The present invention will be further described below with reference to the accompanying drawings.

[0019] like Figure 1 As shown, a dry film 2 is provided on the surface of the redistribution layer 1, a chip 3 is mounted on the other side of the dry film 2, an exposure hole 4 is provided in the dry film 2, and electroplated SnAg 5 is provided in the exposure hole 4, and the electroplated SnAg 5 forms an electrical connection with the redistribution layer metal layer 1-1 and the chip pad 3-1. The other side of the redistribution layer 1 is connected to the bump 9. A plastic package 6 is provided on the outside of the chip 3.

[0020] like Figure 2 As shown, the packaging method of the above packaging structure includes the following steps: S1, providing a carrier plate 7, and coating a release layer 8 on one side of the carrier plate 7; S2, forming a redistribution layer 1 on one surface of the peeling layer 8; S3, laminating the dry film 2, and exposing it after lamination to expose the redistribution layer metal layer 1-1; S4, curing of dry film 2; S5, performing SnAg electroplating on the surface of the exposed redistribution layer metal layer 1-1; S6, performing secondary dry film 2 lamination and exposure to expose SnAg; S7, performing chip bonding of the chip 3, and the chip pad 3-1 corresponds to the exposure position formed in step S6; S8, plastic sealing 6, curing, curing temperature <160℃. ; S9, removing the carrier board 7 and the peeling layer 8; S10, manufacturing bumps 9 on the back side of the redistribution layer 1.

[0021] In step S4 of this embodiment, the thickness of the dry film 2 after curing is 20±10 um. In step S5, the thickness of the electroplated SnAg is just enough to fill the dry film 2.

[0022] In step S6, the CD of the secondary exposure is smaller than the CD of SnAg. At this time, the dry film 2 is not cured and has viscosity, which meets the chip mounting requirements, so there is no need to use underfill material.

[0023] In specific use, the dry film 2 in step S6 is made of a sticky dry film material or a BCB material with a thickness of less than 5 um.

[0024] In step S10, after the bumps 9 are electroplated, when they are reflowed into balls, the SnAg 5 in the dry film 2 is also reflowed at the same time, so as to realize welding between the chip pad 3-1 and the redistribution layer metal layer 1-1 and realize electrical connection.

[0025] In the present invention, the Underfill material is replaced by a dry film. In the existing 2.5D packaging process, the upper and lower chips are fixed by FCBump, and the Underfill performs the filling support operation. The present invention utilizes the chip in the step of flip-chip mounting to the dry film 2, in which the intermediate layer itself has viscosity, and plays the role of fixing the chip. The viscosity requirement is to ensure that the flip chip does not shift in the subsequent molding and curing process. In addition, only the upper 5um dry film needs to be sticky, and the dry film used in step S3 does not need to have viscosity requirements.

[0026] In steps S3 and S6, dry film is used twice to form a space for placing SnAg, thereby forming a prefabricated layer of SnAg, so that the chip pad 3-1 and the redistribution layer metal layer 1-1 can be electrically connected during subsequent reflow.

[0027] In the present invention, only one side of the redistribution layer needs to be plated with SnAg to be electrically connected to the chip, and the metal on the other side of the redistribution layer is exposed, thereby reducing the overall welding height.

Claims

1. A multi-chip stacking package structure, comprising a redistribution layer, characterized in that: A dry film (2) is provided on the surface of the redistribution layer (1), a chip (3) is mounted on the other side of the surface of the dry film (2), an exposure hole (4) is provided in the dry film (2), and electroplated SnAg (5) is provided in the exposure hole (4), and the electroplated SnAg (5) forms an electrical connection with the redistribution layer metal layer (1-1) and the chip pad (3-1).

2. The multi-chip stacking package structure according to claim 1, characterized in that: The other side surface of the redistribution layer (1) is connected to a bump (9).

3. The multi-chip stacking package structure according to claim 1, characterized in that: A plastic seal (6) is provided on the outer side of the chip (3).

4. A multi-chip stacking packaging method, characterized in that: The steps include: S1, providing a carrier plate (7), and coating a release layer (8) on one surface of the carrier plate (7); S2, forming a redistribution layer (1) on one surface of the peeling layer (8); S3, laminating the dry film (2), and exposing after lamination to expose the redistribution layer metal layer (1-1); S4, dry film (2) curing; S5, performing SnAg electroplating on the surface of the exposed redistribution layer metal layer (1-1); S6, performing secondary dry film (2) lamination and exposure to expose SnAg; S7, performing chip bonding of the chip (3), and the chip pad (3-1) corresponds to the exposure position formed in step S6; S8, plastic sealing (6), curing; S9, removing the carrier plate (7) and the peeling layer (8); S10, producing bumps (9) on the back side of the redistribution layer (1).

5. The multi-chip stacking packaging method according to claim 1, characterized in that: In the step S4, the thickness of the dry film (2) after curing is 20±10 um.

6. The multi-chip stacking packaging method according to claim 1, characterized in that: In the step S5, the thickness of the electroplated SnAg is just enough to fill the dry film (2).

7. The multi-chip stacking packaging method according to claim 1, characterized in that: In the step S6, the CD of the secondary exposure is smaller than the CD of SnAg.

8. The multi-chip stacking packaging method according to claim 1 or 7, characterized in that: In the step S6, the dry film (2) in the step S6 is made of a sticky dry film material or a BCB material with a thickness of less than 5 um.

9. The multi-chip stacking packaging method according to claim 1, characterized in that: In the step S8, the curing temperature is less than 160°C.

10. The multi-chip stacking packaging method according to claim 1, characterized in that: In the step S10, after the bumps (9) are electroplated, when they are reflowed to form balls, the SnAg (5) in the dry film (2) is also reflowed at the same time, so as to realize welding between the chip pad (3-1) and the redistribution layer metal layer (1-1) and realize electrical connection.

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