A multi-chip stacked package structure and a packaging method

Abstract

The present application relates to chip packaging technical field, specifically a kind of multi-chip stack package structure and packaging method.It includes rewiring layer, the surface of the rewiring layer is equipped with dry film, dry film other side surface paste chip, dry film is equipped with exposure hole, exposure hole is equipped with electroplated SnAg, electroplated SnAg and rewiring layer metal layer, chip pad form electric connection.Compared with prior art, through dry film material, form the adhesion layer when chip FC, avoid the use of Underfill material.Through SnAg reflow, realize the interconnection of metal layer in rewiring layer and chip pad, avoid FC upper and lower both sides to form Bump, reduce the height of package body, simplify process flow, reduce package body warping.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, specifically a multi-chip stacked packaging structure and packaging method. Background Technology

[0002] like Figure 3 As shown, existing 2.5D packaging often uses FC+MR technology for on-chip integration. This requires the bump to be fabricated on both the interposer and the SoC chip in advance, and FC soldering to be performed. Then, the underfill fills the gap between the SoC and the interposer. Summary of the Invention

[0003] To overcome the shortcomings of the prior art, this invention provides a multi-chip stacked packaging structure and packaging method. It uses a dry film to form a SnAg prefabricated layer, which only requires the SnAg layer to be formed once on the adapter board. Subsequently, the SnAg and chip pads are interconnected through reflow, and no underfill material is required, which reduces the warpage of the package.

[0004] To achieve the above objectives, a multi-chip stacked packaging structure is designed, including a redistribution layer. A dry film is provided on the surface of the redistribution layer, and a chip is mounted on the other side of the dry film. An exposure hole is provided in the dry film, and an electroplated SnAg is provided in the exposure hole. The electroplated SnAg forms an electrical connection with the metal layer of the redistribution layer and the chip pads.

[0005] The other side surface of the rewire layer is connected to the protrusion.

[0006] The chip is encapsulated in plastic.

[0007] To achieve the above objectives, a multi-chip stacked packaging method is designed, comprising the following steps:

[0008] S1, providing a carrier plate, and coating a release layer on one side surface of the carrier plate;

[0009] S2, a redistribution layer is formed on one side of the stripping layer;

[0010] S3, dry film lamination is performed, followed by exposure to expose the redistribution layer metal layer;

[0011] S4, dry film curing;

[0012] S5, SnAg electroplating is performed on the exposed redistribution layer metal layer surface;

[0013] S6, perform secondary dry film lamination and exposure to expose SnAg;

[0014] S7, perform chip mounting, and ensure that the chip pads correspond to the exposure positions formed in step S6;

[0015] S8, plastic sealing, curing;

[0016] S9, remove the carrier plate and peel layer;

[0017] S10, create bumps on the back of the redistribution layer.

[0018] In step S4, the thickness of the cured dry film is 20±10um.

[0019] In step S5, the thickness of the electroplated SnAg is just enough to fill the dry film.

[0020] In step S6, the CD of the second exposure is smaller than the CD of SnAg.

[0021] In step S6, the dry film is selected from adhesive dry film materials or BCB materials, with a thickness of less than 5 μm.

[0022] In step S8, the curing temperature is <160℃.

[0023] In step S10, after the bump plating is completed, when the film is reflowed into balls, the SnAg in the dry film also flows back simultaneously, thereby achieving the welding of the chip pads and the redistribution layer metal layer and realizing electrical connection.

[0024] Compared with existing technologies, this invention uses a dry film material to form the adhesive layer during chip FC (Focus Connection), avoiding the use of underfill material. SnAg reflow enables interconnection between the metal layer in the redistribution layer and the chip pads, preventing bump formation on both the top and bottom of the FC, reducing package height, simplifying the process flow, and minimizing package warpage. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of the present invention.

[0026] Figure 2 This is a schematic diagram of the process of the present invention.

[0027] Figure 3 This is a schematic diagram of the prior art before the improvement of this invention. Detailed Implementation

[0028] The present invention will now be further described with reference to the accompanying drawings.

[0029] like Figure 1 As shown, a dry film 2 is provided on the surface of the redistribution layer 1, and a chip 3 is mounted on the other side of the dry film 2. An exposure hole 4 is provided within the dry film 2, and electroplated SnAg 5 is provided within the exposure hole 4. The electroplated SnAg 5 forms an electrical connection with the metal layer 1-1 of the redistribution layer and the chip pad 3-1. A connection bump 9 is provided on the other side of the redistribution layer 1. A plastic encapsulation 6 is provided on the outer side of the chip 3.

[0030] like Figure 2 As shown, the packaging method of the above-mentioned packaging structure includes the following steps:

[0031] S1, a carrier plate 7 is provided, and a release layer 8 is coated on one side surface of the carrier plate 7;

[0032] S2, a redistribution layer 1 is formed on one side surface of the stripping layer 8;

[0033] S3, perform dry film 2 lamination, and expose after lamination to expose the redistribution layer metal layer 1-1;

[0034] S4, dry film 2-stage curing;

[0035] S5, SnAg electroplating is performed on the exposed redistribution layer metal layer 1-1 surface;

[0036] S6, perform secondary dry film pressing and exposure to expose SnAg;

[0037] S7, chip 3 is mounted, and chip pad 3-1 corresponds to the exposure position formed in step S6;

[0038] S8, encapsulation 6, curing, curing temperature <160℃.

[0039] S9, remove carrier plate 7 and peeling layer 8;

[0040] S10, create bumps 9 on the back side of the redistribution layer 1.

[0041] In step S4 of this embodiment, the thickness of the cured dry film 2 is 20±10 μm. In step S5, the thickness of the electroplated SnAg is just enough to fill the dry film 2.

[0042] In step S6, the CD of the second exposure is smaller than that of SnAg. At this point, the dry film 2 is not cured and has adhesive properties, which meets the chip mounting requirements, thus eliminating the need for underfill material.

[0043] In practical use, the dry film 2 in step S6 is selected from a dry film material with adhesive properties or BCB material, with a thickness of less than 5 μm.

[0044] In step S10, after the bump 9 is electroplated, when it is reflowed into balls, the SnAg5 in the dry film 2 also reflows simultaneously, realizing the welding of the chip pad 3-1 and the redistribution layer metal layer 1-1, and achieving electrical connection.

[0045] In this invention, a dry film replaces the underfill material. In existing 2.5D packaging processes, FCBump is used to fix the upper and lower chips, with the underfill providing filling and support. In this invention, during the flip-chip bonding to the dry film 2 step, the intermediate layer itself has adhesive properties, which helps to fix the chip. This adhesiveness is required to prevent the flip-chip from shifting during the subsequent molding and curing process. Furthermore, only the upper 5µm dry film needs to be adhesive; the dry film used in step S3 does not require adhesiveness.

[0046] Steps S3 and S6 utilize the dry film twice to create a space for placing SnAg, thereby forming a SnAg prefabrication layer so that the chip pad 3-1 can form an electrical connection with the redistribution layer metal layer 1-1 during subsequent reflow.

[0047] In this invention, the redistribution layer only needs to be electroplated with SnAg on one side to be electrically connected to the chip, while the metal on the other side of the redistribution layer is exposed, thereby reducing the overall soldering height.

Claims

1. A multi-chip stacked packaging method, characterized in that: Includes the following steps: S1, a carrier plate (7) is provided, and a release layer (8) is coated on one side surface of the carrier plate (7); S2, a redistribution layer (1) is formed on one side of the surface of the stripping layer (8); S3, dry film (2) is pressed, and after pressing, it is exposed to expose the redistribution layer metal layer (1-1). S4, dry film (2) cured; S5, SnAg electroplating is performed on the exposed redistribution layer metal layer (1-1); S6, perform secondary dry film (2) pressing and exposure to expose SnAg; S7, chip (3) is mounted, and the chip pad (3-1) corresponds to the exposure position formed in step S6; S8, plastic seal (6), cure; S9, Remove carrier plate (7) and peeling layer (8); S10, make bumps (9) on the back of the redistribution layer (1).

2. The multi-chip stacked packaging method according to claim 1, characterized in that: In step S4, the thickness of the cured dry film (2) is 20±10um.

3. The multi-chip stacked packaging method according to claim 1, characterized in that: In step S5, the thickness of the electroplated SnAg is just enough to fill the dry film (2).

4. The multi-chip stacked packaging method according to claim 1, characterized in that: In step S6, the CD of the second exposure is smaller than the CD of SnAg.

5. A multi-chip stacked packaging method according to claim 1 or 4, characterized in that: In step S6, the dry film (2) is selected from adhesive dry film material or BCB material with a thickness of less than 5 μm.

6. The multi-chip stacked packaging method according to claim 1, characterized in that: In step S8, the curing temperature is <160℃.

7. A multi-chip stacked packaging method according to claim 1, characterized in that: In step S10, after the bump (9) is electroplated, when it is reflowed into a ball, the SnAg (5) in the dry film (2) also flows back at the same time, so as to realize the welding of the chip pad (3-1) and the redistribution layer metal layer (1-1) and realize electrical connection.

8. The multi-chip stacked package structure obtained by the multi-chip stacked package method according to any one of claims 1 to 7, comprising a redistribution layer, characterized in that: The redistribution layer (1) has a dry film (2) on its surface, and a chip (3) is mounted on the other side of the dry film (2). An exposure hole (4) is provided in the dry film (2), and an electroplated SnAg (5) is provided in the exposure hole (4). The electroplated SnAg (5) forms an electrical connection with the redistribution layer metal layer (1-1) and the chip pad (3-1).

9. A multi-chip stacked packaging structure according to claim 8, characterized in that: The other side surface of the rewiring layer (1) is connected to the protrusion (9).

10. A multi-chip stacked packaging structure according to claim 8, characterized in that: The chip (3) is encapsulated in plastic (6) on its outer side.

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