High-linearity grid voltage bootstrap switch capable of reducing clock feed-through effect
By introducing compensation circuit modules and dummy transistors into the gate voltage bootstrap switch, the problem of linearity limitation caused by the clock feedthrough effect is solved, and a higher linearity is achieved.
Patent Information
- Application Number
- CN202510045112.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-13
- Publication Date
- 2025-05-09
AI Technical Summary
Due to the influence of the clock feedthrough effect, the linearity of the existing gate voltage bootstrap switch is limited, making it difficult to achieve high linearity.
The compensation circuit module is added on the basis of the traditional gate voltage bootstrap switch, and the nonlinear error caused by the clock feedthrough effect is offset by introducing dummy transistors with the same size as the MOS sampling switch.
Through the use of the compensation circuit module, the nonlinear error caused by the input signal component is significantly reduced, and the linearity of the gate voltage bootstrap switch is improved.
Smart Images
Figure CN119966391A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of analog circuits, and in particular relates to a high-linearity gate voltage bootstrap switch capable of reducing clock feedthrough effect. Background Art
[0002] With the continuous development of signal processing technology and the emergence of more and more smart devices, people's demand for high-precision signals is growing. To obtain high-precision digital signals, they must first be sampled from the analog world, and sampling requires a sampling switch.
[0003] Due to the linearity limitation of CMOS sampling switch, people have proposed gate voltage bootstrap sampling switch, which uses different gate voltages in sampling state and holding state to improve the accuracy of sampling switch. However, the linearity of previous gate voltage bootstrap switch is also limited due to the clock feedthrough effect. Therefore, designing a gate voltage bootstrap switch with higher linearity has become an urgent issue. Summary of the invention
[0004] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a high-linearity gate voltage bootstrap switch that reduces the clock feedthrough effect.
[0005] In order to solve the above technical problems, the present invention provides the following technical solutions:
[0006] A high linearity gate voltage bootstrap switch with reduced clock feedthrough effect, comprising:
[0007] MOS sampling switch, used to sample and hold the input signal;
[0008] A gate voltage bootstrap module is used to enable the MOS sampling switch to perform sampling in the sampling phase to achieve the purpose of gate voltage bootstrap, and to turn off the MOS sampling switch tube in the holding phase;
[0009] A charge pump boost module, used to compensate for the change in the threshold voltage of the gate voltage bootstrap module and increase the gate voltage of the MOS sampling switch; and
[0010] The compensation circuit module is used to compensate for the error caused by the clock feedthrough effect of the MOS sampling switch.
[0011] Further, the MOS sampling switch is defined as an eighth NMOS tube M10; the source of the eighth NMOS tube M10 is used as the output end of the gate voltage bootstrap switch for outputting the voltage VOUT, the gate of the eighth NMOS tube M10 is electrically connected to the fourth node d, and the drain of the eighth NMOS tube M10 is connected to the input signal.
[0012] Furthermore, when the gate voltage bootstrap switch transitions from the sampling stage to the holding stage, the error voltage V generated at the output end of the eighth NMOS tube M10 due to the clock feedthrough effect is:
[0013]
[0014] Among them, C ov10 represents the overlapping capacitance between the gate, drain and source of the eighth NMOS tube M10; C h Represents the capacitance of the load capacitor driven by the gate voltage bootstrap switch; V IN Indicates the voltage of the input signal; V DD Indicates the voltage of the power supply.
[0015] Further, the compensation circuit module includes a fourth PMOS tube M14, an eleventh NMOS tube M15, a twelfth NMOS tube M16, a thirteenth NMOS tube M17, a fourteenth NMOS tube M18 and a third capacitor C3;
[0016] The source of the fourth PMOS transistor M14 and the drain of the fourteenth NMOS transistor M18 are electrically connected to a fifth node e, the drain of the fourth PMOS transistor M14 is connected to the clock signal CLKN, and the drain of the fourth PMOS transistor M14 and the first end of the third capacitor are electrically connected to a sixth node f;
[0017] The source of the eleventh NMOS transistor M15 is electrically connected to the sixth node f, the gate of the eleventh NMOS transistor M15 is connected to the clock signal CLKN, and the drain of the eleventh NMOS transistor M15 is connected to the input signal;
[0018] The source of the twelfth NMOS transistor M16 is electrically connected to the sixth node f, the gate of the twelfth NMOS transistor M16 is connected to the clock signal CLK, and the drain of the twelfth NMOS transistor M16 is electrically connected to the fifth node e;
[0019] The source of the thirteenth NMOS tube M17 is electrically connected to the source of the eighth NMOS tube M10, the gate of the thirteenth NMOS tube M17 is electrically connected to the fifth node e, and the drain of the thirteenth NMOS tube M17 is connected to the power supply;
[0020] The source of the fourteenth NMOS transistor M18 is grounded, the gate of the fourteenth NMOS transistor M18 is connected to the clock signal CLKN, and the drain of the fourteenth NMOS transistor M18 is electrically connected to the fifth node e.
[0021] Furthermore, the thirteenth NMOS transistor M17 has the same size as the eighth NMOS transistor M10.
[0022] Furthermore, when the gate voltage bootstrap switch transitions from the sampling phase to the holding phase, the compensation voltage V generated at the output end by the compensation circuit module c for:
[0023]
[0024] Among them, C ov17 represents the overlapping capacitance between the gate, drain and source of the thirteenth NMOS tube M17; C h It represents the capacitance of the load capacitor driven by the gate voltage bootstrap switch; VIN represents the voltage of the input signal.
[0025] Further, the gate voltage bootstrap module includes a first NMOS tube M1, a first PMOS tube M2, a second PMOS tube M3, a second NMOS tube M4, a third NMOS tube M5, a fourth NMOS tube M6, a fifth NMOS tube M7, a sixth NMOS tube M8, a seventh NMOS tube M9 and a first capacitor C1;
[0026] The source of the first NMOS transistor M1 is grounded, the gate of the first NMOS transistor M1 is connected to the clock signal CLK, and the drain of the first NMOS transistor M1 and the first end of the first capacitor C1 are electrically connected to a first node a;
[0027] The source of the first PMOS transistor M2 is connected to a power supply, the gate of the first PMOS transistor M2 is connected to a clock signal CLKN, and the drain of the first PMOS transistor M2 and the gate of the second PMOS transistor M3 are electrically connected to a second node b;
[0028] The source of the second PMOS transistor M3 and the second end of the first capacitor C1 are electrically connected to a third node c, the gate of the second PMOS transistor M3 is electrically connected to a second node b, and the drain of the second PMOS transistor M3 and the gate of the second NMOS transistor M4 are electrically connected to a fourth node d;
[0029] The source of the second NMOS transistor M4 is electrically connected to the first node a, the gate of the second NMOS transistor M4 is electrically connected to the fourth node d, and the drain of the second NMOS transistor M4 is electrically connected to the drain of the MOS sampling switch;
[0030] The source of the third NMOS transistor M5 is electrically connected to the first node a, and the gate of the third NMOS transistor M5 is connected to the clock signal CLKN; the drain of the third NMOS transistor M5 is electrically connected to the second node b;
[0031] The source of the fourth NMOS transistor M6 is electrically connected to the first node a, the gate of the fourth NMOS transistor M6 is electrically connected to the fourth node d, and the drain of the fourth NMOS transistor M6 is electrically connected to the second node b;
[0032] The source of the fifth NMOS tube M7 is electrically connected to the source of the sixth NMOS tube, the gate of the fifth NMOS tube M7 is connected to the power supply, and the drain of the fifth NMOS tube M7 is electrically connected to the fourth node d;
[0033] The source of the sixth NMOS transistor M8 is electrically connected to the source of the fifth NMOS transistor M7, the gate of the sixth NMOS transistor M8 is connected to the clock signal CLK, and the drain of the sixth NMOS transistor M8 is grounded;
[0034] The source of the seventh NMOS transistor M9 is electrically connected to the third node c, the gate of the seventh NMOS transistor M9 is electrically connected to the charge pump boost module, and the drain of the seventh NMOS transistor M9 is connected to the power supply.
[0035] Further, the charge pump boost module includes a third PMOS tube M11, a ninth NMOS tube M12, a tenth NMOS tube M13 and a second capacitor C2; the source of the third PMOS tube M11 is connected to the power supply, the gate of the third PMOS tube M11 is connected to the clock signal CLKN, and the drain of the third PMOS tube M11 is electrically connected to the first end of the second capacitor C2;
[0036] The source of the ninth NMOS transistor M12 is grounded, the gate of the ninth NMOS transistor M12 is connected to the clock signal CLKN, and the drain of the ninth NMOS transistor M12 is electrically connected to the first end of the second capacitor C2;
[0037] The source of the tenth NMOS tube M13 is electrically connected to the second end of the second capacitor C2, the gate and drain of the tenth NMOS tube M13 are both connected to the power supply, and the second end of the second capacitor C2 is electrically connected to the gate of the seventh NMOS tube M9.
[0038] Furthermore, when the clock signal CLK is at a high level and the clock signal CLKN is at a low level, the gate voltage bootstrap switch enters a holding phase; when the clock signal CLKN is at a high level and the clock signal CLK is at a low level, the gate voltage bootstrap switch enters a sampling phase.
[0039] In the present invention, in order to solve the nonlinear error caused by the clock feedthrough effect, a compensation circuit module is added on the basis of the traditional gate voltage bootstrap switch, and the nonlinear error caused by the clock feedthrough effect is offset by adding the compensation circuit module. In the compensation circuit module, a dummy transistor with the same size as the MOS sampling switch is newly introduced. When undergoing the sampling and holding stage, the clock feedthrough effect of the dummy transistor and the clock feedthrough effect of the sampling tube are offset, thereby greatly reducing the nonlinear error caused by the component of the input signal. In addition, this embodiment does not change the architecture of the traditional gate voltage bootstrap switch, but only improves the linearity by introducing several MOS tubes, which saves transistor overhead while not affecting the overall operation of the sampling system. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0041] Figure 1 A circuit diagram of an embodiment of a high linearity gate voltage bootstrap switch for reducing clock feedthrough effect according to the present invention.
[0042] The accompanying drawings in the specification are numeraled as follows:
[0043] Gate voltage bootstrap module-100; charge pump boost module-200; compensation circuit module-300. DETAILED DESCRIPTION
[0044] The following describes the implementation methods of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other without conflict.
[0045] See also Figure 1 , Figure 1 The circuit diagram of an embodiment of a high-linearity gate voltage bootstrap switch for reducing clock feedthrough effect of the present invention. The high-linearity gate voltage bootstrap switch for reducing clock feedthrough effect of this embodiment includes a gate voltage bootstrap module 100, a charge pump boost module 200, a MOS sampling switch and a compensation circuit module 300. The gate voltage bootstrap module 100 is used to make the MOS sampling switch perform sampling in the sampling stage to achieve the purpose of gate voltage bootstrap, and to turn off the MOS sampling switch tube in the holding stage. The charge pump boost module 200 is used to compensate for the change of the threshold voltage of the gate voltage bootstrap module 100, increase the gate voltage of the MOS sampling switch, and reduce the on-resistance of the MOS sampling switch. The MOS sampling switch is used to input the input signal V INThe compensation circuit module 300 is used to compensate for the error caused by the clock feedthrough effect of the MOS sampling switch.
[0046] The gate voltage bootstrap module 100 may include a first NMOS transistor M1, a first PMOS transistor M2, a second PMOS transistor M3, a second NMOS transistor M4, a third NMOS transistor M5, a fourth NMOS transistor M6, a fifth NMOS transistor M7, a sixth NMOS transistor M8, a seventh NMOS transistor M9 and a first capacitor C1. The source of the first NMOS transistor M1 is grounded, the gate of the first NMOS transistor M1 is connected to the clock signal CLK, the drain of the first NMOS transistor M1 and the first end of the first capacitor C1 are electrically connected to the first node a. The source of the first PMOS transistor M2 is connected to the power supply V DD , the gate of the first PMOS transistor M2 is connected to the clock signal CLKN, the drain of the first PMOS transistor M2 and the gate of the second PMOS transistor M3 are electrically connected to the second node b. The source of the second PMOS transistor M3 and the second end of the first capacitor C1 are electrically connected to the third node c, the gate of the second PMOS transistor M3 is electrically connected to the second node b, the drain of the second PMOS transistor M3 and the gate of the second NMOS transistor M4 are electrically connected to the fourth node d. The source of the second NMOS transistor M4 is electrically connected to the first node a, the gate of the second NMOS transistor M4 is electrically connected to the fourth node d, and the drain of the second NMOS transistor M4 is electrically connected to the drain of the MOS sampling switch.
[0047] The source of the third NMOS tube M5 is electrically connected to the first node a, and the gate of the third NMOS tube M5 is connected to the clock signal CLKN; the drain of the third NMOS tube M5 is electrically connected to the second node b. The source of the fourth NMOS tube M6 is electrically connected to the first node a, the gate of the fourth NMOS tube M6 is electrically connected to the fourth node d, and the drain of the fourth NMOS tube M6 is electrically connected to the second node b. The source of the fifth NMOS tube M7 is electrically connected to the source of the sixth NMOS tube, and the gate of the fifth NMOS tube M7 is connected to the power supply V DD , the drain of the fifth NMOS tube M7 is electrically connected to the fourth node d. The source of the sixth NMOS tube M8 is electrically connected to the source of the fifth NMOS tube M7, the gate of the sixth NMOS tube M8 is connected to the clock signal CLK, and the drain of the sixth NMOS tube M8 is grounded. The source of the seventh NMOS tube M9 is electrically connected to the third node c, the gate of the seventh NMOS tube M9 is electrically connected to the charge pump boost module 200, and the drain of the seventh NMOS tube M9 is connected to the power supply V DD .
[0048] The charge pump boost module 200 may include a third PMOS transistor M11, a ninth NMOS transistor M12, a tenth NMOS transistor M13 and a second capacitor C2; the source of the third PMOS transistor M11 is connected to the power supply V DD The gate of the third PMOS tube M11 is connected to the clock signal CLKN, and the drain of the third PMOS tube M11 is electrically connected to the first end of the second capacitor C2. The source of the ninth NMOS tube M12 is grounded, the gate of the ninth NMOS tube M12 is connected to the clock signal CLKN, and the drain of the ninth NMOS tube M12 is electrically connected to the first end of the second capacitor C2. The source of the tenth NMOS tube M13 is electrically connected to the second end of the second capacitor C2, and the gate and drain of the tenth NMOS tube M13 are both connected to the power supply V DD , the second end of the second capacitor C2 is electrically connected to the gate of the seventh NMOS transistor M9.
[0049] When the clock signal CLKN is at a high level, the ninth NMOS transistor M12 is turned on, pulling the left plate of the second capacitor C2 (i.e., the first end of the second capacitor C2) down to ground. At this time, the tenth NMOS transistor M13 is turned on, pulling the right plate of the second capacitor C2 (i.e., the second end of the second capacitor C2) up to about V DD , the voltage difference between the two plates of the second capacitor C2 is about V DD When the clock signal CLKN is at a low level, the third PMOS tube M11 is turned on, pulling the left plate of the second capacitor C2 up to V DD Since the charge on the capacitor cannot change suddenly, the voltage on the right plate of the second capacitor C2 becomes about 2V. DD , the tenth NMOS tube M13 is turned off at this time.
[0050] In this embodiment, the MOS sampling switch is defined as the eighth NMOS transistor M10. The source of the eighth NMOS transistor M10 is used as the output end of the gate voltage bootstrap switch to output the voltage VOUT to drive the load capacitor C4 of the subsequent stage. The gate of the eighth NMOS transistor M10 is electrically connected to the fourth node d, and the drain of the eighth NMOS transistor M10 is connected to the input signal V IN .
[0051] The compensation circuit module 300 may include a fourth PMOS transistor M14, an eleventh NMOS transistor M15, a twelfth NMOS transistor M16, a thirteenth NMOS transistor M17, a fourteenth NMOS transistor M18 and a third capacitor C3. The thirteenth NMOS transistor M17 has the same size as the eighth NMOS transistor M10.
[0052] The source of the fourth PMOS transistor M14 and the drain of the fourteenth NMOS transistor M18 are electrically connected to the fifth node e, the drain of the fourth PMOS transistor M14 is connected to the clock signal CLKN, and the drain of the fourth PMOS transistor M14 and the first end of the third capacitor are electrically connected to the sixth node f. The source of the eleventh NMOS transistor M15 is electrically connected to the sixth node f, the gate of the eleventh NMOS transistor M15 is connected to the clock signal CLKN, and the drain of the eleventh NMOS transistor M15 is connected to the input signal V IN .
[0053] The source of the twelfth NMOS transistor M16 is electrically connected to the sixth node f, the gate of the twelfth NMOS transistor M16 is connected to the clock signal CLK, and the drain of the twelfth NMOS transistor M16 is electrically connected to the fifth node e. The source of the thirteenth NMOS transistor M17 is electrically connected to the source of the eighth NMOS transistor M10, the gate of the thirteenth NMOS transistor M17 is electrically connected to the fifth node e, and the drain of the thirteenth NMOS transistor M17 is connected to the power supply V DD The source of the fourteenth NMOS transistor M18 is grounded, the gate of the fourteenth NMOS transistor M18 is connected to the clock signal CLKN, and the drain of the fourteenth NMOS transistor M18 is electrically connected to the fifth node e.
[0054] The specific principles of this embodiment are as follows:
[0055] See also Figure 1 , when the clock signal CLK is at a high level and the clock signal CLKN is at a low level, the gate voltage bootstrap switch enters the holding stage. At this time, the first NMOS tube M1 is turned on, pulling the first node a down to the ground. According to the principle of the charge pump boost module 200, at this time, the right plate voltage of the second capacitor C2 is about 2VDD, so the seventh NMOS tube M9 is fully turned on and the threshold loss can be ignored, so that the right plate of the first capacitor C1 (i.e., the second end of the first capacitor C1) is fully charged to the voltage V DD , turning on the first PMOS tube M2 and pulling the second node b up to the power supply voltage V DD Therefore, the second PMOS tube M3 is turned off, the third NMOS tube M5 is turned off, the sixth NMOS tube M8 is turned on, and the fifth NMOS tube M7 is turned on, pulling the fourth node d down to ground. Therefore, the second NMOS tube M4 and the fourth NMOS tube M6 are turned off. At this time, the gate voltage bootstrap switch enters the holding state, and the first capacitor C1 is charged to about V by the first NMOS tube M1 and the seventh NMOS tube M9. DD At the same time, the bootstrap capacitor (ie, the first capacitor C1) is isolated from the MOS sampling switch (ie, the eighth NMOS tube M10), the eighth NMOS tube M10 remains turned off, and the output signal is maintained.
[0056] When the clock signal CLKN is at a high level and the clock signal CLK is at a low level, the gate voltage bootstrap switch enters the sampling phase. At this time, the first NMOS tube M1 is turned off, the third NMOS tube M5 is turned on, and the second node b is pulled down to a low level. The second PMOS tube M3 is turned on, and the right plate of the first capacitor C1 is connected to the gate of the NMOS tube M10. Since the second PMOS tube M3 is turned on, the fourth node d is pulled up to the power supply, so the second NMOS tube M4 is turned on, so that the left plate of the first capacitor C1 (i.e., the first end of the first capacitor C1) is connected to the drain of the NMOS tube M10. Since the fourth node d is at a high level, the fourth NMOS tube M6 is turned on, and this process accelerates the pulling down of the second node b. At the same time, the fourth NMOS tube M6 also exists as a switch startup circuit. It can be seen from the working process of the charge pump boost module 200 that at this time, the voltage of the right plate of the second capacitor C2 is V DD Therefore, the seventh NMOS tube M9 is turned off, the fifth NMOS tube M7 is turned on, the sixth NMOS tube M8 is turned off, and the first PMOS tube M2 is turned off. At this time, the gate voltage bootstrap switch enters the sampling stage, and the bootstrap capacitor is connected across the gate and drain of the eighth NMOS tube M10, so that the on-resistance of the gate voltage bootstrap switch remains constant.
[0057] When the gate voltage bootstrap switch is in the sampling stage, its on-resistance R on The calculation formula is as follows:
[0058]
[0059] Among them, μ n represents the carrier mobility; C OX represents the unit area gate capacitance of the eighth NMOS tube M10; W / L represents the width-to-length ratio of the eighth NMOS tube M10; V GS represents the gate-source voltage of the eighth NMOS tube M10; V DD Indicates the voltage of the power supply; V TH represents the turn-on threshold voltage of the eighth NMOS tube M10.
[0060] The conventional gate voltage bootstrap switch solves the problem that the on-resistance changes with the input signal. However, the linearity of the gate voltage switch is not only affected by the resistance, but also by the capacitance. When the bootstrap switch switches between the sampling stage and the holding stage, due to the feedthrough effect of the clock, there will be charges transferred from the gate of the eighth NMOS tube M10 to its source and drain terminals, thereby causing errors related to the signal. This error cannot be eliminated by the differential circuit. For example, when the gate voltage bootstrap switch changes from the sampling stage to the holding stage, the gate voltage of the eighth NMOS tube M10 quickly changes from V DD +V INWhen the clock turns to 0, due to the clock feedthrough effect, an error voltage V will be generated at the output, which is calculated as follows:
[0061]
[0062] Among them, C ov10 represents the overlapping capacitance between the gate, drain and source of the eighth NMOS tube M10; C h Represents the capacitance of the load capacitor C4 driven by the gate voltage bootstrap switch; V IN Indicates the voltage of the input signal. The error voltage V is related to the power supply V DD The component can be eliminated by the differential circuit, but the input signal V IN The component is related to the input signal, which will cause the nonlinearity of the system and needs to be eliminated by the compensation circuit.
[0063] In the compensation circuit module 300, the thirteenth NMOS transistor M17 is a dummy transistor with the same size as the eighth NMOS transistor M10, and it is always turned off. IN The eleventh NMOS tube M15 is synchronously sampled on the third capacitor C3, and the gate of the thirteenth NMOS tube M17 is pulled down to the ground. When transitioning to the holding stage, the eleventh NMOS tube M15 and the fourteenth NMOS tube M18 are immediately disconnected, and the gate of the thirteenth NMOS tube M17 is pulled up to the input signal V by the third capacitor C3 through the twelfth NMOS tube M16 and the fourth PMOS tube M14. IN At this time, due to the clock feedthrough effect of the thirteenth NMOS tube M17, according to the principle of charge conservation, it can be concluded that the compensation voltage V generated at the output c for:
[0064]
[0065] Among them, C ov17 = represents the overlapping capacitance between the gate, drain and source of the thirteenth NMOS transistor M17. Since the thirteenth NMOS transistor M17 and the eighth NMOS transistor M10 have the same size, their overlapping capacitances are almost the same, that is, C ov17 =C ov10 Therefore, most of the nonlinear errors can be compensated by the compensation circuit module 300, thereby improving the linearity of the gate voltage bootstrap switch.
[0066] In this embodiment, in order to solve the nonlinear error caused by the clock feedthrough effect, a compensation circuit module 300 is added on the basis of the traditional gate voltage bootstrap switch, and the nonlinear error caused by the clock feedthrough effect is offset by adding the compensation circuit module 300. In the compensation circuit module 300, a dummy transistor with the same size as the MOS sampling switch is newly introduced. When undergoing the sampling and holding stage, the clock feedthrough effect of the dummy transistor and the clock feedthrough effect of the sampling tube are offset, thereby greatly reducing the nonlinear error caused by the component of the input signal. In addition, this embodiment does not change the architecture of the traditional gate voltage bootstrap switch, but only improves the linearity by introducing several MOS tubes, which saves transistor overhead while not affecting the overall operation of the sampling system.
[0067] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.
Claims
1. A high linearity gate voltage bootstrap switch for reducing clock feedthrough effect, characterized in that: include: MOS sampling switch, used to sample and hold the input signal; A gate voltage bootstrap module is used to enable the MOS sampling switch to perform sampling in the sampling phase to achieve the purpose of gate voltage bootstrap, and to turn off the MOS sampling switch tube in the holding phase; A charge pump boost module, used to compensate for the change in the threshold voltage of the gate voltage bootstrap module and increase the gate voltage of the MOS sampling switch; and The compensation circuit module is used to compensate for the error caused by the clock feedthrough effect of the MOS sampling switch.
2. The high linearity gate voltage bootstrap switch with reduced clock feedthrough effect as claimed in claim 1, characterized in that: The MOS sampling switch is defined as the eighth NMOS tube M10; the source of the eighth NMOS tube M10 is used as the output end of the gate voltage bootstrap switch for outputting the voltage VOUT, the gate of the eighth NMOS tube M10 is electrically connected to the fourth node d, and the drain of the eighth NMOS tube M10 is connected to the input signal.
3. The high linearity gate voltage bootstrap switch with reduced clock feedthrough effect as claimed in claim 2, characterized in that: When the gate voltage bootstrap switch transitions from the sampling stage to the holding stage, the error voltage V generated at the output end of the eighth NMOS tube M10 due to the clock feedthrough effect is: Among them, C ov10 represents the overlapping capacitance between the gate, drain and source of the eighth NMOS tube M10; C h Represents the capacitance of the load capacitor driven by the gate voltage bootstrap switch; V IN Indicates the voltage of the input signal; V DD Indicates the voltage of the power supply.
4. The high linearity gate voltage bootstrap switch with reduced clock feedthrough effect as claimed in claim 2, characterized in that: The compensation circuit module includes a fourth PMOS transistor M14, an eleventh NMOS transistor M15, a twelfth NMOS transistor M16, a thirteenth NMOS transistor M17, a fourteenth NMOS transistor M18 and a third capacitor C3; The source of the fourth PMOS transistor M14 and the drain of the fourteenth NMOS transistor M18 are electrically connected to a fifth node e, the drain of the fourth PMOS transistor M14 is connected to the clock signal CLKN, and the drain of the fourth PMOS transistor M14 and the first end of the third capacitor are electrically connected to a sixth node f; The source of the eleventh NMOS transistor M15 is electrically connected to the sixth node f, the gate of the eleventh NMOS transistor M15 is connected to the clock signal CLKN, and the drain of the eleventh NMOS transistor M15 is connected to the input signal; The source of the twelfth NMOS transistor M16 is electrically connected to the sixth node f, the gate of the twelfth NMOS transistor M16 is connected to the clock signal CLK, and the drain of the twelfth NMOS transistor M16 is electrically connected to the fifth node e; The source of the thirteenth NMOS tube M17 is electrically connected to the source of the eighth NMOS tube M10, the gate of the thirteenth NMOS tube M17 is electrically connected to the fifth node e, and the drain of the thirteenth NMOS tube M17 is connected to the power supply; The source of the fourteenth NMOS transistor M18 is grounded, the gate of the fourteenth NMOS transistor M18 is connected to the clock signal CLKN, and the drain of the fourteenth NMOS transistor M18 is electrically connected to the fifth node e.
5. The high linearity gate voltage bootstrap switch with reduced clock feedthrough effect as claimed in claim 4, characterized in that: The thirteenth NMOS transistor M17 has the same size as the eighth NMOS transistor M10.
6. The high linearity gate voltage bootstrap switch with reduced clock feedthrough effect as claimed in claim 4, characterized in that: When the gate voltage bootstrap switch transitions from the sampling phase to the holding phase, the compensation voltage V generated by the compensation circuit module at the output end c for: Among them, C ov17 represents the overlapping capacitance between the gate, drain and source of the thirteenth NMOS tube M17; C h It represents the capacitance of the load capacitor driven by the gate voltage bootstrap switch; VIN represents the voltage of the input signal.
7. The high linearity gate voltage bootstrap switch with reduced clock feedthrough effect according to any one of claims 1 to 6, characterized in that: The gate voltage bootstrap module includes a first NMOS tube M1, a first PMOS tube M2, a second PMOS tube M3, a second NMOS tube M4, a third NMOS tube M5, a fourth NMOS tube M6, a fifth NMOS tube M7, a sixth NMOS tube M8, a seventh NMOS tube M9 and a first capacitor C1; The source of the first NMOS transistor M1 is grounded, the gate of the first NMOS transistor M1 is connected to the clock signal CLK, and the drain of the first NMOS transistor M1 and the first end of the first capacitor C1 are electrically connected to a first node a; The source of the first PMOS transistor M2 is connected to a power supply, the gate of the first PMOS transistor M2 is connected to a clock signal CLKN, and the drain of the first PMOS transistor M2 and the gate of the second PMOS transistor M3 are electrically connected to a second node b; The source of the second PMOS transistor M3 and the second end of the first capacitor C1 are electrically connected to a third node c, the gate of the second PMOS transistor M3 is electrically connected to a second node b, and the drain of the second PMOS transistor M3 and the gate of the second NMOS transistor M4 are electrically connected to a fourth node d; The source of the second NMOS transistor M4 is electrically connected to the first node a, the gate of the second NMOS transistor M4 is electrically connected to the fourth node d, and the drain of the second NMOS transistor M4 is electrically connected to the drain of the MOS sampling switch; The source of the third NMOS transistor M5 is electrically connected to the first node a, and the gate of the third NMOS transistor M5 is connected to the clock signal CLKN; the drain of the third NMOS transistor M5 is electrically connected to the second node b; The source of the fourth NMOS transistor M6 is electrically connected to the first node a, the gate of the fourth NMOS transistor M6 is electrically connected to the fourth node d, and the drain of the fourth NMOS transistor M6 is electrically connected to the second node b; The source of the fifth NMOS tube M7 is electrically connected to the source of the sixth NMOS tube, the gate of the fifth NMOS tube M7 is connected to the power supply, and the drain of the fifth NMOS tube M7 is electrically connected to the fourth node d; The source of the sixth NMOS transistor M8 is electrically connected to the source of the fifth NMOS transistor M7, the gate of the sixth NMOS transistor M8 is connected to the clock signal CLK, and the drain of the sixth NMOS transistor M8 is grounded; The source of the seventh NMOS transistor M9 is electrically connected to the third node c, the gate of the seventh NMOS transistor M9 is electrically connected to the charge pump boost module, and the drain of the seventh NMOS transistor M9 is connected to the power supply.
8. The high linearity gate voltage bootstrap switch with reduced clock feedthrough effect as claimed in claim 7, characterized in that: The charge pump boost module includes a third PMOS tube M11, a ninth NMOS tube M12, a tenth NMOS tube M13 and a second capacitor C2; the source of the third PMOS tube M11 is connected to the power supply, the gate of the third PMOS tube M11 is connected to the clock signal CLKN, and the drain of the third PMOS tube M11 is electrically connected to the first end of the second capacitor C2; The source of the ninth NMOS transistor M12 is grounded, the gate of the ninth NMOS transistor M12 is connected to the clock signal CLKN, and the drain of the ninth NMOS transistor M12 is electrically connected to the first end of the second capacitor C2; The source of the tenth NMOS tube M13 is electrically connected to the second end of the second capacitor C2, the gate and drain of the tenth NMOS tube M13 are both connected to the power supply, and the second end of the second capacitor C2 is electrically connected to the gate of the seventh NMOS tube M9.
9. The high linearity gate voltage bootstrap switch with reduced clock feedthrough effect as claimed in claim 7, characterized in that: When the clock signal CLK is at a high level and the clock signal CLKN is at a low level, the gate voltage bootstrap switch enters a holding phase; when the clock signal CLKN is at a high level and the clock signal CLK is at a low level, the gate voltage bootstrap switch enters a sampling phase.