Two-stage injection locking eight-phase clock generator

Abstract

The invention discloses a two-stage injection locking 8-phase clock generator, relates to the technical field of semiconductor chips, constructs a simplified quadrature phase locking loop, injects a group of differential clock signals into a feedforward annular voltage-controlled oscillator, outputs 8-phase clock signals, judges an injection locking phase relationship by a quadrature phase detector, and finally, outputs a set of differential clock signals to the feedforward annular voltage-controlled oscillator. A comparison voltage is output through a comparator and then is input into a voltage regulator through a filter, and a control voltage is output to realize frequency control on a feed-forward annular voltage-controlled oscillator to form a stable negative feedback system, so that the 8-phase clock generator with high-precision phase output is realized, and the phase precision of an output clock is further improved through two-stage injection locking; compared with a traditional clock generator, the requirement for a high frequency multiplication clock is avoided, the design difficulty of a system phase-locked loop is lowered, power consumption is low, the area is small, and the injection locking bandwidth is high.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chips, and in particular to a two-stage injection locked 8-phase clock generator, a clock data recovery circuit, a chip and an electronic device. Background Art

[0002] Serial-to-deserialization (SerDes) technology is widely used in the field of high-speed data transmission, such as internal connection and external communication in data centers, artificial intelligence and machine learning, high-speed optical module interfaces, high-performance computing, chip-to-chip and board-to-board interconnection, 5G communication and other application scenarios that require high-speed data transmission. The clock data recovery (CDR) module is the core component of SerDes. The CDR architecture includes a phase-locked loop structure, a phase interpolator structure, and a bangbang frequency detector single loop structure. With the continuous increase in speed, the generation of multi-phase clocks in CDR design has become an important research topic. Multi-phase clocks are widely used in half-speed and 1 / 4-speed CDR architectures. At the same time, in order to improve the quantization noise of the CDR loop and improve the linearity of the phase interpolator in the CDR based on the phase interpolator structure, a multi-phase clock is also required as the clock source for the phase interpolator.

[0003] Traditional multi-phase clock generators, such as those implemented through frequency dividers, multi-phase filters, delay phase-locked loops, and hybrid structures, have certain disadvantages. For example, multi-phase clock generation through frequency dividers requires a 4-fold high-frequency clock, which increases the difficulty of designing the phase-locked loop and the speed requirements of the process for high-speed SerDes systems; multi-phase clock generation through multi-phase filters requires a power-hungry driver buffer as the driver stage for the multi-phase filter; and multi-phase clock generation through a hybrid structure has a large area and a small bandwidth, which is not conducive to the use of SerDes broadband communication systems. Summary of the invention

[0004] In order to solve the various shortcomings of traditional multi-phase clock generators, the present invention provides a two-stage injection locked 8-phase clock generator, which can output a clock signal with low phase error while avoiding the need for a high-frequency clock, reducing power consumption and area, and having a higher injection locked bandwidth.

[0005] In a first aspect, an embodiment of the present invention provides a two-stage injection locked 8-phase clock generator, comprising: a first-stage injection strength adjustment module, a second-stage injection strength adjustment module, a feedback adjustment module, and an output AC coupling buffer; A first end of the first-stage injection strength adjustment module is connected to a positive differential clock signal, a second end of the first-stage injection strength adjustment module is connected to a reverse differential clock signal, a third end of the first-stage injection strength adjustment module is connected to a first end of the second-stage injection strength adjustment module and a first end of the feedback adjustment module, a second end of the feedback adjustment module is connected to a fourth end of the first-stage injection strength adjustment module and a third end of the second-stage injection strength adjustment module, and a fourth end of the second-stage injection strength adjustment module is connected to a first end of the output AC coupling buffer; The first-stage injection strength adjustment module is configured to adjust the injection strength to output an 8-phase clock signal, the feedback adjustment module is configured to form a negative feedback loop by detecting the 8-phase clock adjustment output voltage, and the second-stage injection strength adjustment module is configured to further adjust the phase error of the 8-phase clock signal.

[0006] Further, the first-stage injection strength adjustment module includes: a first-stage injection strength adjustment control buffer, a first voltage-controlled oscillator, and a first buffer; The first-stage injection strength adjustment control buffer includes a first control buffer and a second control buffer, wherein the first end of the first control buffer is connected to a positive differential clock signal, and the first end of the second control buffer is connected to a reverse differential clock signal; the second end of the first control buffer is connected to the first end of the first voltage-controlled oscillator, the second end of the second control buffer is connected to the second end of the first voltage-controlled oscillator, the third end of the first voltage-controlled oscillator is connected to the first end of the first buffer, and the fourth end of the first voltage-controlled oscillator is connected to the second end of the feedback adjustment module; the second end of the first buffer is connected to the first end of the second-stage injection strength adjustment module and the first end of the feedback adjustment module.

[0007] Further, the second-stage injection strength adjustment module includes: a second-stage injection strength adjustment control buffer, a second voltage-controlled oscillator and a second buffer; A first end of the second-stage injection strength adjustment control buffer is connected to a third end of the first-stage injection strength adjustment module and a first end of the feedback adjustment module, a second end of the second-stage injection strength adjustment control buffer is connected to a first end of the second voltage-controlled oscillator; a second end of the second voltage-controlled oscillator is connected to a first end of the second buffer, a third end of the second voltage-controlled oscillator is connected to a second end of the feedback adjustment module; a second end of the second buffer is connected to the output AC coupling buffer.

[0008] Further, the feedback regulation module includes: an orthogonal phase detector, a comparator, a filter and a voltage regulator; The first end of the orthogonal phase detector is connected to the third end of the first-stage injection strength adjustment module, the second end and the third end of the orthogonal phase detector are respectively connected to the first end and the second end of the comparator, the third end of the comparator is connected to the first end of the filter and the first end of the voltage regulator, the second end of the voltage regulator is connected to the fourth end of the first-stage injection strength adjustment module and the third end of the second-stage injection strength adjustment module; the filter includes a grounded capacitor.

[0009] Optionally, the voltage-controlled oscillator is a feedforward ring voltage-controlled oscillator, which includes: a main loop composed of eight-stage delay units and two sub-loops composed of four-stage delay units, and the phase difference between each stage of delay units in the main loop is 45 degrees.

[0010] Further, the feedforward ring voltage-controlled oscillator includes a first node, a second node, a third node, a fourth node, a fifth node, a sixth node, a seventh node and an eighth node; In the first voltage-controlled oscillator, the fourth node is both an output node and an injection node of the positive differential clock signal, and the eighth node is both an output node and an injection node of the reverse differential clock signal.

[0011] Further, the quadrature phase detector includes: a first AND gate, a second AND gate, a first adder, a third AND gate, a fourth AND gate and a second adder; The first end of the first AND gate is connected to the clock signal output by the first node, and the second end is connected to the clock signal output by the third node; the first end of the second AND gate is connected to the clock signal output by the fifth node, and the second end is connected to the clock signal output by the seventh node; the third end of the first AND gate is connected to the first end of the first adder, the third end of the second AND gate is connected to the second end of the first adder, and the third end of the first adder outputs a reverse detection signal; The first end of the third AND gate is connected to the clock signal output by the second node, and the second end is connected to the clock signal output by the fourth node. The first end of the fourth AND gate is connected to the clock signal output by the sixth node, and the second end is connected to the clock signal output by the eighth node. The third end of the third AND gate is connected to the first end of the second adder, the third end of the fourth AND gate is connected to the second end of the second adder, and the third end of the second adder outputs a forward detection signal.

[0012] In a second aspect, an embodiment of the present invention further provides a clock data recovery circuit, wherein the clock data recovery circuit comprises the two-stage injection locked 8-phase clock generator as described in any one of the first aspects.

[0013] In a third aspect, an embodiment of the present invention further provides a chip, wherein the chip includes the clock data recovery circuit described in the second aspect.

[0014] A fourth aspect provides an electronic device, comprising the chip described in the third aspect.

[0015] The present invention provides a two-stage injection-locked 8-phase clock generator, which constructs a simplified orthogonal phase-locked loop. A group of differential clock signals are injected into a feedforward ring voltage-controlled oscillator to output an 8-phase clock signal. The injection-locked phase relationship is determined by an orthogonal phase detector, and a comparison voltage is output by a comparator. The comparison voltage is then input into a voltage regulator through a filter, and the output control voltage controls the frequency of the feedforward ring voltage-controlled oscillator to form a stable negative feedback system. Thus, an 8-phase clock generator with high-precision phase output is realized, and the output clock phase accuracy is further improved through two-stage injection locking. Compared with traditional clock generators, the need for high-frequency clocks is avoided, the difficulty of system phase-locked loop design is reduced, the power consumption is low, the area is small, and the injection locking bandwidth is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 This is a structural diagram of a two-stage injection locked 8-phase clock generator provided by an embodiment of the present application; Figure 2 This is a structural diagram of a feedforward ring voltage-controlled oscillator of a two-stage injection-locked 8-phase clock generator provided by an embodiment of the present application; Figure 3 It is a structural diagram of an orthogonal phase detector of a two-stage injection locked 8-phase clock generator provided by an embodiment of the present application; Figure 4 It is an input-output state diagram of a quadrature phase detector of a two-stage injection locked 8-phase clock generator provided by one embodiment of the present application; Figure 5 is a structural block diagram of a clock data recovery circuit provided by an embodiment of the present application; Figure 6 This is a structural block diagram of a chip provided by an embodiment of the present application; Figure 7 It is a structural block diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0019] It should be understood that although the terms first, second, third, etc. may be used to describe the acquisition modules in the embodiments of the present invention, the acquisition modules should not be limited to these terms. These terms are only used to distinguish the acquisition modules from each other.

[0020] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0021] It should be noted that the directional words such as "upper", "lower", "left", and "right" described in the embodiments of the present invention are described at the angles shown in the drawings and should not be understood as limiting the embodiments of the present invention. In addition, in the context, it should also be understood that when it is mentioned that an element is formed "on" or "under" another element, it can not only be formed directly "on" or "under" another element, but also be formed "on" or "under" another element indirectly through an intermediate element.

[0022] refer to Figure 1 , an embodiment of the present invention provides a two-stage injection locked 8-phase clock generator 1, the clock generator 1 comprises: a first-stage injection strength adjustment module 11, a second-stage injection strength adjustment module 12, a feedback adjustment module 13 and an output AC coupling buffer 14; A first end of the first-stage injection strength adjustment module 11 is connected to the forward differential clock signal inj_ckp, a second end of the first-stage injection strength adjustment module 11 is connected to the reverse differential clock signal inj_ckn, a third end of the first-stage injection strength adjustment module 11 is connected to a first end of the second-stage injection strength adjustment module 12 and a first end of the feedback adjustment module 13, a second end of the feedback adjustment module 13 is connected to a fourth end of the first-stage injection strength adjustment module 11 and a third end of the second-stage injection strength adjustment module 12, and a fourth end of the second-stage injection strength adjustment module 12 is connected to a first end of the output AC coupling buffer 14; Among them, the first-stage injection strength adjustment module 11 is configured to adjust the injection strength to output an 8-phase clock signal, the feedback adjustment module 13 is configured to form a negative feedback loop by detecting the aforementioned 8-phase clock to adjust the output control voltage, and the second-stage injection strength adjustment module 12 is configured to further adjust the phase error of the above-mentioned 8-phase clock signal.

[0023] refer to Figure 1-3 , the structure of each component module of a two-stage injection locked 8-phase clock generator provided by an embodiment of the present invention is described.

[0024] Exemplarily, the first-stage injection intensity adjustment module 11 may include but is not limited to: a first-stage injection intensity adjustment control buffer 111 , a first voltage-controlled oscillator 112 , and a buffer 113 ; The first-stage injection intensity regulation control buffer 111 includes a control buffer 1111 and a control buffer 1112. The first end of the control buffer 1111 is connected to the forward differential clock signal inj_ckp, and the first end of the control buffer 1112 is connected to the reverse differential clock signal inj_ckn; the second end of the control buffer 1111 is connected to the first end of the first voltage-controlled oscillator 112, the second end of the control buffer 1112 is connected to the second end of the first voltage-controlled oscillator 112, the third end of the first voltage-controlled oscillator 112 is connected to the first end of the buffer 113, and the fourth end of the first voltage-controlled oscillator 112 is connected to the second end of the feedback regulation module 13; the second end of the buffer 113 is connected to the first end of the second-stage injection intensity regulation module 12 and the first end of the feedback regulation module 13.

[0025] Exemplarily, the second-stage injection strength adjustment module 12 may include, but is not limited to: a second-stage injection strength adjustment control buffer 121 , a second voltage-controlled oscillator 122 , and a buffer 123 ; The first end of the second-stage injection intensity regulation control buffer 121 is connected to the third end of the first-stage injection intensity regulation module 11 and the first end of the feedback regulation module 13, and the second end of the second-stage injection intensity regulation control buffer 121 is connected to the first end of the second voltage-controlled oscillator 122; the second end of the second voltage-controlled oscillator 122 is connected to the first end of the buffer 123, and the third end of the second voltage-controlled oscillator 122 is connected to the second end of the feedback regulation module 13; the second end of the buffer 123 is connected to the output AC coupling buffer 14.

[0026] Exemplarily, the feedback regulation module 13 may include, but is not limited to: an orthogonal phase detector 131 , a comparator 132 , a filter 133 , and a voltage regulator 134 ; The first end of the orthogonal phase detector 131 is connected to the third end of the first-stage injection intensity adjustment module 11, the second end and the third end of the orthogonal phase detector 131 are respectively connected to the first end and the second end of the comparator 132, the third end of the comparator 132 is connected to the first end of the filter 133 and the first end of the voltage regulator 134, the second end of the voltage regulator 134 is connected to the fourth end of the first-stage injection intensity adjustment module 11 and the third end of the second-stage injection intensity adjustment module 12; the filter 133 includes a grounded capacitor C1.

[0027] Preferably, in this embodiment, the first voltage-controlled oscillator 112 and the second voltage-controlled oscillator 122 are both feedforward ring voltage-controlled oscillators, see Figure 2 In this embodiment, the feedforward ring voltage-controlled oscillator includes: a main loop composed of eight-stage delay units D0-D7 and two sub-loops composed of four-stage delay units d0-d3 and d4-d7. The phase difference between each stage of the delay unit in the main loop is 45 degrees.

[0028] In this embodiment, the feedforward ring voltage-controlled oscillator also includes nodes ck0, ck1, ck2, ck3, ck4, ck5, ck6 and ck7; wherein the node ck3 of the first voltage-controlled oscillator 112 is the output node of the first voltage-controlled oscillator 112, and is also the injection node of the forward differential clock signal inj_ckp, and the node ck7 of the first voltage-controlled oscillator 112 is the output node of the first voltage-controlled oscillator 112, and is also the injection node of the reverse differential clock signal inj_ckn.

[0029] See also Figure 3 , further describing the structure of the quadrature phase detector 131, the quadrature phase detector 131 includes but is not limited to: AND gate A1, AND gate A2, adder SUM1, AND gate A3, AND gate A4 and adder SUM2; The first end of the AND gate A1 is connected to the clock signal output by the node ck0, the second end is connected to the clock signal output by the node ck2, the first end of the AND gate A2 is connected to the clock signal output by the node ck4, the second end is connected to the clock signal output by the node ck6, the third end of the AND gate A1 is connected to the first end of the adder SUM1, the third end of the AND gate A2 is connected to the second end of the adder SUM1, and the third end of the adder SUM1 outputs the reverse detection signal pdet_n; The first end of the AND gate A3 is connected to the clock signal output by the node ck1, and the second end is connected to the clock signal output by the node ck3. The first end of the AND gate A4 is connected to the clock signal output by the node ck5, and the second end is connected to the clock signal output by the node ck7. The third end of the AND gate A3 is connected to the first end of the adder SUM2, and the third end of the AND gate A4 is connected to the second end of the adder SUM2. The third end of the adder SUM2 outputs the forward detection signal pdet_p.

[0030] See also Figure 4 From the input-output state diagram of the orthogonal phase detector, it can be seen that the output signals of the clock signals of node ck0 and node ck2 are output after the logic multiplication operation of the clock signals through the AND gate A1, and the output signals of the clock signals of node ck4 and node ck6 are output after the logic multiplication operation of the clock signals through the AND gate A2, and the two are output through the adder SUM1 to output the reverse detection signal pdet_n; the output signals of the clock signals of node ck1 and node ck3 are output after the logic multiplication operation of the clock signals through the AND gate A3, and the output signals of the clock signals of node ck5 and node ck7 are output after the logic multiplication operation of the clock signals through the AND gate A4, and the two are output through the adder SUM2 to output the forward detection signal pdet_p.

[0031] refer to Figure 1-4 , the working principle of this embodiment is described. In this embodiment, a set of differential clock signals inj_ckp and inj_ckn are input to the first voltage-controlled oscillator 112. The injection strength can be adjusted according to the situation of the injected clock through the first-stage injection strength adjustment control buffer 111; the first voltage-controlled oscillator 112 outputs an 8-phase clock signal under the control of the initial control voltage Vctrl, and the orthogonal phase detector 131 detects the phase relationship of the input 8-phase clock signal, see Figure 4It can be seen that when the phase of the reverse differential clock signal inj_ckn is advanced after the forward differential clock signal inj_ckp is injected, the pulse width of the forward detection signal pdet_p is greater than the reverse detection signal pdet_n. When the phase of the reverse differential clock signal inj_ckn is delayed after the forward differential clock signal inj_ckp is injected, the pulse width of the forward detection signal pdet_p is smaller than the reverse detection signal pdet_n. Therefore, according to the pulse width of the detection signals pdet_p and pdet_n output by the orthogonal phase detector 131, a control signal of the voltage regulator 134 is generated after passing through the comparator 132 and the filter 133. The voltage regulator 134 adjusts the output control voltage Vctrl to the first voltage-controlled oscillator 112 according to the input control signal, forming a negative feedback loop. When the phase of the reverse differential clock signal inj_ckn is advanced after the positive differential clock signal inj_ckp is injected, the output control voltage Vctrl of the voltage regulator 134 increases, and the frequency of the first voltage-controlled oscillator 112 increases until the phase difference between the injected differential clock signals inj_ckp and inj_ckn and the phase difference between the previous and next clocks is 45 degrees; when the phase of the reverse differential clock signal inj_ckn is delayed after the positive differential clock signal inj_ckp is injected, the output control voltage Vctrl of the voltage regulator 134 decreases, and the frequency of the first voltage-controlled oscillator 112 decreases until the phase difference between the injected differential clock signals inj_ckp and inj_ckn and the phase difference between the previous and next clocks is 45 degrees, and finally a stable orthogonal phase-locked closed loop is formed; after the 8-phase clock is orthogonally phase-locked, the second voltage-controlled oscillator 122 with the same structure as the first voltage-controlled oscillator 112 is injected through the second-stage injection intensity adjustment control buffer 121, and then output through the output AC coupling buffer 14, so as to further reduce the phase error of the 8-phase clock.

[0032] The present invention provides a two-stage injection locked 8-phase clock generator, which constructs a streamlined orthogonal phase locked loop, determines the injection locked phase relationship to form a stable negative feedback system, realizes an 8-phase clock generator with high-precision phase output, and further improves the output clock phase accuracy through two-stage injection locking. Compared with traditional clock generators, it avoids the need for high-frequency clocks, reduces the difficulty of system phase-locked loop design, has low power consumption, small area, and high injection locked bandwidth.

[0033] This embodiment also provides a clock data recovery circuit 2, such as Figure 5 As shown, the clock data recovery circuit 2 includes but is not limited to Figure 1 The two-stage injection locked 8-phase clock generator 1 in the corresponding embodiment.

[0034] This embodiment also provides a chip 3, such as Figure 6 As shown, the chip 3 includes but is not limited to Figure 5Corresponding to the clock data recovery circuit 2 in the embodiment.

[0035] This embodiment also provides an electronic device 4, such as Figure 7 As shown, the electronic device 4 includes but is not limited to Figure 6 Corresponding to chip 3 in the embodiment.

[0036] The above description is only a preferred embodiment of the present invention. Those skilled in the art should understand that the scope of disclosure involved in the present invention is not limited to the technical solution formed by a specific combination of the above technical features, but also should cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present invention (but not limited to) to form a technical solution.

Claims

1. A two-stage injection locked 8-phase clock generator, characterized in that: The clock generator comprises: a first-stage injection strength adjustment module, a second-stage injection strength adjustment module, a feedback adjustment module and an output AC coupling buffer; A first end of the first-stage injection strength adjustment module is connected to a positive differential clock signal, a second end of the first-stage injection strength adjustment module is connected to a reverse differential clock signal, a third end of the first-stage injection strength adjustment module is connected to a first end of the second-stage injection strength adjustment module and a first end of the feedback adjustment module, a second end of the feedback adjustment module is connected to a fourth end of the first-stage injection strength adjustment module and a third end of the second-stage injection strength adjustment module, and a fourth end of the second-stage injection strength adjustment module is connected to a first end of the output AC coupling buffer; The first-stage injection strength adjustment module is configured to adjust the injection strength to output an 8-phase clock signal, the feedback adjustment module is configured to form a negative feedback loop by detecting the 8-phase clock adjustment output voltage, and the second-stage injection strength adjustment module is configured to further adjust the phase error of the 8-phase clock signal.

2. A two-stage injection locked 8-phase clock generator according to claim 1, characterized in that: The first-stage injection intensity adjustment module includes: a first-stage injection intensity adjustment control buffer, a first voltage-controlled oscillator, and a first buffer; The first-stage injection strength adjustment control buffer includes a first control buffer and a second control buffer, wherein the first end of the first control buffer is connected to a positive differential clock signal, and the first end of the second control buffer is connected to a reverse differential clock signal; the second end of the first control buffer is connected to the first end of the first voltage-controlled oscillator, the second end of the second control buffer is connected to the second end of the first voltage-controlled oscillator, the third end of the first voltage-controlled oscillator is connected to the first end of the first buffer, and the fourth end of the first voltage-controlled oscillator is connected to the second end of the feedback adjustment module; the second end of the first buffer is connected to the first end of the second-stage injection strength adjustment module and the first end of the feedback adjustment module.

3. A two-stage injection locked 8-phase clock generator according to claim 2, characterized in that: The second-stage injection strength adjustment module comprises: a second-stage injection strength adjustment control buffer, a second voltage-controlled oscillator and a second buffer; A first end of the second-stage injection strength adjustment control buffer is connected to a third end of the first-stage injection strength adjustment module and a first end of the feedback adjustment module, a second end of the second-stage injection strength adjustment control buffer is connected to a first end of the second voltage-controlled oscillator; a second end of the second voltage-controlled oscillator is connected to a first end of the second buffer, a third end of the second voltage-controlled oscillator is connected to a second end of the feedback adjustment module; a second end of the second buffer is connected to the output AC coupling buffer.

4. A two-stage injection locked 8-phase clock generator according to claim 3, characterized in that: The feedback regulation module includes: an orthogonal phase detector, a comparator, a filter and a voltage regulator; The first end of the orthogonal phase detector is connected to the third end of the first-stage injection strength adjustment module, the second end and the third end of the orthogonal phase detector are respectively connected to the first end and the second end of the comparator, the third end of the comparator is connected to the first end of the filter and the first end of the voltage regulator, the second end of the voltage regulator is connected to the fourth end of the first-stage injection strength adjustment module and the third end of the second-stage injection strength adjustment module; the filter includes a grounded capacitor.

5. A two-stage injection locked 8-phase clock generator according to claim 4, characterized in that: The first voltage-controlled oscillator and the second voltage-controlled oscillator are both feedforward ring voltage-controlled oscillators, and the feedforward ring voltage-controlled oscillator includes: a main loop composed of eight-stage delay units and two sub-loops composed of four-stage delay units, and the phase difference between each stage of delay units in the main loop is 45 degrees.

6. A two-stage injection locked 8-phase clock generator according to claim 5, characterized in that: The feedforward ring voltage controlled oscillator comprises a first node, a second node, a third node, a fourth node, a fifth node, a sixth node, a seventh node and an eighth node; In the first voltage-controlled oscillator, the fourth node is both an output node and an injection node of the positive differential clock signal, and the eighth node is both an output node and an injection node of the reverse differential clock signal.

7. A two-stage injection locked 8-phase clock generator according to claim 6, characterized in that: The quadrature phase detector comprises: a first AND gate, a second AND gate, a first adder, a third AND gate, a fourth AND gate and a second adder; The first end of the first AND gate is connected to the clock signal output by the first node, and the second end is connected to the clock signal output by the third node; the first end of the second AND gate is connected to the clock signal output by the fifth node, and the second end is connected to the clock signal output by the seventh node; the third end of the first AND gate is connected to the first end of the first adder, the third end of the second AND gate is connected to the second end of the first adder, and the third end of the first adder outputs a reverse detection signal; The first end of the third AND gate is connected to the clock signal output by the second node, and the second end is connected to the clock signal output by the fourth node. The first end of the fourth AND gate is connected to the clock signal output by the sixth node, and the second end is connected to the clock signal output by the eighth node. The third end of the third AND gate is connected to the first end of the second adder, the third end of the fourth AND gate is connected to the second end of the second adder, and the third end of the second adder outputs a forward detection signal.

8. A clock data recovery circuit, characterized in that: The clock data recovery circuit comprises the two-stage injection locked 8-phase clock generator as claimed in any one of claims 1 to 7.

9. A chip, characterized in that: The chip comprises the clock data recovery circuit according to claim 8.

10. An electronic device, characterized in that: The electronic device comprises the chip according to claim 9.

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