Via hole wiring impedance optimization method and printed circuit board

Abstract

The invention relates to a via hole wiring impedance optimization method and a printed circuit board, through hole optimization and wiring optimization can be separated in a certain form, and optimization to the impedance matching target is facilitated. The via hole wiring impedance optimization method comprises the following steps: performing parameter design and preliminary hollowing treatment on a via hole in a printed circuit board to obtain a via hole wiring initial structure; based on the impedance simulation result of the via hole wiring initial structure, thickening the part, which is located in the hollowed-out area and is spaced from the hole wall of the via hole, on the wiring in the via hole wiring initial structure to obtain a via hole wiring middle structure; performing simulation analysis on the via hole routing intermediate structure, and performing via hole optimization on the via hole routing intermediate structure to obtain a via hole routing optimization structure; and performing simulation analysis on the through hole wiring optimization structure, and adjusting the size of the thickened part of the through hole wiring in the through hole wiring optimization structure and / or the distance between the thickened part and the hole wall of the through hole so as to obtain a through hole wiring final structure.

Description

Technical Field

[0001] The present application relates to the technical field of circuit boards, and in particular to a via-hole routing impedance optimization method and a printed circuit board. Background Art

[0002] With the rapid development of information and communication technology, the network era has put forward higher requirements for information transmission, and the signal rate is getting higher and higher. The emergence of some more advanced signal transmission technologies such as PAM4 (English: 4-Level Pulse Amplitude Modulation; Chinese: Four-Level Pulse Amplitude Modulation) signals not only improves the signal transmission efficiency, but also reduces the transmission loss. Although more designs are turning to high-speed serial links with ps-level edge rates, any impedance discontinuity in the signal channel will have an adverse effect on signal quality. Since a common and overlooked source of routing channel discontinuity is the signal via, and the via increases jitter and reduces the opening of the eye diagram, which may cause the receiver to erroneously interpret the data, optimizing the via impedance is critical for high-speed signals.

[0003] At present, when the signal propagates through the via, the impedance value may fluctuate greatly due to the surrounding environment and the via itself (i.e., impedance mutation), so the via is generally hollowed out, thickened, and other treatments are performed to slow down the impedance mutation. Although under the condition that the via diameter, via pitch, via stub, and hollowing size remain unchanged, the high point of the impedance curve is usually caused by the trace that is not thickened in the hollowing area, so thickening the line width can effectively reduce the high point of the impedance curve; however, due to the fast transmission of high-speed signals, the effect of thickening the line width to reduce the impedance value of the trace will quickly act directly on the via, resulting in the high and low points of the impedance curve being pulled down at the same time. At this time, if the low point of the impedance curve is too low, it is necessary to raise the low point, and it is impossible to take into account the optimization effect of the high and low points of the impedance curve; that is, for signals with too high speed, the impedance fluctuation range is strict, and it is difficult to optimize the via impedance with conventional impedance optimization methods, or under certain restrictions, it is impossible to optimize to the impedance matching goal. Summary of the invention

[0004] In view of the problem that thickening the line width in conventional impedance optimization methods will lower the high point of the impedance curve while further lowering the low point of the impedance curve, making it difficult to optimize to the impedance matching target; the present application provides a via routing impedance optimization method and a printed circuit board, which can separate via optimization and routing optimization in a certain form, so that the high point and the low point of the via impedance will not deviate too much from the target impedance amplitude, which is conducive to optimizing to the impedance matching target.

[0005] In order to achieve at least one of the above advantages or other advantages and purposes of the present application, the present application provides a via routing impedance optimization method, comprising:

[0006] Perform parameter design and preliminary hollowing processing on the vias on the printed circuit board to obtain the initial via routing structure of the printed circuit board;

[0007] Based on the impedance simulation result of the initial structure of the via routing, thicken the portion of the routing in the initial structure of the via routing that is located within the hollowed-out area and spaced from the via hole wall to obtain an intermediate structure of the via routing;

[0008] By performing simulation analysis on the intermediate structure of the via routing, the intermediate structure of the via routing is optimized to obtain an optimized via routing structure; and

[0009] By performing simulation analysis on the optimized via routing structure, the size of the thickened portion of the via routing in the optimized via routing structure and / or the distance between the thickened portion and the via hole wall are adjusted to obtain the final via routing structure.

[0010] In one embodiment of the present application, in the step of thickening the portion of the via routing in the initial structure of the via routing that is located within the hollowed-out area and spaced from the via hole wall based on the impedance simulation result of the initial structure of the via routing to obtain the intermediate structure of the via routing:

[0011] A metal sheet is added within the hollowed-out area to a portion of the via trace that is spaced apart from the via hole wall, and a gap is formed between the metal sheet and the via hole wall.

[0012] In one embodiment of the present application, the metal sheet is a copper sheet having the same material properties as the via wiring.

[0013] In one embodiment of the present application, the metal sheet is selected from one of a circular copper sheet, a diamond copper sheet, a triangular copper sheet and a rectangular copper sheet.

[0014] In one embodiment of the present application, the step of optimizing the via routing intermediate structure by simulation analysis to obtain the via routing optimized structure includes the steps of:

[0015] By performing impedance simulation on the intermediate structure of the via trace, analyzing the difference between the low point of the impedance curve and the target impedance value; and

[0016] In response to the difference between the target impedance value and the low point impedance value being greater than a preset difference threshold, the via parameters are adjusted to raise the low point of the impedance curve so that the difference between the target impedance value and the low point impedance value is less than or equal to the preset difference threshold.

[0017] In one embodiment of the present application, the step of adjusting the size of the thickened portion of the via routing in the via routing optimization structure and / or the distance between the thickened portion and the via hole wall by performing simulation analysis on the via routing optimization structure to obtain the final structure of the via routing includes the steps of:

[0018] By performing impedance simulation on the optimized via routing structure, it is analyzed whether the high point of the impedance curve falls within the target impedance tolerance range;

[0019] In response to the high point impedance value being greater than the upper limit of the target impedance tolerance range, increasing the size of the thickened portion on the via trace, and / or decreasing the distance between the thickened portion on the via trace and the via hole wall, so as to lower the high point of the impedance curve, so that both the high point and the low point of the impedance curve fall within the target impedance tolerance range; and

[0020] In response to the high point impedance value being less than the lower limit of the target impedance tolerance range, the size of the thickened portion on the via trace is reduced, and / or the distance between the thickened portion on the via trace and the via hole wall is increased to raise the high point of the impedance curve so that both the high point and the low point of the impedance curve fall within the target impedance tolerance range.

[0021] According to another aspect of the present application, the present application further provides a printed circuit board, wherein the printed circuit board includes a via wiring structure optimized by any of the via wiring impedance optimization methods described above.

[0022] According to another aspect of the present application, the present application further provides a printed circuit board, comprising:

[0023] a circuit board; and

[0024] A via routing structure, wherein the via routing structure is arranged on the circuit substrate, and the via routing structure includes a pair of reference layers having a hollowed-out area and differential routing, a pair of vias arranged at intervals within the hollowed-out area, and two pairs of via routings extending from two of the vias to two of the reference layers to correspondingly connect the differential routings; wherein the via routing has a thickened routing segment located within the hollowed-out area and a reserved routing segment extending from the thickened routing segment to the via, and the line width of the thickened routing segment is greater than the line width of the reserved routing segment.

[0025] In one embodiment of the present application, the thickened routing segment is a circular copper sheet that can be electrically superimposed on the via routing.

[0026] In one embodiment of the present application, the via routing further has a transition routing segment, and the transition routing segment correspondingly extends from the thickened routing segment to the differential routing.

[0027] In summary, the via routing impedance optimization method of the present application is to thicken the portion of the routing that is located within the hollowed-out area and spaced from the via hole wall, so that a certain space is reserved between the thickened portion of the via routing and the via hole wall, that is, the thickened portion of the via routing does not directly contact the via hole wall, so that the trend of lowering the routing impedance value of the thickened portion of the via routing will not immediately affect the via impedance, so as to separate the optimization trend of the via impedance from the optimization trend of the routing impedance to a certain extent, and ensure that the high and low points of the impedance curve do not deviate too much from the target impedance amplitude, which is conducive to the effect of jointly optimizing the impedance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of a flow chart of a via routing impedance optimization method according to an embodiment of the present application;

[0029] Figure 2 A schematic flow chart of a via optimization step in the via routing impedance optimization method according to the above embodiment of the present application is shown;

[0030] Figure 3 A schematic flow chart of the routing optimization step in the via routing impedance optimization method according to the above embodiment of the present application is shown;

[0031] Figure 4 is a schematic structural diagram of a printed circuit board according to Example 1 of the present application;

[0032] Figure 5A is a schematic structural diagram of a printed circuit board according to comparative example 1 of the present application;

[0033] Figure 5B is a schematic structural diagram of a printed circuit board according to comparative example 1 of the present application;

[0034] Figure 6 A schematic diagram of impedance curves obtained by impedance simulation of the printed circuit boards of the above example 1, comparative example 1 and comparative example 2 is shown.

[0035] Description of main component symbols:

[0036] 1. Via routing structure; 10. Reference layer; 101. Hollow area; 102. Differential routing; 20. Via; 30. Via routing; 31. Bold routing segment; 32. Reserved routing segment; 33. Transition routing segment.

[0037] The above description of the main component symbols is combined with the accompanying drawings and specific implementation methods to further illustrate the present application in detail. DETAILED DESCRIPTION

[0038] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0039] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0040] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0041] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0042] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0043] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only implementation method.

[0044] Considering that in order to reduce the impact of the via routing impedance deviating from the target impedance value due to the high impedance value of the via routing in the hollowed-out area, the conventional impedance optimization method usually thickens the routing connected to the via hole wall as a whole in the hollowed-out area, so that the routing impedance itself (i.e., the high point of the impedance curve) shows a trend of decreasing and lowering; however, for signals with a higher propagation rate, the thickened routing connected to the via hole wall will quickly directly affect the effect of lowering the impedance on the via, causing the via impedance itself (i.e., the low point of the impedance curve) to be further lowered, and it is impossible to take into account the optimization effect of the high and low points of the impedance curve. In other words, for signals with too high speed, the impedance fluctuation range is required to be strict, and it is difficult for conventional impedance optimization methods to optimize the via impedance, or under certain restrictions, it is impossible to optimize to the impedance matching target. Therefore, the present application creatively provides a via routing impedance optimization method and a printed circuit board, which can separate the via optimization and routing optimization in a certain form, so that the high and low points of the via impedance do not deviate too much from the target impedance amplitude, which is conducive to optimizing to the impedance matching target.

[0045] Specifically, according to another aspect of the present application, Figure 1 As shown, an embodiment of the present application provides a method for optimizing via trace impedance, which may include the steps of:

[0046] S101: performing parameter design and preliminary hollowing processing on vias on a printed circuit board to obtain an initial via routing structure of the printed circuit board;

[0047] S200: based on the impedance simulation result of the initial structure of the via routing, thicken the portion of the routing in the initial structure of the via routing that is located within the hollowed-out area and spaced from the via hole wall, so as to obtain an intermediate structure of the via routing;

[0048] S300: Optimizing the vias in the middle structure of the vias by performing simulation analysis on the middle structure of the vias, so as to obtain an optimized via structure; and

[0049] S400: By performing simulation analysis on the via routing optimization structure, the size of the thickened portion of the routing in the via routing optimization structure and / or the distance between the thickened portion and the via hole wall are adjusted to obtain a final via routing structure.

[0050] More specifically, the initial via routing structure of the printed circuit board may include, but is not limited to, a pair of reference layers having a hollowed-out area and differential routing, a pair of vias spaced apart in the hollowed-out area, and two pairs of via routings extending from the two vias to the two reference layers to be correspondingly connected to the differential routing. Thus, in the above step S101 of the present application, the parameters of the vias include the via diameter, the via spacing, and the distance between the vias and the copper foil of the reference layer (i.e., the size of the hollowed-out area).

[0051] It is worth noting that, through the impedance simulation analysis of the initial structure of the via routing, it can be known that the high point of the impedance curve is usually caused by the routing that is not thickened in the hollowed-out area, and the low point of the impedance curve is presented by the via's own attribute factors. If the routing line width located in the hollowed-out area is thickened as a whole according to the conventional impedance optimization method, the high and low points of the impedance curve will be greatly lowered at the same time, making it difficult to optimize to the impedance matching target. However, the via routing impedance optimization method of the present application is to thicken the part of the routing that is located in the hollowed-out area and separated from the via hole wall, so that a certain space is reserved between the thickened part of the via routing and the via hole wall, that is, the thickened part of the via routing does not directly contact the via hole wall, so that the trend of lowering the routing impedance value of the thickened part of the via routing will not immediately act on the via impedance, so as to separate the optimization trend of the via impedance from the optimization trend of the routing impedance to a certain extent, and ensure that the high and low points of the impedance curve do not deviate too much from the target impedance amplitude, which is conducive to the effect of jointly optimizing the impedance.

[0052] Exemplarily, in step S200 of the via routing impedance optimization method of the present application: a metal sheet is added to the portion of the via routing spaced apart from the via hole wall within the hollowed-out area, and a gap is formed between the metal sheet and the via hole wall to partially thicken the routing line width. It is understandable that the via routing impedance optimization method of the present application can ensure that the routing segment between the metal sheet and the via hole wall is not thickened while partially thickening the routing line width by adding a metal sheet spaced apart from the via hole wall, thereby preventing the low point of the impedance curve from being pulled too low.

[0053] Optionally, the metal sheet is implemented as a copper sheet having the same material properties as the via trace.

[0054] Optionally, the metal sheet is implemented as a circular copper sheet. It is understandable that in other examples of the present application, the metal sheet can also be implemented as a copper sheet having other shapes such as a diamond, a triangle or a rectangle, as long as the line width of the via routing can be partially thickened, and the present application will not repeat this.

[0055] According to the above embodiments of the present application, Figure 2 As shown, step S300 of the via routing impedance optimization method may include the following steps:

[0056] S310: Analyze the difference between the low point of the impedance curve and the target impedance value by performing impedance simulation on the intermediate structure of the via routing; and

[0057] S320: In response to the difference between the target impedance value and the low point impedance value being greater than a preset difference threshold, adjusting the via parameters to raise the low point of the impedance curve so that the difference between the target impedance value and the low point impedance value is less than or equal to the preset difference threshold.

[0058] It can be understood that in the above step S320 of the present application, the low point of the impedance curve can be raised by increasing the size of the hollowed-out area, reducing the via diameter or reducing the via spacing, so that the low point impedance value is close to the target impedance value without deviating too far from the target impedance value.

[0059] Furthermore, if Figure 3 As shown, step S400 of the via trace impedance optimization method of the present application may include the following steps:

[0060] S410: Performing impedance simulation on the optimized via routing structure to analyze whether the high point of the impedance curve falls within the target impedance tolerance range;

[0061] S420: In response to the high point impedance value being greater than the upper limit of the target impedance tolerance range, enlarging the size of the thickened portion on the via trace and / or reducing the distance between the thickened portion on the via trace and the via hole wall, so as to lower the high point of the impedance curve, so that both the high point and the low point of the impedance curve fall within the target impedance tolerance range; and

[0062] S430: In response to the high point impedance value being less than the lower limit of the target impedance tolerance range, reducing the size of the thickened portion on the via trace, and / or increasing the distance between the thickened portion on the via trace and the via hole wall, so as to raise the high point of the impedance curve, so that both the high point and the low point of the impedance curve fall within the target impedance tolerance range.

[0063] In this way, the via routing impedance optimization method of the present application first performs step 200 to partially thicken the routing line width without thickening the routing segment between the thickened portion and the via hole wall, so that the via optimization and routing optimization can be separated to a certain extent, and then performs step 300 to perform via optimization separately, so that the low point of the impedance curve is near the target impedance value, and finally performs step S400 to perform routing optimization separately, so that the high point and the low point of the impedance curve are within the target impedance tolerance range, which greatly reduces the difficulty of impedance matching.

[0064] It is worth mentioning that according to another aspect of the present application, another embodiment of the present application further provides a printed circuit board, which may include a via routing structure optimized by the above-mentioned via routing impedance optimization method.

[0065] Some specific but non-restrictive examples of the embodiments of the present application are described in more detail below with reference to the accompanying drawings. It is to be understood that the following example 1 is applicable to the above-mentioned embodiments of the present application. In addition, in order to reflect the advantages of the printed circuit board of the present application, the present application simulates and verifies the printed circuit board of this example 1 with the printed circuit boards of comparative examples 1 and 2.

[0066] Specifically, Example 1: Figure 4 As shown, the printed circuit board may include a circuit substrate and a via routing structure 1 disposed on the circuit substrate; the via routing structure 1 includes a pair of reference layers 10 having a hollow region 101 and a differential routing 102, a pair of vias 20 disposed at intervals in the hollow region 101, and two pairs of via routings 30 extending from two vias 20 to two reference layers 10 to correspondingly connect the differential routings. In particular, each via routing 30 has a thickened routing segment 31 located in the hollow region 101 and a reserved routing segment 32 extending from the thickened routing segment 31 to the via 20, the line width of the thickened routing segment 31 being greater than the line width of the reserved routing segment 32, so that a gap is reserved between the thickened portion on the via routing 30 and the hole wall of the via 20, which is conducive to reducing the difficulty of impedance optimization and facilitating optimization to the goal of impedance matching. It is understandable that the line width of the reserved routing segment 32 mentioned in the present application can be equal to the line width of the differential routing 102 in the reference layer 10. In addition, in other examples of the present application, the via routing structure 1 can also have only a portion of the via routing 30 having both the thickened routing segment 31 and the reserved routing segment 32, which will not be described in detail in the present application.

[0067] Optionally, the thickened routing segment 31 is implemented as a circular copper sheet electrically superimposed on the via routing 30. It is understandable that in other examples of the present application, the thickened routing segment can also be implemented as a circular copper sheet integrally connected to the reserved routing segment 32.

[0068] Alternatively, if Figure 4 As shown, the via routing 30 also has a transition routing segment 33, wherein the transition routing segment 33 extends from the thickened routing segment 31 to the differential routing 102 correspondingly, so as to electrically connect the thickened routing segment 31 with the differential routing 102 located in the reference layer 10 through the transition routing segment 33, and ensure that the thickened routing segment 31 is completely located in the hollowed-out area 101. It can be understood that in other examples of the present application, the via routing 30 may also not have the transition routing segment 33, and the thickened routing segment 31 directly extends into the reference layer 10 to connect the differential routing 102, and it is only necessary to ensure that the thickened routing segment 31 is partially located in the hollowed-out area 101, and this application will not elaborate on this.

[0069] Comparative Example 1: Figure 5A As shown, compared with the above-mentioned Example 1 of the present application, the difference of the printed circuit board of the comparative example 1 is that the routing line located in the hollowed-out area 101 is not thickened. In other words, the via routing line in the comparative example 1 only has the reserved routing line segment 32, but does not have the thickened routing line segment 31.

[0070] Comparative Example 2: Figure 5B As shown, compared with the above-mentioned Example 1 of the present application, the difference of the printed circuit board of the comparative example 2 is that the routing line located in the hollowed-out area 101 is thickened in a teardrop manner. In other words, the via routing line in the comparative example 2 only has the thickened routing line segment 31, but does not have the reserved routing line segment 32, and the thickened routing line segment 31 is a teardrop-shaped copper sheet that is in direct contact with the hole wall of the via hole 20.

[0071] Then, by performing impedance simulation on the printed circuit boards of Example 1, Comparative Example 1 and Comparative Example 2, the impedance is read to obtain Figure 6 The impedance curve shown is Figure 6 The yellow line in the figure is the impedance curve of comparative example 1. Figure 6 The blue line in the figure is the impedance curve of comparative example 2. Figure 6 The cyan line in the figure is the impedance curve of Example 1. Figure 6From the analysis of the impedance curve shown, it can be seen that: for the printed circuit board in comparative example 1, which does not thicken the routing in the hollowed-out area (i.e., via routing), the impedance of the routing itself will increase due to the change in the routing reference layer, resulting in an overall higher impedance curve, and much higher than the target impedance value; for comparative example 2, which thickens the routing in the hollowed-out area in a teardrop manner, although it can effectively reduce the high point of the impedance curve, it will also pull the low point of the impedance curve down a lot, resulting in the high and low points of the impedance curve being difficult to be within the target impedance tolerance range at the same time; and for example 1 of the present application, which thickens the part of the via routing that is spaced apart from the via, not only will the high point of the impedance curve not be raised too high, but also the low point of the impedance curve will not be pulled down too much, which takes into account the high and low points of the impedance curve, making the impedance curve closer to the target impedance value and meeting the high requirements of high-speed signals for impedance matching.

[0072] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A via routing impedance optimization method, characterized in that: Includes steps: Perform parameter design and preliminary hollowing processing on the vias on the printed circuit board to obtain the initial via routing structure of the printed circuit board; Based on the impedance simulation result of the initial structure of the via routing, thicken the portion of the routing in the initial structure of the via routing that is located within the hollowed-out area and spaced from the via hole wall to obtain an intermediate structure of the via routing; By performing simulation analysis on the intermediate structure of the via routing, the via routing intermediate structure is optimized to obtain an optimized via routing structure; as well as By performing simulation analysis on the optimized via routing structure, the size of the thickened portion of the via routing in the optimized via routing structure and / or the distance between the thickened portion and the via hole wall are adjusted to obtain the final via routing structure.

2. The via routing impedance optimization method according to claim 1, characterized in that: In the step of thickening the portion of the via routing in the initial structure of the via routing that is located within the hollowed-out area and spaced from the via hole wall based on the impedance simulation result of the initial structure of the via routing to obtain the intermediate structure of the via routing: A metal sheet is added within the hollowed-out area to a portion of the via trace that is spaced apart from the via hole wall, and a gap is formed between the metal sheet and the via hole wall.

3. The via routing impedance optimization method according to claim 2, characterized in that: The metal sheet is a copper sheet having the same material properties as the via wiring.

4. The via routing impedance optimization method according to claim 3, characterized in that: The metal sheet is selected from one of a circular copper sheet, a diamond copper sheet, a triangular copper sheet and a rectangular copper sheet.

5. The via routing impedance optimization method according to any one of claims 1 to 4, characterized in that: The step of performing simulation analysis on the intermediate structure of the via routing and optimizing the intermediate structure of the via routing to obtain the optimized structure of the via routing comprises the following steps: By performing impedance simulation on the intermediate structure of the via routing, the difference between the low point of the impedance curve and the target impedance value is analyzed; and In response to the difference between the target impedance value and the low point impedance value being greater than a preset difference threshold, the via parameters are adjusted to raise the low point of the impedance curve so that the difference between the target impedance value and the low point impedance value is less than or equal to the preset difference threshold.

6. The via routing impedance optimization method according to any one of claims 1 to 4, characterized in that: The step of adjusting the size of the thickened portion of the via routing in the via routing optimization structure and / or the distance between the thickened portion and the via hole wall to obtain the final structure of the via routing by simulation analysis of the via routing optimization structure comprises the steps of: By performing impedance simulation on the optimized via routing structure, it is analyzed whether the high point of the impedance curve falls within the target impedance tolerance range; In response to the high point impedance value being greater than the upper limit of the target impedance tolerance range, increasing the size of the thickened portion on the via trace, and / or decreasing the distance between the thickened portion on the via trace and the via hole wall, so as to lower the high point of the impedance curve, so that both the high point and the low point of the impedance curve fall within the target impedance tolerance range; and In response to the high point impedance value being less than the lower limit of the target impedance tolerance range, the size of the thickened portion on the via trace is reduced, and / or the distance between the thickened portion on the via trace and the via hole wall is increased to raise the high point of the impedance curve so that both the high point and the low point of the impedance curve fall within the target impedance tolerance range.

7. A printed circuit board, characterized in that The printed circuit board includes a via-line structure optimized by the via-line impedance optimization method as claimed in any one of claims 1 to 6.

8. A printed circuit board, characterized in that include: Circuit board; and A via routing structure, wherein the via routing structure is disposed on the circuit substrate, and the via routing structure comprises a pair of reference layers having a hollowed-out area and differential routing, a pair of vias disposed at intervals within the hollowed-out area, and two pairs of via routings extending from the two vias to the two reference layers to correspondingly connect the differential routings; The via routing line comprises a thickened routing line segment located in the hollowed-out area and a reserved routing line segment extending from the thickened routing line segment to the via hole, and the line width of the thickened routing line segment is greater than the line width of the reserved routing line segment.

9. The printed circuit board according to claim 8, characterized in that: The thickened wiring segment is a circular copper sheet that can be electrically superimposed on the via wiring.

10. The printed circuit board according to claim 8 or 9, characterized in that: The via routing also has a transition routing segment, and the transition routing segment correspondingly extends from the thickened routing segment to the differential routing.

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