Method for reducing photoresist stripping defects
By setting a specific arrangement of test patterns in the test mask, the complement value is obtained to form a correction mask, the problem of photoresist peeling defects is solved, the R&D cost and time is reduced, and the efficiency of semiconductor manufacturing is improved.
Patent Information
- Application Number
- CN202510171859.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-17
- Publication Date
- 2025-05-13
AI Technical Summary
In the prior art, the photoresist peeling defects lead to device failure during semiconductor manufacturing, and the republishing of the photomask increases R&D costs and delays R&D progress.
By setting multiple test patterns parallel to each other and spaced apart in the test mask, the line width is larger than the standard pattern, and the test spacing gradually increases. The pattern is transferred to the wafer by using a photolithography process to obtain the complement value to form a correction mask and reduce the photoresist peeling defect.
There is no need to publish multiple test masks repeatedly, and directly reduce photoresist peeling defects from the source, save semiconductor R&D time and funds, and improve R&D efficiency.
Smart Images
Figure CN119987152A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to a method for reducing photoresist stripping defects. Background Art
[0002] The stripping of photoresist during the ion implantation process is a common defect in the semiconductor manufacturing process. Its existence will cause ions to be injected into areas where ions should not be injected. When the stripped photoresist falls to the area not covered by the photoresist, the area where ions should be injected will be blocked and cannot be injected normally, causing device failure and seriously affecting the manufacturing yield of semiconductor products.
[0003] To deal with such defects, the current main method is to re-issue the mask and widen the layout of the defective area through the OPC (Optical Proximity Correction) method. However, re-issuing the mask not only greatly increases the R&D cost, but also seriously delays the R&D progress.
[0004] Therefore, how to reduce photoresist stripping defects while reducing semiconductor R&D costs, thereby improving the manufacturing yield and manufacturing efficiency of semiconductor products, is a technical problem that needs to be solved urgently. Summary of the invention
[0005] The present invention provides a method for reducing photoresist stripping defects, which is used to reduce the photoresist stripping defects while reducing the semiconductor research and development cost, thereby improving the manufacturing yield and manufacturing efficiency of semiconductor products.
[0006] According to some embodiments, the present invention provides a method for reducing photoresist stripping defects, comprising the following steps:
[0007] Providing a test structure, the test structure comprising a wafer and a first photoresist layer located on the wafer;
[0008] Forming a test mask, wherein the test mask has a plurality of test patterns arranged in parallel and at intervals, wherein the line width of the test pattern is greater than or equal to the line width of the standard pattern, and along the arrangement direction of the plurality of test patterns, the test spacing between adjacent test patterns gradually increases, and the largest test spacing is used as the maximum test spacing;
[0009] After exposing and developing the test structure using the test mask, removing the first photoresist layer, and forming a plurality of etching patterns corresponding to the plurality of test patterns on the wafer;
[0010] Selecting the etching pattern corresponding to the test pattern with the maximum test pitch as a first target etching pattern, determining whether a line width of the first target etching pattern is smaller than a line width of the standard pattern, and if so, obtaining a difference between the line width of the first target etching pattern and the line width of the standard pattern as a first complementary value;
[0011] The first complementary value is used to compensate the line width of the actual pattern whose actual pitch is greater than or equal to the maximum test pitch to form a corrected mask.
[0012] In some embodiments, the specific steps of forming a test mask include:
[0013] A plurality of test pattern groups are formed, each of the test pattern groups includes a plurality of test patterns that are parallel to each other and arranged at intervals, and the line widths of the test patterns in the plurality of test pattern groups are different from each other. For each of the test pattern groups, the test spacing between adjacent test patterns gradually increases along the arrangement direction of the plurality of test patterns.
[0014] In some embodiments, the first complementary value is used to compensate the line width of the actual pattern whose actual spacing is greater than or equal to the maximum test spacing, and the specific steps of forming the correction mask include:
[0015] The line width of the actual pattern whose actual pitch is greater than or equal to the maximum test pitch is enlarged by the first complementary value to form the corrected mask.
[0016] In some embodiments, a difference between a line width of the actual pattern and a line width of the test pattern before compensation with the first complementary value is less than or equal to 5 nm.
[0017] In some embodiments, the following steps are also included:
[0018] Selecting the etching pattern corresponding to the test pattern with a target test pitch as a second target etching pattern, wherein the target test pitch is smaller than the maximum test pitch, determining whether the line width of the second target etching pattern is smaller than the line width of the standard pattern, and if so, obtaining a difference between the line width of the second target etching pattern and the line width of the standard pattern as a second complementary value;
[0019] The second complementary value is used to compensate the line width of the actual pattern whose actual pitch is equal to the target test pitch to form the corrected mask.
[0020] In some embodiments, the wafer includes a first wafer test area, the first wafer test area includes an active area, and the first photoresist layer is distributed above the active area; after exposing and developing the test structure using the test mask, the first photoresist layer is removed, and the specific steps of forming a plurality of etching patterns corresponding to the plurality of test patterns on the wafer include:
[0021] After the test structure is exposed and developed by using the test mask, the first photoresist layer is removed to form a plurality of etching patterns above the active area of the first wafer test region of the wafer.
[0022] In some embodiments, the wafer further includes a second wafer test area, the second wafer test area includes the active area and a shallow trench isolation area outside the active area, the first photoresist layer is distributed above the first wafer test area and the second wafer test area; the method for reducing photoresist stripping defects further includes the following steps:
[0023] After exposing and developing the test structure using the test mask, removing the first photoresist layer, and forming a plurality of etching patterns in the first wafer test area and the second wafer test area of the wafer respectively;
[0024] The etching patterns corresponding to the test pattern with the maximum test spacing are respectively selected in the first wafer test area and the second wafer test area as the first target etching pattern, and it is determined whether the difference between the first target etching pattern in the first wafer test area and the first target etching pattern in the second wafer test area is less than a first preset difference; if not, the difference between the line width of the first target etching pattern in the second wafer test area and the line width of the standard pattern is used as the first complementary value.
[0025] In some embodiments, the first preset difference is 3nm-5nm.
[0026] In some embodiments, the test mask includes a first mask test area and a second mask test area, the first mask test area includes a plurality of the test patterns arranged in parallel and at intervals, the second mask test area also includes a plurality of the test patterns arranged in parallel and at intervals and an auxiliary pattern located between adjacent test patterns; the method for reducing photoresist stripping defects also includes the following steps:
[0027] After exposing and developing the test structure using the test mask, removing the first photoresist layer, and forming a first etching pattern area corresponding to the first mask test area and a second etching pattern area corresponding to the second mask test area on the wafer;
[0028] The etching patterns corresponding to the test pattern with the maximum test spacing are respectively selected in the first etching pattern area and the second etching pattern area as the first target etching pattern, and it is determined whether the difference between the first target etching pattern in the first etching pattern area and the first target etching pattern in the second etching pattern area is less than a second preset difference; if not, the difference between the line width of the first target etching pattern in the second etching pattern area and the line width of the standard pattern is used as the first complementary value.
[0029] In some embodiments, a material of the test pattern is different from a material of the auxiliary pattern, and a material of the auxiliary pattern is polysilicon.
[0030] In some embodiments, the test mask includes a first mask test area and a third mask test area, the first mask test area and the third mask test area each include a plurality of test patterns that are parallel to each other and arranged at intervals, and the length of the test pattern in the first mask test area is different from the length of the test pattern in the third mask test area; the method for reducing photoresist stripping defects also includes the following steps:
[0031] After exposing and developing the test structure using the test mask, removing the first photoresist layer, and forming a third etched pattern area corresponding to the first mask test area and a fourth etched pattern area corresponding to the third mask test area on the wafer;
[0032] In the third etching pattern area and the fourth etching pattern area, the etching patterns corresponding to the test pattern with the maximum test spacing are respectively selected as the first target etching pattern, and it is determined whether the line widths of the first target etching patterns in the third etching pattern area and the fourth etching pattern area are both smaller than the line width of the standard pattern; if so, the differences between the line widths of the first target etching patterns in the third etching pattern area and the fourth etching pattern area and the line width of the standard pattern are respectively used as the first complementary value.
[0033] In some embodiments, the test pattern is in the shape of a long strip, and the third mask test area also includes a plurality of parallel and spaced-apart trunk patterns, each of the trunk patterns being located at the end of a plurality of the test patterns having the same test spacing and being continuously and vertically connected to the ends of the plurality of the test patterns having the same test spacing.
[0034] In some embodiments, the wafer includes an active area and a peripheral area outside the active area, and the etching pattern is formed on the active area; after forming a plurality of etching patterns corresponding to the plurality of test patterns on the wafer, the method further includes the following steps:
[0035] forming a second photoresist layer on the wafer, wherein the second photoresist layer has an opening exposing the peripheral area;
[0036] implanting doping ions into the peripheral region and removing the second photoresist layer;
[0037] The resistance of the active area is detected, and it is determined whether the resistance of the active area is lower than a preset active area resistance. If so, it is confirmed that the second photoresist layer is stripped.
[0038] The method for reducing photoresist stripping defects provided by the present invention comprises the following steps: a plurality of test patterns which are arranged in parallel and at intervals are arranged in a test mask, the line width of the test patterns being greater than the line width of a standard pattern, and the test spacing between adjacent test patterns gradually increasing along the arrangement direction of the plurality of test patterns. The pattern on the test mask is transferred to a test structure by a photolithography process, and the compensation value required for a graphic area with a risk of photoresist stripping and / or suffering from a photoresist stripping defect can be obtained by a single exposure and development, without the need to repeatedly publish a plurality of test masks, thereby not only reducing the photoresist stripping defect from the source, but also saving semiconductor research and development time and research and development funds, and improving semiconductor research and development efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1 is a flow chart of a method for reducing photoresist stripping defects in a specific embodiment of the present invention;
[0040] Figure 2 is a schematic diagram of an arrangement of multiple test patterns in a test mask according to a specific embodiment of the present invention;
[0041] Figure 3 is another schematic diagram of the arrangement of multiple test patterns in a test mask according to a specific embodiment of the present invention;
[0042] Figure 4 is another schematic diagram of the arrangement of multiple test patterns in the test mask according to a specific embodiment of the present invention;
[0043] Figure 5 It is a structural schematic diagram of testing the resistance of the active area in a specific implementation manner of the present invention.
[0044] Description of Reference Numerals
[0045] 20 test patterns
[0046] P1 First test spacing
[0047] P2 Second test spacing
[0048] P3 Third test spacing
[0049] 30 auxiliary patterns
[0050] 40 Main pattern
[0051] 60 Active area
[0052] 61 Ion implantation area
[0053] 62 Metal pad DETAILED DESCRIPTION
[0054] The specific implementation of the method for reducing photoresist stripping defects provided by the present invention is described in detail below with reference to the accompanying drawings.
[0055] This specific embodiment provides a method for reducing photoresist stripping defects. Figure 1 FIG. 1 is a flow chart of a method for reducing photoresist stripping defects in a specific embodiment of the present invention. Figure 1 As shown, the method for reducing photoresist stripping defects comprises the following steps:
[0056] Step S11, providing a test structure, wherein the test structure includes a wafer and a first photoresist layer located on the wafer;
[0057] Step S12, forming a test mask, wherein the test mask has a plurality of test patterns arranged in parallel and at intervals, wherein the line width of the test pattern is greater than or equal to the line width of the standard pattern, and along the arrangement direction of the plurality of test patterns, the test spacing between adjacent test patterns gradually increases, and the largest test spacing is used as the maximum test spacing;
[0058] Step S13, after exposing and developing the test structure using the test mask, removing the first photoresist layer, and forming a plurality of etching patterns corresponding to the plurality of test patterns on the wafer;
[0059] Step S14, selecting the etching pattern corresponding to the test pattern with the maximum test pitch as the first target etching pattern, determining whether the line width of the first target etching pattern is smaller than the line width of the standard pattern, and if so, obtaining the difference between the line width of the first target etching pattern and the line width of the standard pattern as the first complementary value;
[0060] Step S15 , using the first complementary value to compensate for the line width of the actual pattern whose actual pitch is greater than or equal to the maximum test pitch, so as to form a corrected mask.
[0061] Figure 2 Schematic diagram of the arrangement of multiple test patterns in a test mask according to a specific embodiment of the present invention. In some embodiments, the specific steps of forming the test mask include:
[0062] A plurality of test pattern groups are formed, each of the test pattern groups includes a plurality of test patterns 20 that are parallel to each other and arranged at intervals, and the line widths of the test patterns 20 in the plurality of test pattern groups are different from each other. For each of the test pattern groups, along the arrangement direction of the plurality of test patterns 20, the test spacing between adjacent test patterns 20 gradually increases.
[0063] In some embodiments, the first complementary value is used to compensate the line width of the actual pattern whose actual spacing is greater than or equal to the maximum test spacing, and the specific steps of forming the correction mask include:
[0064] The line width of the actual pattern whose actual pitch is greater than or equal to the maximum test pitch is enlarged by the first complementary value to form the corrected mask.
[0065] In order to further improve the compensation effect of the first compensation value, the line width of the actual pattern before the first compensation value compensation is greater than or equal to the line width of the standard pattern. In some embodiments, the difference between the line width of the actual pattern before the first compensation value compensation and the line width of the test pattern 20 is less than or equal to 5nm.
[0066] For example, the test mask has a plurality of test pattern groups, each of which includes a plurality of test patterns 20 arranged in parallel and at intervals, and for each test pattern group, along the arrangement direction of the plurality of test patterns 20, the test spacing between adjacent test patterns 20 gradually increases, so that the complementary values of the test patterns 20 with different line widths can be obtained through a single exposure and development, thereby further improving the efficiency of semiconductor research and development and reducing the cost of semiconductor research and development. The test spacing refers to the spacing width between adjacent test patterns 20 in the same test pattern group. In one example, the maximum test spacing is 1200nm. Table 1 shows the line width and test pitch of the test patterns 20 in the multiple test pattern groups in the test mask. For example, the test pitch of the multiple test patterns 20 with a line width of 162nm is 162nm, 172nm, 182nm, 192nm, 250nm, 300nm, 350nm, 450nm, 550nm, 700nm, 800nm, 1000nm and 1200nm.
[0067] Table 1 Line width and test spacing dimensions of test patterns in test masks
[0068]
[0069] Figure 2 The arrangement of the plurality of test patterns 20 in one test pattern group is shown as an example, and Figure 2 The line width of all the test patterns 20 in the embodiment is 172 nm. In the arrangement direction of the plurality of test patterns 20, there is a first test pitch P1, a second test pitch P2, a third test pitch P3 and a fourth test pitch P4 between adjacent test patterns 20, and the first test pitch P1 is smaller than the second test pitch P2, the second test pitch P2 is smaller than the third test pitch P3, and the third test pitch P3 is smaller than the fourth test pitch P4. Figure 2Taking the test pattern group shown as an example, the maximum test spacing is the fourth test spacing P4. The test structure is exposed and developed using a photolithography process and the test mask, so that a plurality of etching patterns corresponding to the plurality of test patterns 20 are formed on the wafer in the test structure. By measuring the etching patterns on the wafer, the line widths of the plurality of etching patterns and the test spacing between adjacent etching patterns can be obtained. The etching pattern corresponding to the test pattern 20 having the maximum test spacing (for example, the fourth test spacing P4) is selected as the first target etching pattern, and it is determined whether the line width of the first target etching pattern is less than the line width of the standard pattern. If so, it is confirmed that the test pattern 20 having the maximum test spacing has a photoresist stripping defect when it is transferred to the wafer through exposure and development, and the difference between the line width of the first target etching pattern and the line width of the standard pattern is obtained as the first complementary value. In one example, the line width of the standard pattern is 162nm. According to a preset layout (the preset layout includes a plurality of pre-designed and spaced actual patterns), the line width of the actual pattern whose line width is within a preset range (for example, the difference with the line width of the test pattern is within 5nm) and the actual spacing is above the maximum test spacing is enlarged by the first complementary value through OPC correction to form the corrected mask. The actual spacing refers to the spacing width between adjacent actual patterns.
[0070] In practical applications, the line width of the actual pattern whose line width is within the preset range and whose actual spacing is greater than or equal to the maximum test spacing is enlarged by the first complementary value to form the correction mask, thereby further reducing the photoresist stripping defects in the process of manufacturing large test spacing patterns. For example, for the test pattern 20 with a line width of 172nm and a test spacing of 1200nm, the line width of the etched pattern obtained after exposure and development is 150nm. Since 150nm is less than 162nm (i.e., the line width of the standard pattern), it is confirmed that the test pattern 20 with the 1200nm test spacing has a photoresist stripping defect when it is transferred to the wafer through exposure and development, and since the line width difference between the etched pattern and the test pattern 20 is 12nm, 12nm is used as the first complementary value. The line width of the actual pattern 20 with a line width within the range of 167nm to 177nm and an actual spacing of more than 1200nm is enlarged by 12nm through OPC correction to form the correction mask.
[0071] In some embodiments, the method for reducing photoresist stripping defects further comprises the following steps:
[0072] Selecting the etching pattern corresponding to the test pattern 20 having a target test pitch as a second target etching pattern, wherein the target test pitch is smaller than the maximum test pitch, determining whether the line width of the second target etching pattern is smaller than the line width of the standard pattern, and if so, obtaining a difference between the line width of the second target etching pattern and the line width of the standard pattern as a second complementary value;
[0073] The second complementary value is used to compensate the line width of the actual pattern whose actual pitch is the target test pitch to form a corrected mask.
[0074] The following is an example in which the line width of the test pattern 20 is 172nm and the target test spacing is 550nm. The test structure is exposed and developed using a photolithography process and the test mask, so that a plurality of etching patterns corresponding to the plurality of test patterns 20 are formed on the wafer in the test structure. By measuring the etching patterns on the wafer, the line widths of the plurality of etching patterns and the test spacing between adjacent etching patterns can be obtained. It is determined whether the line width of the second target etching pattern corresponding to the test pattern 20 with a line width of 172nm and a target test spacing of 550nm is smaller than the line width of the standard pattern. If so, it is confirmed that the test pattern 20 with the target test spacing has a photoresist stripping defect when it is transferred to the wafer through exposure and development. The difference between the line width of the second target etching pattern and the line width of the standard pattern is obtained as the second complementary value. The line width of the actual pattern with a line width of 172 nm and an actual pitch equal to the target test pitch is enlarged by the second complementary value through OPC correction to form the corrected mask.
[0075] In order to simulate a real semiconductor product, thereby further improving the accuracy of the compensation value, in some embodiments, the wafer includes a first wafer test area, the first wafer test area includes an active area, and the first photoresist layer is distributed above the active area; after the test structure is exposed and developed using the test mask, the first photoresist layer is removed, and the specific steps of forming a plurality of etching patterns corresponding to the plurality of test patterns 20 on the wafer include:
[0076] After the test structure is exposed and developed by using the test mask, the first photoresist layer is removed to form a plurality of etching patterns above the active area of the first wafer test region of the wafer.
[0077] In some embodiments, the wafer further includes a second wafer test area, the second wafer test area includes the active area and a shallow trench isolation area outside the active area, the first photoresist layer is distributed above the first wafer test area and the second wafer test area; the method for reducing photoresist stripping defects further includes the following steps:
[0078] After exposing and developing the test structure using the test mask, removing the first photoresist layer, and forming a plurality of etching patterns in the first wafer test area and the second wafer test area of the wafer respectively;
[0079] The etching patterns corresponding to the test pattern 20 having the maximum test spacing are respectively selected in the first wafer test area and the second wafer test area as the first target etching pattern, and it is determined whether the difference between the first target etching pattern in the first wafer test area and the first target etching pattern in the second wafer test area is less than a first preset difference; if not, the difference between the line width of the first target etching pattern in the second wafer test area and the line width of the standard pattern is used as the first complementary value.
[0080] In some embodiments, the first preset difference is 3nm-5nm.
[0081] Specifically, by setting the first wafer test area and the second wafer test area in the wafer of the test structure, the first wafer test area includes an active area, and the second wafer test area includes the active area and a shallow trench isolation area outside the active area. After the test structure is exposed and developed using the test mask, a plurality of etching patterns are formed in the first wafer test area and the second wafer test area of the wafer, respectively, so that the influence of different structures in the wafer on the photolithography process can be obtained, so as to better simulate the structure of a real semiconductor product, so as to further improve the accuracy and reliability of the first compensation value.
[0082] Figure 3 1 is another arrangement diagram of multiple test patterns in a test mask according to a specific embodiment of the present invention. In some embodiments, the test mask includes a first mask test area and a second mask test area, and the first mask test area includes multiple test patterns 20 arranged in parallel and at intervals (see Figure 2 ), the second mask test area also includes a plurality of the test patterns 20 arranged in parallel and at intervals and an auxiliary pattern 30 located between adjacent test patterns 20 (see Figure 3 ); The method for reducing photoresist stripping defects also includes the following steps:
[0083] After exposing and developing the test structure using the test mask, removing the first photoresist layer, and forming a first etching pattern area corresponding to the first mask test area and a second etching pattern area corresponding to the second mask test area on the wafer;
[0084] The etching patterns corresponding to the test pattern with the maximum test spacing are respectively selected in the first etching pattern area and the second etching pattern area as the first target etching pattern, and it is determined whether the difference between the first target etching pattern in the first etching pattern area and the first target etching pattern in the second etching pattern area is less than a second preset difference; if not, the difference between the line width of the first target etching pattern in the second etching pattern area and the line width of the standard pattern is used as the first complementary value.
[0085] In some embodiments, the material of the test pattern is different from the material of the auxiliary pattern 30 , and the material of the auxiliary pattern 30 is polysilicon.
[0086] For example, the test mask includes a first mask test area and a second mask test area, and the arrangement of the plurality of test patterns 20 in the first mask test area is as follows: Figure 2 As shown, the arrangement of the plurality of test patterns 20 and the auxiliary patterns 30 of polysilicon material in the second mask test area is as follows: Figure 3 By comparing the difference in line width between the first target etching pattern formed after the test pattern 20 in the first mask test area is transferred to the wafer and the first target etching pattern formed after the test pattern 20 in the second mask test area is transferred to the wafer, the influence of the diffraction effect of the auxiliary pattern 30 of the polysilicon material on the line width of the first target etching pattern can be known during the photolithography process, so as to better simulate the structure of the real semiconductor product, so as to further improve the accuracy and reliability of the first compensation value.
[0087] Figure 4 It is another schematic diagram of the arrangement of multiple test patterns in the test mask of a specific embodiment of the present invention. In some embodiments, the test mask includes a first mask test area and a third mask test area, the first mask test area and the third mask test area both include a plurality of test patterns 20 arranged in parallel and spaced apart from each other, and the length of the test pattern 20 in the first mask test area is different from the length of the test pattern 20 in the third mask test area; the method for reducing photoresist stripping defects also includes the following steps:
[0088] After exposing and developing the test structure using the test mask, removing the first photoresist layer, and forming a third etched pattern area corresponding to the first mask test area and a fourth etched pattern area corresponding to the third mask test area on the wafer;
[0089] In the third etching pattern area and the fourth etching pattern area, the etching patterns corresponding to the test pattern with the maximum test spacing are respectively selected as the first target etching pattern, and it is determined whether the line widths of the first target etching patterns in the third etching pattern area and the fourth etching pattern area are both smaller than the line width of the standard pattern; if so, the differences between the line widths of the first target etching patterns in the third etching pattern area and the fourth etching pattern area and the line width of the standard pattern are respectively used as the first complementary value.
[0090] In some embodiments, the test pattern 20 is in the shape of a long strip, and the third mask test area further includes a plurality of parallel and spaced trunk patterns 40, each of which is located at the end of a plurality of the test patterns 20 having the same test pitch and is continuously and vertically connected to the ends of the plurality of the test patterns 20 having the same test pitch, such as Figure 4 shown.
[0091] For example, the test mask includes a first mask test area and a third mask test area, wherein the first mask test area includes a plurality of test patterns 20 arranged in parallel and at intervals and a plurality of trunk patterns 40 arranged in parallel and at intervals, each of the trunk patterns 40 is located at the end of the plurality of test patterns 20 having the same test pitch and is continuously and vertically connected to the ends of the plurality of test patterns 20 having the same test pitch, forming a plurality of comb-shaped structures, such as Figure 4 By comparing the difference in line width between the first target etching pattern formed after the test pattern 20 in the first mask test area is transferred to the wafer and the first target etching pattern formed after the test pattern 20 in the third mask test area is transferred to the wafer, the influence of the length of the test pattern in the lithography process and the pattern of the comb-tooth structure on the line width of the first target etching pattern and the photoresist stripping defect can be known, so as to better simulate the structure of the real semiconductor product and further improve the accuracy and reliability of the first compensation value.
[0092] Figure 560 is a schematic diagram of a structure when testing the resistance of the active area in a specific embodiment of the present invention. In some embodiments, the wafer includes an active area and a peripheral area outside the active area, and the etching pattern is formed on the active area 60; after forming a plurality of etching patterns corresponding to the plurality of test patterns 20 on the wafer, the following steps are also included:
[0093] forming a second photoresist layer on the wafer, wherein the second photoresist layer has an opening exposing the peripheral area;
[0094] implanting doping ions into the peripheral region and removing the second photoresist layer;
[0095] The resistance of the active area 60 is detected, and it is determined whether the resistance of the active area 60 is lower than a preset active area resistance. If so, it is confirmed that the second photoresist layer is stripped.
[0096] Specifically, after doping ions are implanted into the peripheral region to form the ion implantation region 61, the active region 60 can be electrically connected through the metal pad 62 to detect the resistance of the active region 60. Since additional ions are implanted into the active region 60 after the second photoresist layer stripping defect occurs, the resistance of the active region 60 is significantly reduced, and thus by judging whether the resistance of the active region 60 is lower than the preset active region resistance, it can be confirmed whether the second photoresist layer has a stripping defect.
[0097] The method for reducing photoresist stripping defects provided in this specific embodiment is achieved by setting a plurality of test patterns that are parallel to each other and arranged at intervals in a test mask, wherein the line width of the test patterns is greater than the line width of a standard pattern, and the test spacing between adjacent test patterns gradually increases along the arrangement direction of the plurality of test patterns. The pattern on the test mask is transferred to a test structure using a photolithography process, and the required compensation value for a graphic area with a risk of photoresist stripping and / or suffering from a photoresist stripping defect can be obtained through a single exposure and development, without the need to repeatedly publish multiple test masks, which not only reduces photoresist stripping defects at the source, but also saves semiconductor R&D time and R&D funds, thereby improving semiconductor R&D efficiency.
[0098] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A method for reducing photoresist stripping defects, characterized in that: The steps include: Providing a test structure, the test structure comprising a wafer and a first photoresist layer located on the wafer; Forming a test mask, wherein the test mask has a plurality of test patterns arranged in parallel and at intervals, wherein the line width of the test pattern is greater than or equal to the line width of the standard pattern, and along the arrangement direction of the plurality of test patterns, the test spacing between adjacent test patterns gradually increases, and the largest test spacing is used as the maximum test spacing; After exposing and developing the test structure using the test mask, removing the first photoresist layer, and forming a plurality of etching patterns corresponding to the plurality of test patterns on the wafer; Selecting the etching pattern corresponding to the test pattern with the maximum test pitch as a first target etching pattern, determining whether a line width of the first target etching pattern is smaller than a line width of the standard pattern, and if so, obtaining a difference between the line width of the first target etching pattern and the line width of the standard pattern as a first complementary value; The first complementary value is used to compensate the line width of the actual pattern whose actual pitch is greater than or equal to the maximum test pitch to form a corrected mask.
2. The method for reducing photoresist stripping defects according to claim 1, characterized in that: The specific steps of forming the test mask include: A plurality of test pattern groups are formed, each of the test pattern groups includes a plurality of test patterns that are parallel to each other and arranged at intervals, and the line widths of the test patterns in the plurality of test pattern groups are different from each other. For each of the test pattern groups, the test spacing between adjacent test patterns gradually increases along the arrangement direction of the plurality of test patterns.
3. The method for reducing photoresist stripping defects according to claim 1, characterized in that: The specific steps of using the first complementary value to compensate the line width of the actual pattern whose actual spacing is greater than or equal to the maximum test spacing to form a corrected mask include: The line width of the actual pattern whose actual pitch is greater than or equal to the maximum test pitch is enlarged by the first complementary value to form the corrected mask.
4. The method for reducing photoresist stripping defects according to claim 1, characterized in that: A difference between a line width of the actual pattern and a line width of the test pattern before compensation with the first complementary value is less than or equal to 5 nm.
5. The method for reducing photoresist stripping defects according to claim 1, characterized in that: The following steps are also included: Selecting the etching pattern corresponding to the test pattern with a target test pitch as a second target etching pattern, wherein the target test pitch is smaller than the maximum test pitch, determining whether the line width of the second target etching pattern is smaller than the line width of the standard pattern, and if so, obtaining a difference between the line width of the second target etching pattern and the line width of the standard pattern as a second complementary value; The second complementary value is used to compensate the line width of the actual pattern whose actual pitch is equal to the target test pitch to form the corrected mask.
6. The method for reducing photoresist stripping defects according to claim 1, characterized in that: The wafer includes a first wafer test area, the first wafer test area includes an active area, and the first photoresist layer is distributed above the active area; after the test structure is exposed and developed using the test mask, the first photoresist layer is removed, and a plurality of etching patterns corresponding to the plurality of test patterns are formed on the wafer. The specific steps include: After the test structure is exposed and developed by using the test mask, the first photoresist layer is removed to form a plurality of etching patterns above the active area of the first wafer test region of the wafer.
7. The method for reducing photoresist stripping defects according to claim 6, characterized in that: The wafer further includes a second wafer test area, the second wafer test area includes the active area and a shallow trench isolation area outside the active area, the first photoresist layer is distributed above the first wafer test area and the second wafer test area; the method for reducing photoresist stripping defects also includes the following steps: After exposing and developing the test structure using the test mask, removing the first photoresist layer, and forming a plurality of etching patterns in the first wafer test area and the second wafer test area of the wafer respectively; The etching patterns corresponding to the test pattern with the maximum test spacing are respectively selected in the first wafer test area and the second wafer test area as the first target etching pattern, and it is determined whether the difference between the first target etching pattern in the first wafer test area and the first target etching pattern in the second wafer test area is less than a first preset difference; if not, the difference between the line width of the first target etching pattern in the second wafer test area and the line width of the standard pattern is used as the first complementary value.
8. The method for reducing photoresist stripping defects according to claim 7, characterized in that: The first preset difference is 3nm-5nm.
9. The method for reducing photoresist stripping defects according to claim 1, characterized in that: The test mask includes a first mask test area and a second mask test area, the first mask test area includes a plurality of test patterns arranged in parallel and at intervals, the second mask test area also includes a plurality of test patterns arranged in parallel and at intervals and an auxiliary pattern located between adjacent test patterns; the method for reducing photoresist stripping defects also includes the following steps: After exposing and developing the test structure using the test mask, removing the first photoresist layer, and forming a first etching pattern area corresponding to the first mask test area and a second etching pattern area corresponding to the second mask test area on the wafer; The etching patterns corresponding to the test pattern with the maximum test spacing are respectively selected in the first etching pattern area and the second etching pattern area as the first target etching pattern, and it is determined whether the difference between the first target etching pattern in the first etching pattern area and the first target etching pattern in the second etching pattern area is less than a second preset difference; if not, the difference between the line width of the first target etching pattern in the second etching pattern area and the line width of the standard pattern is used as the first complementary value.
10. The method for reducing photoresist stripping defects according to claim 9, characterized in that: The material of the test pattern is different from that of the auxiliary pattern, and the material of the auxiliary pattern is polysilicon.
11. The method for reducing photoresist stripping defects according to claim 1, characterized in that: The test mask includes a first mask test area and a third mask test area, the first mask test area and the third mask test area both include a plurality of test patterns that are parallel to each other and spaced apart, and the length of the test pattern in the first mask test area is different from the length of the test pattern in the third mask test area; the method for reducing photoresist stripping defects also includes the following steps: After exposing and developing the test structure using the test mask, removing the first photoresist layer, and forming a third etched pattern area corresponding to the first mask test area and a fourth etched pattern area corresponding to the third mask test area on the wafer; In the third etching pattern area and the fourth etching pattern area, the etching patterns corresponding to the test pattern with the maximum test spacing are respectively selected as the first target etching pattern, and it is determined whether the line widths of the first target etching patterns in the third etching pattern area and the fourth etching pattern area are both smaller than the line width of the standard pattern; if so, the differences between the line widths of the first target etching patterns in the third etching pattern area and the fourth etching pattern area and the line width of the standard pattern are respectively used as the first complementary value.
12. The method for reducing photoresist stripping defects according to claim 11, characterized in that: The test pattern is in the shape of a long strip, and the third mask test area also includes a plurality of parallel and spaced-apart trunk patterns, each of which is located at the end of a plurality of the test patterns with the same test spacing and is continuously and vertically connected to the ends of the plurality of the test patterns with the same test spacing.
13. The method for reducing photoresist stripping defects according to claim 1, characterized in that: The wafer includes an active area and a peripheral area outside the active area, and the etching pattern is formed on the active area; after forming a plurality of etching patterns corresponding to the plurality of test patterns on the wafer, the method further includes the following steps: forming a second photoresist layer on the wafer, wherein the second photoresist layer has an opening exposing the peripheral area; implanting doping ions into the peripheral region and removing the second photoresist layer; The resistance of the active area is detected, and it is determined whether the resistance of the active area is lower than a preset active area resistance. If so, it is confirmed that the second photoresist layer is stripped.