CPU chip capable of resisting power consumption side channel attack based on energy trace balance
By introducing T interference modules and M interference modules into the CPU chip, targeted interference instructions are generated, and the problems of insufficient protection of different CPU models and poor noise interference protection in the prior art are solved, customized protection of different CPU models and efficient noise interference are achieved, and the CPU's resistance to side channel attacks is enhanced.
Patent Information
- Application Number
- CN202510058591.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-14
- Publication Date
- 2025-05-13
AI Technical Summary
The prior art has failed to achieve targeted protection of different CPU chip models, and the traditional noise interference protection effect is poor, so it cannot effectively resist power-side channel attacks.
Using an anti-power-dissipation-side channel attack CPU chip based on energy trace balance, the T interference module and the M interference module are introduced into the protection module to generate targeted interference instructions to ensure that the energy trace of the interference instructions is large and offset, and a fixed energy trace is formed.
Customized protection of different CPU chip models is achieved, which increases the difficulty of attackers, reduces the possibility of attack success, and improves the CPU's ability to resist side channel attacks.
Smart Images
Figure CN119989434A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of CPU power consumption side channel protection, and in particular to a CPU chip resistant to power consumption side channel attacks based on energy trace balance. Background Art
[0002] With the continuous development of computer technology, server performance and security issues have become an important research direction in the computer field. In traditional computer systems, the CPU is the core component of the entire system, and its security issues directly affect the performance and stability of the entire system. Therefore, how to improve the CPU's anti-attack capabilities and improve the system's performance and stability has become an important issue in the computer field.
[0003] There are several methods available to protect the CPU's power consumption side channel: (i) Use a power consumption balancing algorithm. By designing the algorithm, the power consumption of processing various data is consistent, thereby eliminating the correlation between power consumption changes and data processing, and increasing the difficulty for attackers to infer. This method requires that the algorithm fully consider the power consumption balancing factor when designing; (ii) Power consumption management technology. By adopting power consumption management technology such as dynamic voltage adjustment and power consumption gating, the amplitude of power consumption changes is reduced, making it difficult for attackers to infer valid information from power consumption changes; (iii) Random noise technology. Adding random noise to the CPU's power supply line can mask the power consumption changes of the CPU during operation, making it difficult for attackers to extract valid information from it.
[0004] However, the above-mentioned power consumption side channel protection method has the following problems: 1. Targeted protection of CPU chip models is not implemented. For a series of multiple specific CPU models, traditional power consumption side channel protection measures do not implement customized targeted protection. The specific parameters of the protection measures often cannot be bound to the specific models, so the protection measures on different models are almost the same. This gives attackers the opportunity to attack the power consumption performance differences of different CPU models. 2. Targeted noise interference of CPU instructions is not implemented. Traditional noise interference schemes do not impose targeted interference on specific CPU instructions at the instruction level. In terms of statistical characteristics, when different types of instructions are executed, the interference signals of the noise interference module often have the same statistical characteristics, which gives attackers greater opportunities for noise reduction. Summary of the invention
[0005] Aiming at the problems that the CPU power consumption side channel protection method fails to realize targeted protection for different CPU chip models and the traditional noise interference protection effect is poor, the present invention provides a CPU chip resistant to power consumption side channel attacks based on energy trace balance.
[0006] The present invention is implemented by adopting the following technical scheme: a CPU chip resistant to power consumption side channel attacks based on energy trace balance, comprising a protection module for generating power consumption interference instructions, wherein the protection module comprises a T interference module and an M interference module.
[0007] The T interference module includes a separation characteristic table, a random number generator, an instruction content register and a random instruction selector; the separation characteristic table is used to record the alternative instructions of each actual execution instruction and the separation between the actual execution instruction and L alternative instructions, the random number generator generates a random number r, which falls on the interval [a, b]; the instruction content register records the content of the current actual execution instruction; the random instruction selector uses the separation between the alternative instructions and the actual execution instructions as the weight, divides the interval [a, b] into L parts, and selects the alternative instructions with the same order as the final interference instructions according to the order in which the random number r falls on the interval.
[0008] The M interference module includes an active module identification table, a parameter source identifier, a module input generator and a mirror function module; the active module identification table records the active modules corresponding to different actual execution instructions, the parameter source identifier identifies the parameter source of the actual execution instruction, and distinguishes whether the source is inside or outside the CPU; identifies the parameter source required by the interference instruction, and distinguishes whether the source is inside or outside the CPU; the module input generator obtains data from the parameter source identifier, and for the interference instruction, for the parameters of the internal source, directly obtains the internal parameters of the actual execution instruction and inverts them bit by bit as the internal parameters of the interference instruction; for the parameters of the external source, if they also exist in the external parameters of the actual execution instruction, they are directly obtained and the values remain unchanged; if they do not exist in the external parameters of the actual execution instruction, they are replaced by random numbers; thereby, a complete interference instruction with parameters is generated; the mirror function module identifies the active module and the inactive module of the actual execution instruction, sets the mirror function module enable signal corresponding to the active module to inactive, and sets the mirror function module enable signal corresponding to the inactive module to active, the parameters from the instruction required by the mirror function module are provided by the interference instruction, and the content from the IO and storage modules required by the mirror function module is directly obtained from the IO and storage modules.
[0009] When the CPU executes a specific instruction, a mirror function module in the protection module executes an interference instruction. Two CPU instructions are executed at the same time. The power consumption caused by the interference instruction affects the total power consumption of the CPU. The energy trace of the interference instruction and the energy trace of the actual execution instruction are very different, which just offset each other, and the overall energy trace tends to a fixed energy trace, making it impossible for attackers to use devices such as temperature sensors and oscilloscopes to guess what kind of instructions the current CPU actually executes through the power consumption characteristics of the CPU, thereby concealing the actual operation of the CPU and protecting the side channel security of the CPU chip.
[0010] The above-mentioned energy trace balance-based anti-power consumption side channel attack CPU chip, the protection module also includes an idle signal receiving module, the idle signal receiving module includes an output resistor, an output capacitor and a protection resistor, all output pins of the mirror function module are connected to the output resistor, the output resistors are all connected in parallel and connected to an output capacitor, and the other side of the output capacitor is grounded after another protection resistor.
[0011] In the above-mentioned energy trace balance-based anti-power consumption side channel attack CPU chip, the idle signal receiving module and the T interference module and the M interference module are all arranged in the CPU chip shell and are electromagnetically shielded by the metal shell.
[0012] Compared with the prior art, the present invention has at least one of the following advantages:
[0013] 1. Realize targeted protection of CPU chip models
[0014] For different CPU models, even for the same instructions, the division of active modules and inactive modules may be different. Therefore, for this CPU, the power consumption side channel protection measures have achieved customized targeted protection, and the specific parameters of the protection measures have been bound to the specific model, so the protection measures on different models are different, which basically eliminates the possibility of attackers launching attacks based on the power consumption performance differences of different CPU models.
[0015] 2. Implement targeted noise interference of CPU instructions
[0016] The noise interference scheme of this CPU realizes targeted interference on specific CPU instructions at the instruction level. In terms of statistical characteristics, when different types of instructions are executed, the interference signal of the noise interference module has different statistical characteristics, which greatly reduces the attacker's greater noise reduction opportunities.
[0017] 3. Provides a new method for CPU to resist simple power consumption attacks
[0018] The design of this CPU improves the information entropy of power consumption changes, thereby ensuring the security of the CPU and providing the industry with a typical solution for resisting side-channel attacks. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 It is a principle block diagram of the present invention. DETAILED DESCRIPTION
[0020] The present invention discloses a CPU chip with the characteristic of resisting power consumption side channel attack. When the CPU executes a specific instruction, a mirror function module in a protection module executes an interference instruction, and two CPU instructions are executed simultaneously, wherein the power consumption caused by the interference instruction affects the total power consumption of the CPU. The energy trace of the interference instruction and the energy trace of the actual execution instruction are very different, and they just offset each other, and the whole tends to a fixed energy trace, so that the attacker cannot use devices such as temperature sensors and oscilloscopes to guess what kind of instruction the current CPU actually executes through the power consumption characteristics of the CPU, thereby concealing the actual operation of the CPU and protecting the side channel security of the CPU chip.
[0021] 1. Data Preparation
[0022] 1. Separation
[0023] The power consumption curve of the chip when working is also called the energy trace.
[0024] For an instruction C, let the CPU execute the instruction (at this time the protection device is closed or not installed), measure the energy trace brought by instruction C at this time, that is, the actual power consumption curve. Execute C multiple times and measure the energy trace, and then align the time to obtain the average curve, which is the average energy trace. For convenience, the power consumption value can be expressed in voltage / current / temperature / instantaneous power, etc.
[0025] For instructions A and B, take the average energy trace, and assume that the functions of their power consumption values to time are f(t) and g(t) respectively. The time value after the curves are aligned is t1~t2, and the separation degree between the two is defined as:
[0026]
[0027] Among them, M f , M g , m f , m g They are respectively the maximum value of f(t), the maximum value of g(t), the minimum value of f(t), and the minimum value of g(t) in the interval (t1, t2).
[0028] For instructions C1, C2, C3, ...C n , the separations (except one instruction and itself) are all measured, a total of n 2 Separation value. Instruction C i Sort the instructions by degree of separation from the rest, take the names of the three largest instructions, and record them as alternative instructions for this instruction.
[0029] 2. Active modules
[0030] The CPU chip has different working modules when it is working, and different instructions activate / enable different modules. Suppose the CPU chip has functional modules M1, M2, ...M n For each instruction, the corresponding k (k≤n) active modules are identified in advance, and the remaining (nk) are inactive modules.
[0031] 2. T Interference Module
[0032] 1) Separation characteristic table
[0033] For different actual execution instructions, a table is provided recording three alternative instructions for each actual execution instruction and their separation degrees.
[0034] 2) Random Number Generator
[0035] Generate a uniformly distributed random number r in the interval [a, b].
[0036] 3) Instruction content register
[0037] Record the content of the currently executed instruction.
[0038] 4) Random Instruction Picker
[0039] Taking the separation degree between the backup instruction and the actual execution instruction as the weight (relative proportion), the interval [a, b] is divided into 3 parts, and the backup instruction is selected as the final interference instruction according to the specific position where the random number r falls.
[0040] 3. M Interference Module
[0041] 1) Active module identification table
[0042] A table that records the active modules corresponding to different actual execution instructions.
[0043] 2) Parameter source identifier
[0044] For the actual execution instructions (protected instructions), identify the source of the parameters and distinguish whether the source is internal or external to the CPU. Immediate values, registers, and CPU cache are internal parameters, and ports, memory, and disks are external parameters. Similarly, identify the source of the parameters required for the interference instructions.
[0045] 3) Module input generator
[0046] Obtain data from the parameter source identifier. For interference instructions, for parameters from internal sources, directly obtain the internal parameters of the actual execution instruction and invert them bit by bit as the internal parameters of the interference instruction. For parameters from external sources, if they also exist in the external parameters of the actual execution instruction, directly obtain them and keep the values unchanged. If they do not exist in the external parameters of the actual execution instruction, replace them with random numbers. Thus, a complete interference instruction with parameters is generated.
[0047] 4) Mirror function module
[0048] The image of the actual functional module of the CPU (such as ALU, etc., but excluding IO and storage modules). Multiple functional modules each have one image.
[0049] The active module that actually executes the instruction is identified, and its corresponding mirror function module enable signal is set to be inactive. Conversely, the mirror function module enable signal of the inactive module that actually executes the instruction is set to be active.
[0050] The parameters from the instructions required by the mirror function module are provided by the interference instructions, and the contents from the IO and storage modules required by the mirror function module are directly obtained from the actual IO and storage modules.
[0051] 5) Idle signal receiving module
[0052] The internal structure of the mirror function module is exactly the same as the actual function module to be protected, so it must have multiple output pins. All the output pins of the mirror function module are connected to resistors and capacitors in sequence, and then connected in parallel, and connected to a protection resistor and the ground terminal.
[0053] A CPU chip is provided with a protection module for generating power consumption interference instructions. The protection module comprises a T interference module, an M interference module and an idle signal receiving module.
[0054] The T interference module includes a separation characteristic table, a random number generator, an instruction content register and a random instruction selector.
[0055] The M interference module includes an active module discrimination table, a parameter source identifier, a module input generator, and a mirror function module.
[0056] The idle signal receiving module consists of three parts: output resistor, output capacitor and protection resistor.
[0057] All output pins of the mirror function module are connected to an equal value resistor, which is the output resistor of the idle signal receiving module; these output resistors are all connected in parallel and connected to a capacitor, which is the output capacitor; the other side of the output capacitor is grounded after passing through another protection resistor. The idle signal receiving module and the T interference module and the M interference module are all inside the CPU chip shell and are electromagnetically shielded by the metal shell.
Claims
1. A CPU chip that is resistant to power consumption side channel attacks based on energy trace balance, characterized by: It includes a protection module for generating power consumption interference instructions, and the protection module includes a T interference module and an M interference module; The T interference module includes a separation characteristic table, a random number generator, an instruction content register and a random instruction selector; the separation characteristic table is used to record the alternative instructions of each actually executed instruction and the separation degree between the actually executed instruction and L alternative instructions, the random number generator generates a random number r, which falls on the interval [a, b]; the instruction content register records the content of the current actually executed instruction; the random instruction selector uses the separation degree of the alternative instruction and the actually executed instruction as a weight, divides the interval [a, b] into L parts, and selects the alternative instructions of the same order as the final interference instructions according to the order in which the random number r falls on the interval; The M interference module includes an active module identification table, a parameter source identifier, a module input generator and a mirror function module; the active module identification table records the active modules corresponding to different actual execution instructions, the parameter source identifier identifies the parameter source of the actual execution instruction, and distinguishes whether the source is inside or outside the CPU; identifies the parameter source required by the interference instruction, and distinguishes whether the source is inside or outside the CPU; the module input generator obtains data from the parameter source identifier, and for the interference instruction, for the parameters of the internal source, directly obtains the internal parameters of the actual execution instruction and inverts them bit by bit as the internal parameters of the interference instruction; for the parameters of the external source, if they also exist in the external parameters of the actual execution instruction, they are directly obtained and the values remain unchanged; if they do not exist in the external parameters of the actual execution instruction, they are replaced by random numbers; thereby, a complete interference instruction with parameters is generated; the mirror function module identifies the active module and the inactive module of the actual execution instruction, sets the mirror function module enable signal corresponding to the active module to inactive, and sets the mirror function module enable signal corresponding to the inactive module to active, the parameters from the instruction required by the mirror function module are provided by the interference instruction, and the content from the IO and storage modules required by the mirror function module is directly obtained from the IO and storage modules.
2. The CPU chip against power consumption side channel attacks based on energy trace balance according to claim 1 is characterized in that: The protection module also includes an idle signal receiving module, which includes an output resistor, an output capacitor and a protection resistor. All output pins of the mirror function module are connected to the output resistor. All output resistors are connected in parallel and connected to an output capacitor. The other side of the output capacitor is grounded after passing through another protection resistor.
3. The CPU chip against power consumption side channel attacks based on energy trace balance according to claim 1 or 2, characterized in that: The idle signal receiving module, the T interference module and the M interference module are all arranged in the CPU chip housing and are electromagnetically shielded by the metal housing.