Display driving circuit, display module and electronic equipment

Abstract

The invention provides a display driving circuit, a display module and electronic equipment. The display driving circuit comprises a signal control module, an output switch circuit and a source electrode output circuit. When the signal control module compares the current frame display data and the previous frame display data corresponding to the same display position in the display screen to be different, a first switching signal is output and provided for the switching control end of the output switching circuit; and the output switch circuit controls the first switch branch to be switched off and the second switch branch to be switched on according to the first switch signal, so that the output switch circuit outputs a negative voltage signal, and the negative voltage signal is output after being processed by the source electrode output circuit. Therefore, according to the scheme, for the display pixel with the display content needing to be updated, the output switch circuit of the DDIC outputs the preset negative voltage, and the source output circuit amplifies the driving capability of the preset negative voltage signal and then outputs the signal, namely, source output. The voltage range of the source output output by the DDIC comprises the preset negative voltage signal, so that the DDIC is suitable for an OLED local refreshing scene, and the application range of the DDIC is expanded.

Description

Technical Field

[0001] The present application relates to the field of terminal technology, and in particular to a display driving circuit, a display module and an electronic device. Background Art

[0002] The display driver integration chip (DDIC) is one of the main control components of the display panel, which sends driving signals and data to the display panel in the form of electrical signals, so that the display panel displays corresponding content.

[0003] At present, the source output voltage range of the driver IC of the organic light-emitting diode (OLED) to control the grayscale display of the pixel is positive voltage, but in some special usage scenarios of OLED (such as partial refresh), the DDIC needs to output a set negative voltage at a specific time. The source output voltage range of the driver IC of OLED does not include negative voltage, thus limiting the use of OLED in special scenarios. Summary of the invention

[0004] In view of this, the present application provides a display driving circuit, a display module and an electronic device to solve the problem that DDIC cannot output a negative voltage. The disclosed technical solution is as follows:

[0005] In the first aspect, the present application provides a display driving circuit for controlling the display pixels of OLED, the display driving circuit comprising: a signal control module, an output switch circuit and a source output circuit; the output switch circuit comprises an input terminal, a switch control terminal, an output terminal, a first switch branch and a second switch branch, the first switch branch is connected between the input terminal and the output terminal, the second switch branch is connected between the output terminal and the negative reference voltage source, and the switch control terminal is respectively connected to the control terminals of the first switch branch and the second switch branch; when the signal control module compares the current frame display data and the previous frame display data corresponding to the same display position in the display screen, the first switch signal is output and provided to the switch control terminal of the output switch circuit; the output switch circuit controls the first switch branch to turn off and the second switch branch to turn on according to the first switch signal, so that the output switch circuit outputs a negative voltage signal, and the negative voltage signal is processed by the source output circuit and then output. It can be seen that in this scheme, for display pixels whose display content needs to be updated, the switch control terminal of the output switch circuit of the DDIC inputs the first switch signal, and at this time, the output switch circuit outputs a preset negative voltage and transmits it to the source output circuit. The source output circuit increases the driving capability of the received preset negative voltage signal and then outputs a write data trigger signal (i.e., the preset negative voltage after the driving capability is increased), thereby triggering the OLED to receive the data signal. That is, the voltage range of the source output of the DDIC includes the preset negative voltage signal, so that the DDIC is suitable for the OLED partial refresh scenario, which expands the scope of application of the DDIC.

[0006] In a possible implementation, when the signal control module compares the current frame display data corresponding to the same display position in the display screen and the previous frame display data, the second switch signal is output and provided to the switch control end of the output switch circuit; the output switch circuit controls the first switch branch to be turned on and the geothermal switch branch to be turned off according to the second switch signal, so that the output end of the output switch circuit outputs the signal input by the input end, and the level of the second switch signal is opposite to that of the first switch signal. It can be seen that for display pixels whose display content does not need to be updated, the switch control end of the output switch circuit inputs the second switch signal. At this time, the output end of the output switch circuit follows the input end, that is, the output signal of the output switch circuit is the signal input by the input end. DDIC will not output a write data trigger signal, and therefore will not trigger the OLED to receive a data signal.

[0007] In one possible implementation, the signal control module includes a digital signal control circuit and a signal digital-to-analog conversion circuit; the digital signal control circuit compares whether the current frame display data and the previous frame display data corresponding to the same display position in the display screen are the same, generates a switch signal corresponding to the comparison result and transmits it to the signal digital-to-analog conversion circuit; the signal digital-to-analog conversion circuit converts the switch signal into an analog signal and transmits it to the output switch circuit.

[0008] In a possible implementation, an output switch circuit is configured for each column of display pixels of the OLED screen.

[0009] In a possible implementation, the output switch circuit includes a first switch tube, a second switch tube and a third switch tube; the first end of the first switch tube is connected to the input end of the output switch circuit, the second end is connected to the output end of the output switch circuit, the control end is connected to the second end of the second switch tube, and the control end also inputs a first voltage, the first voltage is a high level voltage; the first end of the second switch tube inputs a second voltage, the control end is connected to the switch control end of the output switch circuit, and the second voltage is a low level voltage or a negative voltage; the first end of the third switch tube is connected to the output end of the output switch circuit, the second end inputs a preset negative voltage, and the control end is connected to the switch control end. It can be seen that the output switch circuit in this implementation has high stability, thereby improving the stability of the DDIC.

[0010] In a possible implementation, the first switch tube, the second switch tube, and the third switch tube are all NMOS tubes, the first end is a drain, the second end is a source, and the control end is a gate.

[0011] In a possible implementation, the output switch circuit includes a fourth switch tube, a fifth switch tube and a sixth switch tube; the first end of the fourth switch tube is connected to the input end of the output switch circuit, the second end is connected to the output end of the output switch circuit, and the control end is connected to the switch control end of the output switch circuit; the first end of the fifth switch tube inputs the second voltage, and the second end inputs the first voltage, the first voltage is a high-level voltage, and the second voltage is a low-level voltage or a negative voltage; the first end of the sixth switch tube is connected to the output end of the output switch circuit, the second end inputs a preset negative voltage, and the control end inputs the first voltage.

[0012] In a possible implementation, the fourth switch tube, the fifth switch tube, and the sixth switch tube are all NMOS tubes, the first end is a drain, the second end is a source, and the control end is a gate.

[0013] In a possible implementation manner, the first switch signal is a high level signal.

[0014] In a possible implementation, the output switch circuit includes a seventh switch tube and an eighth switch tube; the first end of the seventh switch tube is the input end of the output switch circuit, the second end is the output end of the output switch circuit, and the control end is the switch control end of the output switch circuit; the first end of the eighth switch tube is connected to the output end of the output switch circuit, the second end inputs a preset negative voltage, and the control end is connected to the switch control end. It can be seen that the output switch circuit in this implementation is simple in structure, simple in control, and has low hardware cost.

[0015] In a possible implementation, the seventh switch tube is an NMOS tube, the first end of the seventh switch tube is the drain of the NMOS tube, the second end is the source, and the control end is the gate; the eighth switch tube is a PMOS tube, the first end of the eighth switch tube is the drain of the PMOS tube, the second end is the source, and the control end is the gate.

[0016] In a possible implementation manner, the first switch signal is a low level signal.

[0017] In a second aspect, the present application further provides a display module, comprising: a display screen and a display driving circuit according to any one of the first aspects.

[0018] In a third aspect, the present application also provides an electronic device, comprising: one or more processors, a memory, a touch screen and a display driver circuit of any one of the first aspects; the memory is used to store program code; the processor is used to run the program code so that the display driver circuit drives the touch screen to update the display content.

[0019] It should be understood that the description of technical features, technical solutions, beneficial effects or similar language in this application does not imply that all features and advantages can be realized in any single embodiment. On the contrary, it is understood that the description of features or beneficial effects means that specific technical features, technical solutions or beneficial effects are included in at least one embodiment. Therefore, the description of technical features, technical solutions or beneficial effects in this specification does not necessarily refer to the same embodiment. Furthermore, the technical features, technical solutions and beneficial effects described in the present embodiment can also be combined in any appropriate manner. Those skilled in the art will understand that the embodiment can be realized without one or more specific technical features, technical solutions or beneficial effects of a specific embodiment. In other embodiments, additional technical features and beneficial effects can also be identified in a specific embodiment that does not embody all embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0022] Figure 2 is a schematic diagram of a pixel array of a display screen;

[0023] Figure 3is a schematic diagram of the structure of a display driver chip provided in an embodiment of the present application;

[0024] Figure 4 is a circuit diagram of an output switch circuit provided in an embodiment of the present application;

[0025] Figure 5 The embodiment of this application provides Figure 3 Schematic diagram of waveforms of various signals in the output switch circuit shown;

[0026] Figure 6 is a circuit diagram of another output switch circuit provided in an embodiment of the present application;

[0027] Figure 7 is a circuit diagram of another output switch circuit provided in an embodiment of the present application;

[0028] Figure 8 The embodiment of this application provides Figure 6 Schematic diagram of the voltage signal waveform corresponding to the output switching circuit shown. DETAILED DESCRIPTION

[0029] The terms "first", "second", "third", etc. in the specification, claims and drawings of this application are used to distinguish different objects rather than to limit a specific order.

[0030] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0031] See also Figure 1 , shows a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device can be a device in any form including a display screen, such as a mobile phone, a tablet computer, a desktop, a laptop, a notebook computer, an ultra-mobile personal computer (UMPC), a handheld computer, a netbook, a personal digital assistant (PDA), a wearable electronic device, a smart watch, and other devices.

[0032] The electronic device includes a processor, a memory, a display driver chip (DDIC) and a display screen. The processor can also be called a system on chip (SoC).

[0033] It is to be understood that the structure illustrated in this embodiment does not constitute a specific limitation on the electronic device. In other embodiments, the electronic device may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0034] like Figure 1 As shown, the processor is connected to the DDIC and the memory. The processor may include one or more processing units. Different processing units may be independent devices or integrated into one or more processors.

[0035] A memory may also be provided in the processor for storing instructions and data. In some embodiments, the memory in the processor is a cache memory. The memory may store instructions or data that the processor has just used or is cyclically used. If the processor needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor, and thus improves the efficiency of the system.

[0036] A memory may also be provided in the processor for storing instructions and data. In some embodiments, the memory in the processor is a high-speed cache memory.

[0037] like Figure 1 As shown, the TE pin of the DDIC is connected to the processor. At the same time, both the processor and the DDIC are provided with a display serial interface (DSI). The DSI of the processor and the DSI of the DDIC are connected via a mobile industry processor interface (MIPI) bus.

[0038] The memory can be used to store computer executable program codes, which include instructions. The processor executes various functional applications and data processing of the electronic device by running the instructions stored in the memory.

[0039] The memory may include a program storage area and a data storage area. The program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data (such as audio data, etc.) created during the use of the electronic device, etc. The processor executes various functional applications and data processing of the mobile terminal by running instructions stored in the memory and / or instructions stored in the memory provided in the processor.

[0040] The display driver chip DDIC is connected to the display screen. Exemplarily, the DDIC can be integrated with the display screen into one device, for example, it can be fixed on the back of the display screen. After the display screen is turned on, the DDIC notifies the processor of the refresh rate through the TE pin, and the processor generates image data in real time according to the received refresh rate (for example, 60Hz) and sends it to the DDIC through the MIPI bus. The DDIC controls the display screen to display the corresponding image according to the image data. For example, the processor generates image data representing the system desktop and sends it to the DDIC, and the DDIC controls the display screen to display the system desktop according to the image data.

[0041] See also Figure 2 , showing a schematic diagram of a pixel array of a display screen.

[0042] like Figure 2 As shown, the OLED screen includes a pixel array, which is an effective display area of ​​the display screen for displaying content. For example, a typical distribution of the pixel array is an array of 1920*1080 pixels. Figure 2 Only a 10×7 pixel array is used as an example.

[0043] The OLED screen also includes a pixel driving circuit and an array driving circuit. The array driving circuit includes a row scanning driving circuit and a column driving circuit, wherein the row scanning driving circuit provides a row scanning signal to the pixel driving circuit. The column driving circuit provides a data signal to the pixel driving circuit. The row scanning signal converts the serial bus clock signal output by the DDIC into a sequential write pulse with driving capability. The data signal is linearly written into the pixel circuit under the drive of the row scanning signal, thereby realizing the content refresh of the entire screen.

[0044] Each pixel in the pixel array includes three organic light emitting diodes, red, green and blue, namely RedOLED, GreenOLED and BlueOLED. Each OLED is coupled to a pixel driving circuit. Each pixel driving circuit is input with a row scanning signal and a data signal. The pixel driving circuit drives the OLED to emit light and adjust the brightness based on the row scanning signal and the data signal.

[0045] DDIC drives the OLED screen to display corresponding content according to the display data and update instructions output by the processor (also called SOC).

[0046] See also Figure 3 , shows a schematic structural diagram of a display driver chip provided in an embodiment of the present application.

[0047] like Figure 3As shown, the display driver chip includes a data / command interface, a data control module, a command decoding module, an update address management module, a data storage module, a digital signal control circuit (digital control circuit), a data latch circuit, a data digital-to-analog conversion circuit, a signal digital-to-analog conversion circuit, an output switch circuit and a source output circuit (sourceoutput).

[0048] Understandably, Figure 3 The structure illustrated in this embodiment does not constitute a specific limitation on DDIC. In other embodiments, DDIC may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0049] like Figure 3 As shown, the input end of the data / command interface is connected to the processor via the MIPI bus, the data output end of the data / command interface is connected to the data control module, and the signal output end of the data / command interface is connected to the input end of the command decoding module. The data / command interface receives display data and / or refresh instructions sent by the processor. Further, the data / command interface transmits the received display data to the data control module, and transmits the received update instructions to the command decoding module.

[0050] The output end of the data control module is connected to the data input end of the data storage module. The data control module processes the received display data accordingly and transmits it to the data storage module for storage. Exemplarily, the data storage module (also referred to as display RAM) can be a random access memory (RAM), and the received display data is stored in the corresponding storage space in the RAM.

[0051] The first output end of the instruction decoding module is connected to the input end of the update address management module, and the second output end is connected to the digital signal control circuit. The instruction decoding module decodes the received update instruction and transmits it to the digital signal control circuit. At the same time, the content update address obtained by parsing the update instruction is transmitted to the update address management module for management. The content update address is the position coordinate corresponding to the position on the display screen where the content needs to be updated.

[0052] The output of the data control module is connected to the first input of the data storage module, the output of the update address management module is connected to the second input of the data storage module, and the output of the data storage module is connected to the first input of the digital signal control circuit. The data storage module is used to store display data and content update addresses.

[0053] The second input end of the digital signal control circuit is connected to the instruction decoding module, the first output end is connected to the input end of the data latch circuit, and the second output end is connected to the input end of the signal digital-to-analog conversion circuit. The digital signal control circuit is used to compare whether the current frame display data corresponding to the same position on the display screen is the same as the previous frame display data. If they are the same, it indicates that the display content of the position does not need to be updated, and the second switch signal is output and transmitted to the signal digital-to-analog conversion circuit. If they are not the same, it indicates that the display content of the position needs to be updated, and the current frame display data of the position is output to the data latch circuit, and at the same time, the first switch signal is output and transmitted to the signal digital-to-analog conversion circuit.

[0054] In a possible implementation, a digital signal control circuit is configured for each column of pixels in the pixel array, and the digital signal control circuit corresponding to each column is used to compare whether the two frames of display data corresponding to the column and the current scanning row are the same. Figure 2 The pixel array shown includes 7 columns, and 7 digital signal control circuits are arranged in the DDIC, that is, each column of display pixels corresponds to a digital signal control circuit, and each digital signal control circuit compares the display content of each row of display pixels in the column one by one to see if there is any change.

[0055] For example, Figure 2 In the pixel array shown, taking the display pixels in the first column as an example, the digital signal control circuit corresponding to the display pixels in the first column and the first row compares the current frame data and the previous frame data corresponding to the display pixels in the first column and the first row at the first moment. If they are different, the current frame data corresponding to the first column and the first row is transmitted to the data latch circuit corresponding to the column, and the first switch signal is outputted at the same time. The digital signal control circuit compares the current frame data and the previous frame data corresponding to the display pixels in the second row of the first column at the second moment. If they are different, the current frame data corresponding to the second row of the first column is transmitted to the data latch circuit corresponding to the column, and the first switch signal is outputted at the same time. By analogy, the digital control circuit compares the current frame data and the previous frame data corresponding to the display pixels in the Nth row of the first column at the Nth moment. If they are different, the current frame data of the display pixel is latched and the first switch signal is outputted. If they are the same, the second switch signal is outputted.

[0056] In a possible implementation, the data storage module also stores the previous frame display data, so the digital signal control circuit can read the previous frame display data corresponding to the current pixel position from the data storage module, and further compare the previous frame display data with the current frame data.

[0057] In one scenario, the update instruction carries a local update flag. In this scenario, after each digital signal control circuit receives the update instruction carrying the local update flag transmitted by the instruction decoding module, it is necessary to compare the current frame data and the previous frame data of each display pixel corresponding to each row of the current column, until all display pixels in the entire column are compared to obtain the display position of the column that needs to be updated.

[0058] In another scenario, the update instruction carries a local update flag and an update position. In this scenario, after the digital signal control circuit receives the update instruction transmitted by the instruction decoding module, it obtains the update position. Further, the digital signal control circuit corresponding to the update position compares the current frame data with the previous frame data. If the two frames of display data corresponding to the position are indeed different, the current frame display data corresponding to the position is transmitted to the data latch circuit for latching, and the first switch signal is transmitted to the output switch circuit.

[0059] In a possible implementation, the digital signal control circuit may read the previous frame display data corresponding to the update position from the display RAM according to the update position, and further compare whether the previous frame display data corresponding to the update position is the same as the current frame display data.

[0060] In another scenario, the update instruction does not carry a local update flag. The processing process of the digital signal control circuit in this scenario is the same as that in the scenario where the update instruction carries an update flag but does not include an update position, and will not be repeated here.

[0061] The output end of the data latch circuit is connected to the input end of the data digital-to-analog conversion circuit. The data latch circuit receives the current frame display data (digital signal) transmitted by the digital signal control circuit and transmits it to the data digital-to-analog conversion circuit. In an embodiment of the present application, the data latch circuit includes a plurality of data latches, one data latch corresponds to a column of display pixels in the screen, and each data latch is used to latch the display data corresponding to this position at the current moment. When the display data of this position at the next moment is received, the data in the data latch is updated to the newly received display data.

[0062] The output end of the data digital-to-analog conversion circuit is connected to the input end input of the output switch circuit. The data digital-to-analog conversion circuit converts the current frame display data from a digital signal to an analog signal and transmits it to the input end input of the output switch circuit.

[0063] The output end of the signal digital-to-analog conversion circuit is connected to the switch control end switch of the output switch circuit. The signal digital-to-analog conversion circuit is used to convert the digital switch signal transmitted by the digital signal control circuit into an analog switch signal and transmit it to the switch control end switch of the output switch circuit.

[0064] The output switch circuit controls the output of the corresponding signal at the output terminal output according to the switch signal (also called switch signal) inputted from the switch control terminal. If the switch signal is the first switch signal, a preset negative voltage is outputted. If the switch signal is the second switch signal, the signal outputted from the output terminal is the signal inputted from the input terminal input, that is, the output terminal of the output switch circuit follows the input terminal.

[0065] In a possible implementation, an output switch circuit is provided for each column of pixels in the pixel array, that is, one column of display pixels corresponds to one output switch circuit, the pixel array includes N columns of pixels, and N output switch circuits are configured in the corresponding DDIC, and each output switch circuit is responsible for output control of the data signal or the preset negative voltage signal (i.e., the negative reference voltage Vref) of the pixels in the column. For example, when there are display pixels in the column that need to be partially refreshed, the output switch circuit first outputs the preset negative voltage signal and then outputs the data signal corresponding to the display pixel.

[0066] The input end of the source output circuit is connected to the output end output of the output switch circuit, and the output end of the source output circuit is the source output of the DDIC. The source output is used to control the gray scale of the display pixel, that is, the voltage signal used to control the gray scale of the display.

[0067] Grayscale refers to the number of gray levels represented by each pixel in the image. Specifically, each pixel on the display is composed of OLEDs of the three primary colors of red, green, and blue, and the light source behind each primary color can show different brightness levels. Grayscale represents the different levels of brightness from the darkest to the brightest. The level of change in each of the three primary colors from pure color to black is divided into the grayscale of the color.

[0068] In one embodiment, the source output circuit may be a voltage follower, that is, the output voltage of the source output circuit is the same as the input voltage, but the output current is greater than the input current, that is, the source output circuit is used to improve the driving capability of the output signal.

[0069] When the output switch circuit outputs a preset negative voltage, the source output circuit amplifies the current of the preset negative voltage signal to improve the driving capability of the signal. When the output switch circuit outputs a display data analog signal, the output end of the source output circuit outputs the display data analog signal with amplified driving capability.

[0070] The display driver chip provided by the embodiment of the present application, in the scenario where the local content of the display screen needs to be updated (i.e., local update), for the display pixels whose display content needs to be updated, the switch control end of the output switch circuit of the DDIC inputs a first switch signal, and at this time the output switch circuit outputs a preset negative voltage and transmits it to the source output circuit. The source output circuit outputs a write data trigger signal (i.e., the preset negative voltage after the driving capability is increased) after the driving capability method of the received preset negative voltage signal, thereby triggering the OLED to receive the data signal. For the display pixels whose display content does not need to be updated, the switch control end of the output switch circuit inputs a second switch signal, and at this time the output end of the output switch circuit follows the input end, that is, the output signal of the output switch circuit is the signal input by the input end. The DDIC will not output a write data trigger signal, and therefore will not trigger the OLED to receive the data signal. It can be seen that the voltage range of the source output output of the DDIC provided by the present application includes a preset negative voltage signal, so that the DDIC is suitable for the OLED local refresh scenario, which expands the scope of application of the DDIC.

[0071] See also Figure 4-Figure 5 , Figure 4 A circuit diagram of an output switch circuit provided in an embodiment of the present application is shown; Figure 5 Shows Figure 4 Schematic diagram of the waveforms of various signals in the output switching circuit shown.

[0072] like Figure 4 As shown, the output switch circuit includes a first switch tube T1, a second switch tube T2, and a third switch tube T3. T1 to T3 in this embodiment are all NMOS tubes. In other embodiments, T1 to T3 can select other types of switch tubes, and this application does not limit the type of switch tube. In addition, each switch tube can be replaced by a structure of at least two switches of the same type connected in series or in parallel, which will not be repeated in this application.

[0073] The drain of T1 is the input terminal of the output switch circuit, the source of T1 is the output terminal of the output switch circuit, the gate of T1 is connected to the source of T2, the drain of T2 is input to VSS, VSS is a low level signal or a negative voltage signal. The gate of T2 is connected to the gate of T3 and serves as the switch control terminal of the output switch circuit.

[0074] The gate of T1 is connected to the voltage source VDD through the resistor R1. In this embodiment, VDD is a high level voltage. The function of the resistor R1 is to limit the current. In this embodiment of the application, the resistance value of the resistor R1 can be determined according to the actual circuit parameters.

[0075] The source of T3 is connected to the output end of the output switch circuit, and the drain of T3 inputs a reference voltage Vref, and Vref is a negative voltage.

[0076] Combine the following Figure 4 and Figure 5 Introduce the working process of the output switching circuit:

[0077] t0-t1 stage: switch is a low-level signal, that is, the gates of T2 and T3 input low-level signals. At this time, T2 and T3 are disconnected, and the gate of T1 inputs VDD, that is, a high-level signal, and T1 is turned on. Since T1 is connected between the input and output ends, when T1 is turned on, the input signal is directly transmitted to the output end, that is, the output end directly outputs the input signal. That is, when switch is low, the output outputs the input signal. Figure 5 As shown, during the t0-t1 phase, the output signal waveform is consistent with the input signal waveform, that is, the output end follows the input end during this phase.

[0078] During the t1-t2 phase, switch is a high-level signal, that is, the gates of T2 and T3 input a high-level signal, and T2 and T3 are turned on. T2 is turned on to transmit VSS to the gate of T1, and VSS is a low-level voltage or a negative voltage, so T1 is turned off. T3 is turned on to transmit the negative voltage Vref to the output terminal output, that is, when switch is a high level, output outputs Vref, that is, a negative voltage. Figure 5 As shown, during the t1-t2 phase, the output signal waveform is a negative voltage.

[0079] During the t2-t4 period, the switch is at a low level, and the input is at a high level during the t2-t3 period and at a low level during the t3-t4 period. As mentioned above, when the switch is at a low level, the output follows the input. Figure 5 As shown, the voltage waveform of the output during the t2-t4 period is consistent with the voltage waveform of the input.

[0080] For example, assume that the time period t1-t4 is Figure 2 In the write data cycle corresponding to the display pixel in the first column and the first row in the pixel array shown, the output switch circuit outputs a preset negative voltage signal (i.e., Vref) during the time t1-t2 of the write data cycle, and outputs the data signal corresponding to the display pixel during the time t2-t4. At the same time, t4 is the start time of the next write data cycle, and this cycle is used to output the data signal corresponding to the display pixel in the first column and the second row. Similarly, the preset negative voltage signal, i.e., Vref, is output during the time t4-t5 of this cycle, and the data signal corresponding to the display pixel is output from t5 to the end of this cycle.

[0081] In addition, for the convenience of drawing, this application uses a pulse signal waveform to illustrate the waveform of the input signal. In practical applications, the voltage range of the input signal is [Vgmp, Vgsp], and different voltage values ​​correspond to different brightness values ​​of the display pixel. The larger the voltage value, the higher the pixel brightness. The values ​​of Vgmp and Vgsp can be determined according to the actual pixels of the display panel, and this application does not limit this.

[0082] The output switch circuit provided by the present application, when the switch control terminal switch inputs a high level, closes the transmission branch between the input terminal and the output terminal, and opens the transmission branch between the negative voltage Vref and the output terminal, so that the output switch circuit outputs the negative voltage Vref. When the switch control terminal switch inputs a low level, the transmission branch between the input terminal and the output terminal is opened, and the transmission branch between the negative voltage Vref and the output terminal is closed, so that the output terminal of the output switch circuit follows the input terminal, that is, the signal input by the input terminal is output. It can be seen that the output switch circuit is arranged in the previous stage of the source output circuit of the DDIC, and the negative voltage output by the output switch circuit is output after the source output circuit amplifies its driving capability, and finally the source output voltage range of the DDIC includes the negative voltage. Thereby, the DDIC is suitable for the local refresh scenario of the OLED, that is, the applicable scenario of the DDIC is expanded.

[0083] See also Figure 6 , shows a circuit diagram of another output switching circuit provided in an embodiment of the present application.

[0084] like Figure 6 As shown, the output switch circuit includes a fourth switch tube T4, a fifth switch tube T5 and a sixth switch tube T6. In this embodiment, T4-T6 are all NMOS tubes. In other embodiments, T4-T6 can select other types of switch tubes, and this application does not limit the type of switch tube. In addition, each switch tube can be replaced by a structure of at least two switches of the same type connected in series or in parallel, which will not be repeated in this application.

[0085] The drain of T4 is the input terminal of the output switch circuit, which inputs display data. The source of T4 is the output terminal of the output switch circuit, and the gate of T1 is the switch control terminal of the output switch circuit, which inputs the switch signal.

[0086] The switch control terminal is also connected to the gate of T5, the drain of T5 is connected to the voltage source VDD via the resistor R2, and the source of T5 is connected to the voltage source VSS.

[0087] In an embodiment of the present application, VDD is a high-level voltage source, and VSS is a low-level or negative voltage source. The function of resistor R2 is to limit the current to prevent T5 from burning due to excessive current flowing through T5. The resistance value of R2 can be determined according to actual circuit parameters.

[0088] The output terminal output is also connected to the source of T6, the gate of T6 is connected to the voltage source VDD via R2, and the drain of T6 inputs the reference voltage Vref, which is a negative voltage.

[0089] The following will be described in detail Figure 6 The working process of the output switching circuit shown:

[0090] When the switch signal is a high-level signal, both T4 and T5 are turned on. When T4 is turned on, the transmission branch between the input and output ends is turned on. After T5 is turned on, the voltage at point A is pulled down to VSS, that is, the gate voltage of T6 is a low level or negative voltage, so T6 is turned off. When T6 is turned off, the transmission branch between the reference voltage Vref and the output is turned off. That is, when a high-level signal is input to the switch end, the output follows the input, that is, the output outputs the signal input to the input end.

[0091] When the switch signal is low, both T4 and T5 are turned off, T4 is turned off and the transmission branch between the input and output ends is turned off. T5 is turned off so that the gate voltage of T6 is VDD, that is, the gate of T6 inputs a high-level signal, and at this time T6 is turned on, that is, the transmission branch between the reference voltage Vref and the output end is turned on. That is, when the switch end inputs a low-level signal, the output end outputs a negative voltage Vref.

[0092] According to the above Figure 6 The working process of the output switch circuit shown in FIG. 1 shows that the waveform diagram of each signal voltage in the output switch circuit is Figure 5 The waveform diagram shown is not described here in detail.

[0093] See also Figure 7 and Figure 8 , Figure 7 A circuit diagram of another output switch circuit provided in an embodiment of the present application is shown; Figure 8 Shows Figure 7 Schematic diagram of the voltage signal waveform corresponding to the output switching circuit shown.

[0094] like Figure 7 As shown, the output switch circuit includes a seventh switch tube T7 and an eighth switch tube T8.

[0095] In this embodiment, T7 is an NMOS tube, and T8 is a PMOS tube. In other embodiments, T7 and T8 can select other types of switch tubes, and this application does not limit the type of switch tube. In addition, each switch tube can be replaced by a structure in which at least two switches of the same type are connected in series or in parallel, which will not be described in detail in this application.

[0096] The drain of T7 is the input terminal of the output switch circuit, the source of T7 is the output terminal of the output switch circuit, and the gate of T7 is the switch control terminal. The drain of T8 inputs the reference voltage Vref, which is a negative voltage. The source of T8 is connected to the output terminal, and the gate of T8 is connected to the switch control terminal.

[0097] Combine the following Figure 7 and Figure 8 The working process of the output switch circuit provided in this embodiment is introduced as follows:

[0098] Phase t0-t1: switch is a high-level signal, that is, the gates of T7 and T8 both input high-level signals. T7 is an NMOS tube, and when the gate is high, T7 is turned on. T8 is a PMOS tube, and when the gate is high, T8 is turned off. T7 is turned on, so that the transmission branch between the input and output ends is turned on, and T8 is turned off, so that the transmission branch between the reference voltage Vref and the output end is disconnected. That is, when the switch inputs a high-level signal, the output follows the input. Figure 8 As shown, the waveform of the output during the time period t0-t1 is consistent with the input.

[0099] Phase t1-t2: switch is a low-level signal, that is, the gates of T7 and T8 are both input with low-level signals, so T7 is turned off and T8 is turned on. T7 is connected between the input and output terminals, so when T7 is turned off, the transmission branch between the input and output terminals is turned off. T8 is connected between Vref and the output terminal, so when T8 is turned on, the transmission branch between Vref and the output terminal is turned on. That is, when switch is a low-level signal, the output outputs the reference voltage Vref, and Vref is a negative voltage. Figure 8 As shown, the output terminal outputs a reference voltage Vref during the time period t1-t2.

[0100] Phase t2-t4: switch is a high level signal. This phase is the same as phase t0-t1. The output follows the input. Figure 8 As shown, the voltage waveform of the output during the t2-t4 period is consistent with that of the input.

[0101] In this embodiment, it is assumed that the time period t1-t4 is Figure 2 In the data writing cycle corresponding to the display pixel in the first column and the first row in the pixel array shown, the output switch circuit outputs a preset negative voltage signal, namely Vref, during the time t1-t2 of the cycle, and outputs the data signal corresponding to the display pixel during the time t2-t4. At the same time, t4 is the start time of the next writing cycle, and the cycle is used to output the data signal corresponding to the display pixel in the first column and the second row. Similarly, the preset negative voltage signal, namely Vref, is output during the time t4-t5 of the cycle, and the data signal corresponding to the display pixel is output from t5 to the end of the cycle.

[0102] like Figure 7 As shown, the output switch circuit provided in this embodiment is arranged in the previous stage of the source output circuit of the DDIC, and the negative voltage output by the output switch circuit is output after the source output circuit amplifies its driving capability, so that the output voltage range of the DDIC output includes negative voltage. Thus, the DDIC is suitable for the OLED partial refresh scenario, that is, the applicable scenarios of the DDIC are expanded. Moreover, the output switch circuit contains fewer switch tubes and does not require voltage sources such as VDD and VSS. It can be seen that the circuit structure and control process of the output switch circuit are simpler. In addition, the small number of devices in the circuit reduces the hardware cost of the output switch circuit.

[0103] Through the description of the above implementation methods, technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device and unit described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0104] In the several embodiments provided in this embodiment, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0105] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0106] In addition, each functional unit in each embodiment of the present embodiment may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0107] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the method described in each embodiment. The aforementioned storage medium includes: flash memory, mobile hard disk, read-only memory, random access memory, disk or optical disk and other media that can store program codes.

[0108] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A display driving circuit, characterized in that: Used to control the display pixels of OLED, the display driving circuit includes: a signal control module, an output switch circuit and a source output circuit; The output switch circuit comprises an input terminal, a switch control terminal, an output terminal, a first switch branch and a second switch branch, wherein the first switch branch is connected between the input terminal and the output terminal, the second switch branch is connected between the output terminal and a negative reference voltage source, and the switch control terminal is connected to the control terminals of the first switch branch and the second switch branch respectively; The signal control module compares the current frame display data and the previous frame display data corresponding to the same display position in the display screen and when they are different, outputs a first switch signal and provides it to the switch control terminal of the output switch circuit; The output switch circuit controls the first switch branch to be turned off and the second switch branch to be turned on according to the first switch signal, so that the output switch circuit outputs a negative voltage signal, and the negative voltage signal is output after being processed by the source output circuit.

2. The display driving circuit according to claim 1, characterized in that: When the signal control module compares the current frame display data corresponding to the same display position in the display screen with the previous frame display data and finds that they are the same, the signal control module outputs a second switch signal and provides it to the switch control terminal of the output switch circuit; The output switch circuit controls the first switch branch to be turned on and the geothermal switch branch to be turned off according to the second switch signal, so that the output end of the output switch circuit outputs the signal input by the input end, and the level of the second switch signal is opposite to that of the first switch signal.

3. The display driving circuit according to claim 1 or 2, characterized in that: The signal control module includes a digital signal control circuit and a signal digital-to-analog conversion circuit; The digital signal control circuit compares whether the current frame display data and the previous frame display data corresponding to the same display position in the display screen are the same, generates a switch signal corresponding to the comparison result and transmits it to the signal digital-to-analog conversion circuit; The signal digital-to-analog conversion circuit converts the switch signal into an analog signal and transmits the analog signal to the output switch circuit.

4. The display driving circuit according to any one of claims 1 to 3, characterized in that: One output switch circuit is configured for each column of display pixels on the OLED screen.

5. The display driving circuit according to any one of claims 1 to 4, characterized in that: The output switch circuit includes a first switch tube, a second switch tube and a third switch tube; The first end of the first switch tube is connected to the input end of the output switch circuit, the second end is connected to the output end of the output switch circuit, the control end is connected to the second end of the second switch tube, and the control end is also input with a first voltage, which is a high level voltage; A second voltage is input to a first terminal of the second switch tube, and a control terminal is connected to a switch control terminal of the output switch circuit, wherein the second voltage is a low level voltage or a negative voltage; The first end of the third switch tube is connected to the output end of the output switch circuit, the second end is input with a preset negative voltage, and the control end is connected to the switch control end.

6. The display driving circuit according to claim 5, characterized in that: The first switch tube, the second switch tube and the third switch tube are all NMOS tubes, the first end is a drain, the second end is a source, and the control end is a gate.

7. The display driving circuit according to any one of claims 1 to 4, characterized in that: The output switch circuit includes a fourth switch tube, a fifth switch tube and a sixth switch tube; The first end of the fourth switch tube is connected to the input end of the output switch circuit, the second end is connected to the output end of the output switch circuit, and the control end is connected to the switch control end of the output switch circuit; The first end of the fifth switch tube inputs a second voltage, and the second end inputs a first voltage, the first voltage is a high level voltage, and the second voltage is a low level voltage or a negative voltage; The first end of the sixth switch tube is connected to the output end of the output switch circuit, the second end is input with a preset negative voltage, and the control end is input with the first voltage.

8. The display driving circuit according to claim 7, characterized in that: The fourth switch tube, the fifth switch tube and the sixth switch tube are all NMOS tubes, the first end is a drain, the second end is a source, and the control end is a gate.

9. The display driving circuit according to any one of claims 5 to 8, characterized in that: The first switch signal is a high level signal.

10. The display driving circuit according to any one of claims 1 to 4, characterized in that: The output switch circuit includes a seventh switch tube and an eighth switch tube; The first end of the seventh switch tube is the input end of the output switch circuit, the second end is the output end of the output switch circuit, and the control end is the switch control end of the output switch circuit; The first end of the eighth switch tube is connected to the output end of the output switch circuit, the second end is input with a preset negative voltage, and the control end is connected to the switch control end.

11. The display driving circuit according to claim 10, characterized in that: The seventh switch tube is an NMOS tube, the first end of the seventh switch tube is the drain of the NMOS tube, the second end is the source, and the control end is the gate; The eighth switch tube is a PMOS tube, the first end of the eighth switch tube is the drain of the PMOS tube, the second end is the source, and the control end is the gate.

12. The display driving circuit according to claim 10 or 11, characterized in that: The first switch signal is a low level signal.

13. A display module, characterized in that: include: A display screen and a display driving circuit as described in any one of claims 1 to 12.

14. An electronic device, characterized in that: The electronic device comprises: one or more processors, a memory, a touch screen and a display driving circuit as described in any one of claims 1-12; the memory is used to store program code; the processor is used to run the program code so that the display driving circuit drives the touch screen to update the display content.

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