Switching converter and control circuit and control method thereof

Abstract

The invention discloses a switching converter and a control circuit and a control method thereof. The control circuit determines the conduction time of a main power tube according to a comparison result between a loop error signal and a preset threshold voltage in a PFM mode, and determines the turn-off time of the main power tube according to a comparison result between a current sampling signal representing an inductive current and the threshold voltage. Therefore, the switching frequency can be adjusted by adjusting the time position of the pulse of the switching signal, the pulse width of the switching signal (namely, the conduction time in the switching period) is constant, and compared with a control scheme in the prior art, the switching converter provided by the embodiment of the invention has the advantages that the switching frequency can be adjusted by adjusting the time position of the pulse of the switching signal no matter the switching converter is in a PWM mode or a PFM mode; and the feedback voltage always fluctuates near the reference voltage, so that the problem that the output voltage is too high in the PFM mode is avoided, and the stability and efficiency of the system are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply, and more specifically, to a switching converter and a control circuit and a control method thereof. Background Art

[0002] In recent years, with the rise of various battery-powered wearable devices and IoT devices, more requirements have been put forward for power chips, requiring power chips to have higher efficiency and achieve longer battery life. For example, in wearable devices, sensor devices are less in working time, and the system is more often under light load or even no load. Therefore, such devices pay special attention to efficiency under extreme light load, which directly affects the battery life of the device.

[0003] DCDC converters are usually used as common power supply devices in such electronic products. DCDC products have high conversion efficiency and are controlled by PWM (Pulse Width Modulation). The PWM control method has the advantages of fixed operating frequency, small output voltage ripple, good stability, and mature control. However, since the power tube in the converter must be turned on and off in each switching cycle, the switching loss of the power tube is large, and the overall efficiency of the converter is low when light load or standby, which seriously limits the application scope of the PWM control method.

[0004] In the prior art, PFM (Pulse Frequency Modulation) control mode and PSM (Pulse PSM Modulation) control mode are usually used to prevent the working efficiency of the DCDC converter from decreasing when the load changes from heavy to light. The essence of the PFM control mode and the PSM control mode is to reduce the actual switching frequency, thereby improving the light load working efficiency.

[0005] In existing technologies, DCDC products with PWM / PSM or PWM / PFM mixed working modes are used in power management technology for systems and electronic devices with a wide working range and constant changes between light load and heavy load, in order to improve efficiency and circuit performance under light and heavy load. However, there are still many problems to be solved in the current mode control method. Figure 1As shown, the existing peak current mode DCDC converter usually uses the peak current of the fixed inductor when lightly loaded, and uses the comparison result of the feedback voltage Vfb and the reference voltage Vref2 to determine whether to turn on the main power tube Q1, thereby adjusting the operating frequency of the system. However, since the voltage value of the reference voltage Vref2 needs to be greater than the voltage value of the reference voltage Vref1, the output voltage of the DCDC converter is relatively high in the PFM mode, so that when the DCDC converter switches between the PWM mode and the PFM mode, the output voltage fluctuates greatly, which increases the output ripple of the circuit and reduces the system stability and efficiency. Summary of the invention

[0006] In view of the above problems, an object of the present invention is to provide a switching converter and a control circuit and a control method thereof, which improve the problem of high output voltage of the traditional switching converter in PFM mode and are beneficial to improving system stability and efficiency.

[0007] According to one aspect of the present invention, a control circuit for a switching converter is provided, wherein the switching converter includes a main power tube, wherein the control circuit includes: an error amplifier, used to compare a feedback voltage of an output voltage of the switching converter with a reference voltage to generate a loop error signal; a mode comparator, used to compare the loop error signal with one of a first threshold voltage and a second threshold voltage to generate a mode control signal; a ripple comparator, used to compare the loop error signal with a third threshold voltage to generate a ripple control signal; a peak comparator, used to compare a current sampling signal related to an inductor current of the switching converter with the loop error signal or the first threshold voltage according to the mode control signal to generate a peak control signal; and a logic circuit, used to generate a switching signal according to the mode control signal, the ripple control signal, the peak control signal and a clock signal, The switching signal is used to control the on or off of the main power tube, wherein, when the mode control signal is valid, the peak comparator generates the peak control signal according to the comparison result of the current sampling signal and the third threshold voltage, and the logic circuit controls the on time of the main power tube in each switching cycle according to the ripple control signal, and controls the off time of the main power tube in each switching cycle according to the peak control signal, so as to control the switching converter to operate in the first mode, and when the mode control signal is invalid, the peak comparator generates the peak control signal according to the comparison result of the current sampling signal and the loop error signal, and the logic circuit controls the on time of the main power tube in each switching cycle according to the clock signal, and controls the off time of the main power tube in each switching cycle according to the peak control signal, so as to control the switching converter to operate in the second mode.

[0008] Optionally, the first mode is a pulse frequency modulation mode, and the second mode is a pulse width modulation mode.

[0009] Optionally, a voltage value of the third threshold voltage is greater than a voltage value of the first threshold voltage, and less than a voltage value of the second threshold voltage.

[0010] Optionally, the mode comparator has a positive input terminal, a negative input terminal and an output terminal, the negative input terminal of the mode comparator is used to receive the loop error signal, and the control circuit also includes: a first switch, used to provide the first threshold voltage to the positive input terminal of the mode comparator when the mode control signal is invalid, and to provide the second threshold voltage to the positive input terminal of the mode comparator when the mode control signal is valid.

[0011] Optionally, the switching converter also includes a synchronous rectifier tube that is turned on non-overlappingly with the main power tube, and the control circuit also includes: a zero-crossing detection circuit, which is used to generate a zero-crossing detection signal when the inductor current passes through zero, and the logic circuit is also used to control the shutdown time of the rectifier tube in each switching cycle according to the zero-crossing detection signal.

[0012] Optionally, the logic circuit includes: a first latch, whose set end is used to receive the inverted signal of the peak control signal, and whose output end is used to output a first switching signal through a first inverter, wherein the first switching signal is used to control the on or off of the main power tube; a first logic module, which is used to provide a logic signal related to the clock signal to the reset end of the first latch when the mode control signal is invalid, and to provide a logic signal related to the wave control signal to the reset end of the first latch when the mode control signal is valid; a second latch, whose reset end is connected to the output end of the first latch, and whose set end is used to receive the inverted signal of the zero-crossing detection signal; and a second logic module, which is used to provide a second switching signal according to the outputs of the first latch and the second latch, wherein the second switching signal is used to control the on or off of the synchronous rectifier tube.

[0013] Optionally, the first logic module includes: a first NAND gate, whose first input end is used to receive the mode control signal, and whose second input end is used to receive the waving control signal; a second NAND gate, whose first input end receives the waving control signal via a second inverter, and whose second input end is used to receive the mode control signal; a third NAND gate, whose first input end is connected to the output end of the second NAND gate, and whose second input end is used to receive the clock signal; a first NOR gate, whose first input end is connected to the output end of the first NAND gate via a third inverter, whose second input end is connected to the output end of the third NAND gate via a fourth inverter, and whose output end is connected to the reset end of the first latch, and the second logic module includes: a fifth inverter, whose input end is connected to the output end of the second latch; a fourth NAND gate, whose first input end is connected to the output end of the first latch, and whose second input end is connected to the output end of the fifth inverter; and a sixth inverter, whose input end is connected to the output end of the fourth NAND gate, and whose output end is used to provide the second switch signal.

[0014] Optionally, the control circuit also includes: an adaptive compensation circuit connected to the output end of the error amplifier, for providing frequency compensation to the loop error signal according to the mode control signal, wherein the adaptive compensation circuit includes: a first compensation resistor, a second compensation resistor and a compensation capacitor connected in series between the output end of the error amplifier and a reference ground; and a second switch connected in parallel between the two ends of the second compensation resistor, the second switch being used to be disconnected when the mode control signal is valid, and to be turned on when the mode control signal is invalid.

[0015] According to another aspect of the present invention, a control method for a switching converter is provided, the switching converter comprising a main power tube, the control method comprising: comparing a feedback voltage of an output voltage of the switching converter with a reference voltage to generate a loop error signal; comparing the loop error signal with one of a first threshold voltage and a second threshold voltage to generate a mode control signal; when the mode control signal is valid, controlling the turn-on time of the main power tube in each switching cycle according to a comparison result between the loop error signal and a third threshold voltage, and controlling the turn-off time of the main power tube in each switching cycle according to a comparison result between a current sampling signal related to an inductor current and the third threshold voltage, so as to control the switching converter to operate in a pulse frequency modulation mode; and when the mode control signal is invalid, controlling the turn-on time of the main power tube in each switching cycle according to a clock signal, and controlling the turn-off time of the main power tube in each switching cycle according to a comparison result between the current sampling signal and the loop error signal, so as to control the switching converter to operate in a pulse width modulation mode.

[0016] According to another aspect of the present invention, there is provided a switching converter, comprising: a power circuit, comprising a main power tube, a synchronous rectifier tube and an inductor; and the control circuit, wherein the control circuit converts an input voltage into an output voltage by repeatedly turning on / off the main power tube and the synchronous rectifier tube alternately and utilizing the inductor to perform energy conversion.

[0017] In summary, the switching converter and its control circuit and control method according to the embodiment of the present invention determine the timing of turning on the main power tube according to the comparison result between the loop error signal and the preset threshold voltage in the PFM mode, and determine the timing of turning off the main power tube according to the comparison result between the current sampling signal representing the inductor current and the threshold voltage, so that the switching frequency can be adjusted by adjusting the time position of the pulse of the switching signal, and the pulse width of the switching signal (that is, the conduction time in the switching cycle) is constant. Compared with the control scheme of the prior art, the feedback voltage of the switching converter according to the embodiment of the present invention always fluctuates around the reference voltage regardless of whether it is in the PWM mode or the PFM mode, so the problem of high output voltage in the PFM mode will not occur, which is beneficial to improving the stability and efficiency of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0019] Figure 1 It is a schematic circuit diagram of a peak current mode switching converter in the prior art.

[0020] Figure 2a and Figure 2b They are schematic waveform diagrams of a switching converter in the prior art in a continuous conduction mode and a discontinuous conduction mode respectively.

[0021] Figure 3 The figure is a schematic waveform diagram of a switching converter in the prior art switching from a PWM mode to a PFM mode.

[0022] Figure 4 It is a schematic waveform diagram of a switching converter in the prior art working in the PFM mode.

[0023] Figure 5 The figure is a schematic waveform diagram of a switching converter in the prior art switching from a PFM mode to a PWM mode.

[0024] Figure 6 is a schematic circuit diagram of a switching converter according to an embodiment of the present invention.

[0025] Figure 7 is a schematic circuit diagram of a logic circuit according to an embodiment of the present invention.

[0026] Figure 8 is a schematic circuit diagram of an adaptive compensation circuit according to an embodiment of the present invention.

[0027] Fig. 9 It is a schematic waveform diagram of the switching converter according to an embodiment of the present invention switching from PWM mode to PFM mode. DETAILED DESCRIPTION

[0028] Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings.Where possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0029] In the specification, it should be noted that similar reference numerals that have been used to represent similar parts in other drawings are used for these elements as much as possible. In the following description, when functions and configurations known to those skilled in the art are not related to the basic configuration of the present disclosure, their detailed description will be omitted. The terms described in the specification should be understood as follows.

[0030] The advantages and features of the present disclosure and their implementation methods will be described through the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments described herein. Rather, these embodiments are provided to make the present disclosure comprehensive and complete, so as to fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0031] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is therefore not limited to the illustrated details. Similar reference numerals always represent similar elements. In the following description, when it is determined that a detailed description of a related known function or construction will inevitably obscure the focus of the present disclosure, the detailed description will be omitted.

[0032] As those skilled in the art can fully understand, the features of the various embodiments of the present disclosure can be partially or completely combined or combined with each other, and can interoperate and technically drive each other in various ways. The embodiments of the present disclosure can be performed independently of each other, or can be performed together in a mutually dependent relationship.

[0033] In the present application, a MOS tube (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first end, a second end and a control end. When the MOS tube is in the on state, current flows from the first end to the second end. The first end, the second end and the control end of a PMOS tube are the source, the drain and the gate, respectively, and the first end, the second end and the control end of an NMOS tube are the drain, the source and the gate, respectively.

[0034] like Figure 1 As shown, in the circuit structure of the conventional peak current mode switching converter 100, a power circuit and a control circuit 110 are included. The power circuit includes switches Q1 and Q2 connected in series between the input terminal of the switching converter 100 and the ground, an inductor L1 connected between the connection node SW of the two and the output terminal of the switching converter 100, and an output capacitor Cout and a feedback network connected in parallel between the output terminal of the switching converter 100 and the ground. The feedback network includes resistors Ra and Rb connected in series, which are used to generate a feedback voltage Vfb. The load Load is connected in parallel between the two ends of the output capacitor Cout.

[0035] The control circuit 110 of the switching converter 100 further includes an error amplifier 121 , a peak comparator 122 , a current sampling circuit 123 , a logic circuit 124 , a zero-crossing detection circuit 125 , a clamping circuit 126 , a compensation circuit 127 , a mode comparator 131 and a ripple comparator 132 .

[0036] The positive input terminal of the error amplifier 121 is used to receive the feedback voltage Vfb, and the negative input terminal is used to receive the reference voltage Vref1. The error amplifier 121 is configured to compare the feedback voltage Vfb with the reference voltage Vref1 to generate a loop error signal Verr, wherein the signal Verr represents the difference between the feedback voltage Vfb and the reference voltage Vref1.

[0037] The negative input terminal of the peak comparator 122 is used to receive the loop error signal Verr, and the positive input terminal is used to receive the current sampling signal Vipk related to the inductor current in the power circuit. For example, the current sampling circuit 123 obtains the current sampling signal Vipk by sensing the high-side current of the power circuit. The peak comparator 122 is configured to compare the current sampling signal Vipk with the loop error signal Verr to generate a peak control signal TRIP to turn off the switch tube Q1 when the inductor current peak reaches a set threshold in each switching cycle. The compensation circuit 127 is connected to the output terminal of the error amplifier 121 to provide frequency compensation to the loop error signal Verr.

[0038] The negative input terminal of the mode comparator 131 is used to receive the loop error signal Verr, and the positive input terminal is used to receive the threshold voltage VTPL or VTPH. The mode comparator 131 is configured to compare the loop error signal Verr with the threshold voltage VTPL or VTPH, and generate a mode control signal PFM according to the comparison result to control the switching converter 100 to operate in the PFM mode or the PWM mode.

[0039] The negative input terminal of the ripple comparator 132 is used to receive the feedback voltage Vfb, and the positive input terminal is used to receive the reference voltage Vref2. The ripple comparator 132 is configured to compare the feedback voltage Vfb with the reference voltage Vref2, and generate a ripple control signal Fbuv according to the comparison result.

[0040] The clamp circuit 126 is connected to the output terminal of the error amplifier 121 , and is used for clamping the loop error signal Verr at a set peak current threshold Vpeak according to the mode control signal PFM when the switching converter operates in the PFM mode.

[0041] Figure 2a and Figure 2b Schematic waveform diagrams of the switching converter in the prior art in the continuous conduction mode and the discontinuous conduction mode are shown respectively. Figure 2a and Figure 2b As shown, the existing switching converter 100 has two conduction modes according to the load conditions, namely, continuous conduction mode (CCM) and discontinuous conduction mode (DCM). In the DCM mode, the synchronous switch tube Q2 is turned off when the inductor current IL is reduced to 0A through the body diode. In the CCM mode, after the inductor current IL is continued to 0A, the synchronous switch tube Q2 will not be controlled to turn off, but will not be turned off until the inductor current IL reaches the maximum allowed negative current or the main switch tube Q1 is turned on, so that the inductor current IL can be continuous.

[0042] like Figure 2a As shown, when the switching converter 100 is in the CCM mode, the main switch tube Q1 is turned on when the pulse of the clock signal CLK arrives, and the current sampling signal Vipk gradually rises. When the current sampling signal Vipk rises to the loop error signal Verr, the main switch tube Q1 is turned off, the synchronous switch tube Q2 is turned on, and the inductor current decreases until the next pulse of the clock signal CLK arrives, and the main switch tube Q1 is turned on again. Therefore, the switching converter 100 is in the PWM mode at this time, and the duty cycle of the switching signal is adjusted by adjusting the on-time (i.e., pulse width) of the switching signal in each switching cycle, and the switching frequency is constant.

[0043] In PWM mode, the current sampling signal , where Ipeak is the peak current of the inductor current IL, Ri is the sampling coefficient, and Voffset is the fixed offset voltage. Figure 2a and Figure 2bIt can be seen that when the switching converter 100 is in PWM mode, the peak current Ipeak of the inductor current is always equal to the loop error signal Verr. As the load current decreases, the peak current Ipeak of the inductor current gradually decreases, and the loop error signal Verr also decreases. When the inductor current triggers zero-crossing detection due to a load drop, the synchronous switch tube needs to be turned off when the inductor current crosses zero. At this time, the switching converter 100 works as follows: Figure 2b In the DCM mode shown in FIG. 1 , a dead time of duration T0 will appear between the main switch tube Q1 and the synchronous switch tube Q2 in the DCM mode.

[0044] After the switching converter 100 transitions from the heavy-load CCM mode to the light-load DCM mode, as the load current further decreases, the inductor current peak value Ipeak will further decrease. At this time, in order to save power, the switching converter 100 needs to switch from the PWM mode to the PFM mode to improve the efficiency of the circuit.

[0045] Specifically, Figure 3 As shown, as the load current ILoad decreases, the loop error signal Verr will also decrease. When the load current ILoad is less than the current I3, the loop error signal Verr is less than the threshold voltage VTPL, and the mode control signal PFM becomes high level, indicating that the system enters the PFM mode. When the switching converter 100 is in the PFM mode, the feedback voltage Vfb is compared with the reference voltage Vref2 by the wave comparator 132 to control the turn-on time of the main switch tube Q1, and the turn-off time of the main switch tube Q1 is controlled by the comparison result of the current sampling signal Vipk and the loop error signal Verr, and finally the feedback voltage Vfb is stabilized near the reference voltage Vref2. Since the reference voltage Vref2 is greater than the reference voltage Vref1, the feedback voltage Vfb will be greater than the reference voltage Vref1, which will cause the voltage of the loop error signal Verr to be very low. Therefore, the switching converter 100 of the prior art also needs the clamping circuit 126 to clamp the voltage of the loop error signal Verr at the set peak current threshold, so as to fix the peak value of the inductor current of the circuit to Ipeak0.

[0046] like Figure 4 As shown, after the switching converter 100 in the prior art enters the PFM mode, the feedback voltage Vfb is compared with the reference voltage Vref2. Whenever the feedback voltage Vfb is less than the reference voltage Vref2, the switch tube Q1 is turned on, causing the inductor current to increase. When the peak value of the inductor current reaches Ipeak0, the switch tube Q1 is turned off, and the inductor current decreases.

[0047] like Figure 5As shown, when the switching converter 100 is in the PFM mode, as the load current ILoad increases, when the load current is greater than the output current corresponding to the peak current Ipeak0, the feedback voltage Vfb begins to decrease until the feedback voltage Vfb is less than the reference voltage Vref1, and the loop error signal Verr begins to rise. When the loop error signal Verr is greater than the threshold voltage VTPH, the switching converter 100 switches from the PFM mode to the PWM mode.

[0048] like Figure 3 and Figure 5 As shown, the existing peak current mode DCDC converter usually uses the peak current of the fixed inductor when lightly loaded, and uses the comparison result of the feedback voltage Vfb and the reference voltage Vref2 to determine whether to turn on the main power tube Q1, thereby adjusting the operating frequency of the system. However, since the voltage value of the reference voltage Vref2 needs to be greater than the voltage value of the reference voltage Vref1, the output voltage of the DCDC converter is relatively high in the PFM mode, so that when the DCDC converter switches between the PWM mode and the PFM mode, the output voltage fluctuates greatly, which increases the output ripple of the circuit and reduces the system stability and efficiency.

[0049] Figure 6 FIG. 1 is a schematic circuit diagram of a switching converter according to an embodiment of the present invention. Figure 6 As shown, the switching converter 200 of this embodiment includes a power circuit and a control circuit 210. The power circuit is an output circuit of a common peak current mode synchronous rectification buck switching regulator, which steps down the input voltage Vin applied to the input terminal and provides an output voltage Vout from the output terminal.

[0050] However, the present invention is not limited to this, and the various concepts disclosed in the present invention can be used in association with any type of DC-DC converter architecture, for example, according to the topology classification of the power circuit, including a buck converter, a boost converter, a flyback converter, and a buck-boost converter, etc. In addition, although complementary PWM control of a high-side switch device and a low-side switch device is used in the examples of the embodiments of the present invention, the concepts described in the present invention can be implemented in a power converter using only a single switch device, and / or in a power converter applying more than two pulse width modulations.

[0051] like Figure 6As shown, the power circuit includes a high-side switch tube Q1 (also called the main power tube), a low-side switch tube Q2 (also called a synchronous rectifier tube) and an inductor L1. Among them, the drains of the high-side switch tube Q1 and the low-side switch tube Q2 are connected to each other, and the common end of the two forms a switch node SW, the source of the low-side switch tube Q2 is connected to the ground terminal, and the source of the high-side switch tube Q1 is connected to the input voltage VIN. The first end of the inductor L1 is connected to the switch node LX, and the second end of the inductor L1 is connected to the output voltage VOUT. It should be understood that in this embodiment, the switch tube Q1 is the main power tube, the switch tube Q2 is the rectifier tube, and the switch tubes Q1 and Q2 can be any type of field effect tube, such as a metal oxide semiconductor field effect transistor (MOSFET), and can also be other types of field effect tubes and / or other types of transistors within the scope known to those skilled in the art without departing from the teachings of the present invention.

[0052] The switching converter 200 further includes an output capacitor Cout, which is arranged between the output terminal of the switching converter 200 and the ground terminal to generate an output voltage Vout at its two ends. The voltage divider network composed of resistors Ra and Rb is used to obtain a feedback voltage Vfb of the output voltage Vout.

[0053] The control circuit 210 is used to generate a driving signal applied to the gates of the switch tubes Q1 and Q2, and control the switch states of the switch tubes Q1 and Q2 to provide energy to the load. In this embodiment, the control circuit 210 repeatedly turns the switch tubes Q1 and Q2 on / off alternately, and uses the inductor L1 to perform energy conversion, so that the input voltage Vin is stepped down, and the stepped-down voltage is smoothed through the inductor L1 and the output capacitor Cout, and is output as the output voltage Vout.

[0054] The control circuit 210 of the switching converter 200 may be integrated into an LSI chip on a semiconductor substrate. In this embodiment, the switch tubes Q1 and Q2 may be arranged outside the control circuit 210, but may also be arranged inside the control circuit.

[0055] The switching converter of the embodiment of the present invention can be operated in multiple working modes. Further, the switching converter of the present embodiment can be operated in a combination of a pulse width modulation mode (hereinafter referred to as a PWM mode) and a pulse frequency modulation mode (hereinafter referred to as a PFM mode). When the load of the switching converter is heavy, the switching converter operates in the PWM mode; when the load of the switching converter is light, the switching converter operates in the PFM mode.

[0056] In this embodiment, the control circuit 210 of the switching converter 200 further includes an error amplifier 221 , a peak comparator 222 , a current sampling circuit 223 , a logic circuit 224 , a zero-crossing detection circuit 225 , an adaptive compensation circuit 226 , a mode comparator 231 and a ripple comparator 232 .

[0057] The positive input terminal of the error amplifier 221 is used to receive the feedback voltage Vfb, and the negative input terminal is used to receive the reference voltage Vref1. The error amplifier 221 is configured to compare the feedback voltage Vfb with the reference voltage Vref1 to generate a loop error signal Verr, wherein the signal Verr represents the difference between the feedback voltage Vfb and the reference voltage Vref1.

[0058] The negative input terminal of the mode comparator 231 is used to receive the loop error signal Verr, and the positive input terminal is used to receive the threshold voltage VTPL or VTPH. The mode comparator 231 is configured to compare the loop error signal Verr with the threshold voltage VTPL or VTPH, and generate a mode control signal PFM according to the comparison result to control the switching converter 200 to operate in the PFM mode or the PWM mode.

[0059] Furthermore, the control circuit 210 of the present embodiment further includes a switch S1 connected to the positive input terminal of the mode comparator 231, and the switch S1 is used to switch the voltage of the negative input terminal of the mode comparator 231 according to the state of the mode control signal PFM. Specifically, when the mode control signal PFM is invalid (for example, low level), the switch S1 provides the threshold voltage VTPL to the positive input terminal of the mode comparator 231, and when the mode control signal PFM is valid (for example, high level), the switch S1 provides the threshold voltage VTPH to the positive input terminal of the mode comparator 231.

[0060] The negative input terminal of the ripple comparator 232 is used to receive a threshold voltage Vpeak indicating a set inductor current peak value, and the positive input terminal is used to receive the loop error signal Verr. The ripple comparator 232 is configured to compare the loop error signal Verr with the threshold voltage Vpeak, and generate a ripple control signal Fbuv according to the comparison result.

[0061] The positive input terminal of the peak comparator 222 is used to receive a current sampling signal Vipk related to the inductor current in the power circuit. For example, the current sampling circuit 223 obtains the current sampling signal Vipk by sensing the high-side current of the power circuit. The peak comparator 222 is used to compare the current sampling signal Vipk with the loop error signal Verr or the threshold voltage Vpeak according to the mode control signal PFM to generate a peak control signal TRIP. The peak control signal TRIP is used to turn off the switch tube Q1 when the peak value of the inductor current reaches a set threshold in each switching cycle.

[0062] Furthermore, a switch S2 is provided at the negative input terminal of the peak comparator 222 , and the switch S2 is used to provide the loop error signal Verr or the threshold voltage Vpeak to the negative input terminal of the peak comparator 222 according to the mode control signal PFM.

[0063] Furthermore, when the mode control signal PFM is valid (for example, a high level), the switch S2 provides the threshold voltage Vpeak to the negative input terminal of the peak comparator 222, and the peak comparator 222 compares the current sampling signal Vipk with the threshold voltage Vpeak to generate the peak control signal TRIP; when the mode control signal PFM is invalid (for example, a low level), the switch S2 provides the loop error signal Verr to the negative input terminal of the peak comparator 222, and the peak comparator 222 compares the current sampling signal Verr with the loop error signal Verr to generate the peak control signal TRIP.

[0064] In this embodiment, the adaptive compensation circuit 227 is connected to the output terminal of the error amplifier 221 and is used to provide frequency compensation to the loop error signal Verr according to the mode control signal PFM.

[0065] In this embodiment, the zero-crossing detection circuit 227 is used to detect the inductor current of the switching converter 200 and generate a valid zero-crossing detection signal ZCD when the inductor current passes through zero, so as to control the turn-off time of the synchronous switch tube Q2 in each switching cycle.

[0066] The logic circuit 224 is used to implement the logic control function of the system, and its input is connected to the clock signal CLK, the peak comparator 222, the wave comparator 232, the mode comparator 231 and the output of the zero-crossing detection circuit 225. The output of the logic circuit 224 is connected to the gates of the switch tubes Q1 and Q2, and operates these transistors so that the power circuit outputs electrical energy to the load in the PWM mode or the PFM mode. For example, the logic circuit 224 generates a complementary first switch signal HSDR and a second switch signal LSDR, and generates a gate control signal to drive the gates of the switch tubes Q1 and Q2 according to these two signals. In an exemplary embodiment, the control circuit 210 also includes a driver (not shown in the figure) corresponding to the switch tubes Q1 and Q2, and the driver is used to drive the switch tubes Q1 and Q2 according to the first switch signal HSDR and the second switch signal LSDR, respectively.

[0067] Depending on the output of the logic circuit 224, the current will flow from the input voltage Vin through the inductor L1 and through the switch tube Q1 or the switch tube Q2. When the switch tube Q1 is turned on, the input voltage Vin charges the inductor L1, so the current of the inductor L1 increases; when the switch tube Q2 is turned on, the current stored in the inductor L1 flows to the load, so the current of the inductor L1 decreases.

[0068] Further, the logic circuit 224 of this embodiment is also used to control the change of the operation of the power circuit between the PWM mode and the PFM mode according to the mode control signal PFM. For example, when the mode control signal PFM is valid, the logic circuit 224 controls the power circuit to operate in the PFM mode, and controls the turn-on time of the switch tube Q1 in each switching cycle according to the ripple control signal Fbuv, and controls the turn-off time of the switch tube Q1 in each switching cycle according to the peak control signal TRIP, and adjusts the switching frequency by adjusting the time position of the pulse of the switching signal, and the pulse width of the switching signal (that is, the turn-on time in the switching cycle) is constant; when the mode control signal PFM is invalid, the logic circuit 224 controls the power circuit to operate in the PWM mode, and controls the turn-on time of the switch tube Q1 in each switching cycle according to the clock signal CLK, and controls the turn-off time of the switch tube Q1 in each switching cycle according to the peak control signal TRIP, and adjusts the duty cycle of the switch signal by adjusting the turn-on time (that is, pulse width) of the switch signal in each switching cycle, and the switching frequency is constant.

[0069] Figure 7 FIG. 1 is a schematic circuit diagram of a logic circuit according to an embodiment of the present invention. Figure 7As shown, the logic circuit 224 of this embodiment includes inverters INV1, INV5 and INV6, RS latches 201 and 202, and logic modules 203 and 204. The input of the inverter INV1 is connected to the peak control signal TRIP, the output of the inverter INV1 is connected to the set end of the RS latch 201, the output end of the RS latch 201 is connected to the input of the inverter INV5, and the output of the inverter INV5 is used to provide the first switch signal HSDR.

[0070] The input of the logic module 203 is used to receive the mode control signal PFM, the clock signal CLK and the waving control signal Fbuv, and the output of the logic module 203 is connected to the reset terminal of the RS latch 201. The logic module 203 is configured to control the waveform of the logic signal V1 to be consistent with the clock signal CLK or the waving control signal Fbuv according to the state of the mode control signal PFM. For example, when the mode control signal PFM is invalid, the logic module 203 controls the waveform of the logic signal V1 to be consistent with the waveform of the clock signal CLK; when the mode control signal PFM is valid, the logic module 203 controls the waveform of the logic signal V1 to be consistent with the waveform of the waving control signal Fbuv.

[0071] In this embodiment, the logic module 203 includes NAND gates NAND1-NAND3, inverters INV2-INV4 and NOR gate NOR1. The first input end of the NAND gate NAND1 is used to receive the mode control signal PFM, the second input end of the NAND gate NAND1 is used to receive the wave control signal Fbuv, the output end of the NAND gate NAND1 is connected to the input end of the inverter INV2, and the output of the inverter INV2 is connected to the first input end of the NOR gate NOR1. The input of the inverter INV3 is connected to the wave control signal Fbuv, the output of the inverter INV3 is connected to the first input terminal of the NAND gate NAND2, the second input terminal of the NAND gate NAND2 is connected to the mode control signal PFM, the output terminal of the NAND gate NAND2 is connected to the first input terminal of the NAND gate NAND3, the second input terminal of the NAND gate NAND3 is connected to the clock signal CLK, the output terminal of the NAND gate NAND3 is connected to the input of the inverter INV4, the output of the inverter INV4 is connected to the second input terminal of the NOR gate NOR1, and the output terminal of the NOR gate NOR1 is connected to the reset terminal of the RS latch 201.

[0072] The input of the inverter INV6 is connected to the zero-crossing detection signal ZCD, the output of the inverter INV6 is connected to the set end of the RS latch 202, and the reset end of the RS latch 202 is connected to the output end of the RS latch 201. The input of the logic module 204 is connected to the output ends of the RS latches 201 and 202, and is used to obtain the second switch signal LSDR according to the outputs of the RS latches 201 and 202.

[0073] Specifically, the logic module 204 includes inverters INV7 and INV8 and a NAND gate NAND4. The input of the inverter INV7 is connected to the output of the RS latch 202, the output of the inverter INV7 is connected to the second input of the NAND gate NAND4, the first input of the NAND gate NAND4 is connected to the output of the RS latch 201, the output of the NAND gate NAND4 is connected to the input of the inverter INV8, and the output of the inverter INV8 is used to provide the second switch signal LSDR.

[0074] Table 1 shows the truth table of RS latches 201 and 202 .

[0075] R S Q 0 0 1 0 1 0 1 0 1 1 1 Keep it the same Table 1

[0076] exist Figure 7In the embodiment, when the switching converter 200 is in the PWM mode, the mode control signal PFM and the pulsation control signal Fbuv are both at low level, and then the output of the inverter INV2 is at low level, and the output of the NAND gate NAND2 is at high level, so the outputs of the NAND gate NAND3 and the NOR gate NOR1 are both inverted signals of the clock signal CLK, so when the pulse of the clock signal CLK arrives, the reset end of the RS latch 201 is at low level "0", and the set end is at high level "1", and the output end of the RS latch 201 is set to low level "0", so the first switch signal HSDR flips to high level, and the second switch signal LSDR flips to low level, the switch tube Q1 is turned on, the switch tube Q2 is turned off, and the inductor current IL gradually increases. When the peak value of the inductor current reaches the loop error signal Verr, the peak control signal TRIP is flipped to a high level, the set end of the RS latch 201 becomes a low level "0", and the output end of the RS latch 201 is set to a high level "1", so the first switch signal HSDR is flipped to a low level, the second switch signal LSDR is flipped to a high level, the switch tube Q1 is turned off, the switch tube Q2 is turned on, and the inductor current IL gradually decreases. When the inductor current IL decreases to 0A, the zero-crossing detection circuit 227 generates a valid (for example, a narrow pulse) zero-crossing detection signal ZCD, so the output end of the RS latch 202 is set to "1", and after passing through the inverter INV7, the NAND gate NAND4 and the inverter INV8, the second switch signal LSDR is flipped to a low level. At this time, the switching converter 200 is in the dead time when both the main switch tube Q1 and the synchronous switch tube Q2 are turned off. When the pulse of the clock signal CLK arrives again, the first switch signal HSDR is flipped to a high level again, and the main switch tube Q1 is triggered to turn on again, and the cycle repeats.

[0077] When the switching converter 200 is in the PFM mode, the mode control signal PFM is at a high level, the waveform of the logic signal V1 mainly changes with the ripple control signal Fbuv, and the pulse of the clock signal CLK is shielded. Therefore, when the pulse of the ripple control signal Fbuv arrives, the reset end of the RS latch 201 is at a low level "0", the set end is at a high level "1", and the output end of the RS latch 201 is set to a low level "0", so the first switch signal HSDR flips to a high level, the second switch signal LSDR flips to a low level, the switch tube Q1 is turned on, the switch tube Q2 is turned off, and the inductor current IL gradually increases. When the peak value of the inductor current reaches the threshold voltage Vpeak, the peak control signal TRIP flips to a high level, the set end of the RS latch 201 becomes a low level "0", and the output end of the RS latch 201 is set to a high level "1", so the first switch signal HSDR flips to a low level, the second switch signal LSDR flips to a high level, the switch tube Q1 is turned off, the switch tube Q2 is turned on, and the inductor current IL gradually decreases. When the inductor current IL decreases to 0A, the zero-crossing detection circuit 227 generates a valid (for example, a narrow pulse) zero-crossing detection signal ZCD, so the output of the RS latch 202 is set to "1", and after passing through the inverter INV7, the NAND gate NAND4 and the inverter INV8, the second switch signal LSDR is flipped to a low level. At this time, the switching converter 200 is in the dead time when both the main switch tube Q1 and the synchronous switch tube Q2 are turned off. When the pulse of the ripple control signal Fbuv arrives again, the first switch signal HSDR is flipped to a high level again, and the main switch tube Q1 is triggered to turn on again, and the cycle repeats.

[0078] Figure 8 FIG. 1 is a schematic circuit diagram of an adaptive compensation circuit according to an embodiment of the present invention. Figure 8 As shown, the adaptive compensation circuit 226 of this embodiment includes compensation resistors Rz1 and Rz2, compensation capacitor Cz and switch K1. The compensation resistor Rz1, compensation resistor Rz2 and compensation capacitor Cz are connected in series between the output end of the error amplifier 221 and the reference ground, and the switch K1 is connected in parallel between the two ends of the compensation resistor Rz2. The on and off of the switch K1 is controlled by the mode control signal PFM. For example, the switch K1 is used to be disconnected when the mode control signal PFM is valid, and to be turned on when the mode control signal PFM is invalid, so that the loop bandwidth of the compensation network can be increased when the switching converter 200 switches from the PFM mode to the PWM mode, thereby improving the response speed.

[0079] Fig. 9 FIG. 1 is a schematic waveform diagram of a switching converter according to an embodiment of the present invention switching from a PWM mode to a PFM mode. Fig. 9As shown, in this embodiment, the threshold voltage Vpeak is greater than the threshold voltage VTPL and less than the threshold voltage VTPH. Fig. 9 The working process of the control circuit 210 of this embodiment is described in detail with reference to the working waveform diagram.

[0080] Specifically, before time t1, the load current ILoad of the switching converter 200 is greater than the preset current I3, at which time the loop error signal Verr is greater than the threshold voltage VTPL, and the switching converter 200 operates in the PWM mode, at which time the circuit controls the conduction of the switch tube Q1 according to the pulse of the clock signal CLK, and controls the turn-off of the switch tube Q1 according to the comparison result of the current sampling signal Vipk and the loop error signal Verr. As the load current ILoad decreases, after time t1, the load current ILoad of the switching converter 200 is less than the preset current I3, at which time the loop error signal Verr is less than the threshold voltage VTPL, and the switching converter 200 operates in the PFM mode, at which time the circuit controls the conduction of the switch tube Q1 according to the comparison result of the loop error signal Verr and the threshold voltage Vpeak, and controls the turn-off of the switch tube Q1 according to the comparison result of the current sampling signal Vipk and the threshold voltage Vpeak.

[0081] Specifically, in the PFM mode, whenever the loop error signal Verr is greater than the threshold voltage Vpeak, the ripple control signal Fbuv becomes high level, the switch tube Q1 of the control power circuit is turned on, and the inductor current rises. Whenever the current sampling signal Vipk rises to the threshold voltage Vpeak, the switch tube Q1 is turned off, and the inductor current drops, and finally the loop error signal Verr fluctuates around the threshold voltage Vpeak. In addition, since the threshold voltage Vpeak is set according to the preset inductor peak current and will not fluctuate with the change of load current, the switching converter 200 can also fix the peak value of the inductor current in the PFM mode. In addition, from Fig. 9 It can be seen that in the switching converter of this embodiment, no matter in PWM mode or PFM mode, the feedback voltage Vfb always fluctuates around the reference voltage Vref, so the problem of high output voltage will not occur in PFM mode, which is beneficial to improving the stability and efficiency of the system.

[0082] In summary, the switching converter and its control circuit and control method according to the embodiment of the present invention determine the timing of turning on the main power tube according to the comparison result between the loop error signal and the preset threshold voltage in the PFM mode, and determine the timing of turning off the main power tube according to the comparison result between the current sampling signal representing the inductor current and the threshold voltage, so that the switching frequency can be adjusted by adjusting the time position of the pulse of the switching signal, and the pulse width of the switching signal (that is, the conduction time in the switching cycle) is constant. Compared with the control scheme of the prior art, the feedback voltage of the switching converter according to the embodiment of the present invention always fluctuates around the reference voltage regardless of whether it is in the PWM mode or the PFM mode, so the problem of high output voltage in the PFM mode will not occur, which is beneficial to improving the stability and efficiency of the system.

[0083] In the above description, the well-known structural elements and steps are not described in detail. However, it should be understood by those skilled in the art that the corresponding structural elements and steps can be realized by various technical means. In addition, in order to form the same structural elements, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although each embodiment is described above respectively, this does not mean that the measures in each embodiment cannot be advantageously used in combination.

[0084] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A control circuit for a switching converter, the switching converter comprising a main power tube, wherein: The control circuit comprises: an error amplifier, used for comparing a feedback voltage of the output voltage of the switching converter with a reference voltage to generate a loop error signal; a mode comparator, for comparing the loop error signal with one of a first threshold voltage and a second threshold voltage to generate a mode control signal; A wave-generating comparator, used for comparing the loop error signal with a third threshold voltage to generate a wave-generating control signal; a peak comparator, configured to compare a current sampling signal related to an inductor current of the switching converter with the loop error signal or the first threshold voltage according to the mode control signal to generate a peak control signal; and a logic circuit, used to generate a switch signal according to the mode control signal, the wave control signal, the peak control signal and the clock signal, wherein the switch signal is used to control the on or off of the main power tube, Wherein, when the mode control signal is valid, the peak comparator generates the peak control signal according to the comparison result between the current sampling signal and the third threshold voltage, and the logic circuit controls the turn-on time of the main power tube in each switching cycle according to the ripple control signal, and controls the turn-off time of the main power tube in each switching cycle according to the peak control signal, so as to control the switching converter to operate in the first mode, and When the mode control signal is invalid, the peak comparator generates the peak control signal according to the comparison result of the current sampling signal and the loop error signal, and the logic circuit controls the turn-on time of the main power tube in each switching cycle according to the clock signal, and controls the turn-off time of the main power tube in each switching cycle according to the peak control signal, so as to control the switching converter to operate in the second mode.

2. The control circuit according to claim 1, wherein: The first mode is a pulse frequency modulation mode, and the second mode is a pulse width modulation mode.

3. The control circuit according to claim 1, wherein: A voltage value of the third threshold voltage is greater than a voltage value of the first threshold voltage, and less than a voltage value of the second threshold voltage.

4. The control circuit according to claim 3, wherein: The mode comparator has a positive input terminal, a negative input terminal and an output terminal, and the negative input terminal of the mode comparator is used to receive the loop error signal. The control circuit also includes: The first switch is used to provide the first threshold voltage to the positive input terminal of the mode comparator when the mode control signal is invalid, and to provide the second threshold voltage to the positive input terminal of the mode comparator when the mode control signal is valid.

5. The control circuit according to claim 1, wherein: The switching converter further includes a synchronous rectifier tube that is non-overlappingly conductive with the main power tube, and the control circuit further includes: The zero-crossing detection circuit is used to generate a zero-crossing detection signal when the inductor current passes through zero, and the logic circuit is also used to control the turn-off moment of the rectifier tube in each switching cycle according to the zero-crossing detection signal.

6. The control circuit according to claim 5, wherein: The logic circuit comprises: A first latch, whose set end is used to receive the inverted signal of the peak control signal, and whose output end is used to output a first switching signal via a first inverter, wherein the first switching signal is used to control the on or off of the main power tube; a first logic module, configured to provide a logic signal related to the clock signal to a reset terminal of the first latch when the mode control signal is invalid, and to provide a logic signal related to the oscillation control signal to a reset terminal of the first latch when the mode control signal is valid; A second latch, whose reset terminal is connected to the output terminal of the first latch, and whose set terminal is used to receive an inverted signal of the zero-crossing detection signal; and The second logic module is used to provide a second switch signal according to the output of the first latch and the second latch, and the second switch signal is used to control the conduction or shutdown of the synchronous rectifier.

7. The control circuit according to claim 6, wherein: The first logic module includes: A first NAND gate, whose first input terminal is used to receive the mode control signal, and whose second input terminal is used to receive the oscillation control signal; A second NAND gate, a first input end of which receives the ripple control signal via a second inverter, and a second input end of which is used to receive the mode control signal; A third NAND gate, a first input end of which is connected to the output end of the second NAND gate, and a second input end of which is used to receive the clock signal; a first NOR gate, whose first input terminal is connected to the output terminal of the first NAND gate via a third inverter, whose second input terminal is connected to the output terminal of the third NAND gate via a fourth inverter, and whose output terminal is connected to the reset terminal of the first latch, The second logic module includes: a fifth inverter, an input terminal of which is connected to the output terminal of the second latch; a fourth NAND gate, a first input terminal of which is connected to the output terminal of the first latch, and a second input terminal of which is connected to the output terminal of the fifth inverter; and A sixth inverter, whose input end is connected to the output end of the fourth NAND gate, and whose output end is used to provide the second switch signal.

8. The control circuit according to claim 1, further comprising: an adaptive compensation circuit, connected to the output terminal of the error amplifier, and configured to provide frequency compensation to the loop error signal according to the mode control signal, wherein the adaptive compensation circuit comprises: A first compensation resistor, a second compensation resistor and a compensation capacitor connected in series between the output terminal of the error amplifier and a reference ground; and A second switch is connected in parallel between two ends of the second compensation resistor, and the second switch is used to be disconnected when the mode control signal is valid, and to be turned on when the mode control signal is invalid.

9. A control method for a switching converter, the switching converter comprising a main power tube, the control method comprising: Comparing a feedback voltage of the output voltage of the switching converter with a reference voltage to generate a loop error signal; comparing the loop error signal with one of a first threshold voltage and a second threshold voltage to generate a mode control signal; When the mode control signal is valid, the turn-on time of the main power tube in each switching cycle is controlled according to the comparison result between the loop error signal and the third threshold voltage, and the turn-off time of the main power tube in each switching cycle is controlled according to the comparison result between the current sampling signal related to the inductor current and the third threshold voltage, so as to control the switching converter to operate in the pulse frequency modulation mode; as well as When the mode control signal is invalid, the turn-on time of the main power tube in each switching cycle is controlled according to the clock signal, and the turn-off time of the main power tube in each switching cycle is controlled according to the comparison result between the current sampling signal and the loop error signal, so as to control the switching converter to operate in the pulse width modulation mode.

10. A switching converter, comprising: Power circuit, including main power tube, synchronous rectifier tube and inductor; as well as The control circuit according to any one of claims 1 to 8, wherein the control circuit converts the input voltage into the output voltage by repeatedly turning on / off the main power tube and the synchronous rectifier tube alternately and utilizing the inductor to perform energy conversion.

Images