ESD structure based on high-voltage power PMOS transistor

Abstract

The invention relates to the technical field of semiconductor integrated circuits, and particularly discloses an ESD (Electro-Static Discharge) structure based on a high-voltage power PMOS (P-channel Metal Oxide Semiconductor) tube, which comprises a parasitic PNP tube for performing ESD protection on the input end of the high-voltage power PMOS tube to the ground; the parasitic PNP tube comprises a source P active region of the high-voltage power PMOS tube serving as a base, an external P active region substrate grounding ring serving as a collector and a back grid N active region ring of the high-voltage power PMOS tube serving as a base electrode; wherein in a normal working state, the parasitic PNP tube is in a cut-off state; when an electrostatic discharge event occurs, the parasitic PNP tube is conducted. The problem that an existing high-voltage pin ESD protection device occupies a large chip area can be solved, the occupied chip area is small, and meanwhile high ESD protection capacity is provided.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to an ESD structure based on a high-voltage power PMOS tube. Background Art

[0002] During the manufacturing, transportation, and use of integrated circuit chips, due to the accumulation of charges in the external environment or internal structure, when a path is formed between pins, charge transfer occurs, forming electrostatic discharge. Electrostatic discharge usually has a very high instantaneous voltage, which can cause excessive electrical stress damage to electronic components or integrated circuit systems. This damage is usually devastating and permanent, and can cause the circuit to burn out directly.

[0003] In order to solve the problem of electrostatic discharge, it is necessary to provide a discharge path for the accumulated charge. Therefore, an electrostatic discharge protection circuit is usually used in the integrated circuit to discharge the accumulated charge. The electrostatic discharge protection circuit can be various ESD protection devices or ESD trigger protection modules. For the ESD protection of high-voltage pins, high-voltage devices or stacked low-voltage devices can generally be used as ESD protection devices for high-voltage pins to achieve ESD protection for high-voltage pins. However, whether it is a high-voltage device or a stacked low-voltage device for ESD protection of high-voltage pins, it takes up a large chip area. If the integrated circuit has many high-voltage pins, the ESD protection device will occupy a large chip area, increasing the chip cost.

[0004] Therefore, it is urgent to propose an ESD structure that can solve the problem that the existing high-voltage pin ESD protection device occupies a large chip area, occupy a smaller chip area, and provide a higher ESD protection capability. Summary of the invention

[0005] In view of the above problems, the purpose of the present invention is to provide an ESD structure based on a high-voltage power PMOS tube, which can solve the problem that the existing high-voltage pin ESD protection device occupies a large chip area, occupy a smaller chip area, and provide higher ESD protection capability.

[0006] The present invention provides an ESD structure based on a high-voltage power PMOS tube, comprising: a parasitic PNP tube for performing ESD protection from the input end of the high-voltage power PMOS tube to the ground;

[0007] The parasitic PNP tube includes a source P active region of a high-voltage power PMOS tube as a base, an external P active region substrate grounding ring as a collector, and a back gate N active region ring of a high-voltage power PMOS tube as a base electrode;

[0008] Wherein, under normal working conditions, the parasitic PNP tube is in a cut-off state; and when an electrostatic discharge event occurs, the parasitic PNP tube is turned on.

[0009] In a possible implementation, the source P active region is located in a deep N well.

[0010] In a possible implementation, the back gate N active region of the high-voltage power PMOS tube is located in a shallow N well.

[0011] In a possible implementation manner, the shallow N-well is located in the deep N-well.

[0012] In a possible implementation, the source P active region and the back gate N active region are short-circuited by metal and are at the same potential.

[0013] In a possible implementation, the back gate N active area ring is located between the source P active area and the external P active area substrate grounding ring.

[0014] In a possible implementation, the back gate N active region ring is formed by a P well led out from a P active region.

[0015] In a possible implementation, the trigger voltage of the parasitic PNP transistor is adjusted by the distance between the shallow N well and the back gate N active region.

[0016] In a possible implementation, the trigger voltage of the parasitic PNP transistor is adjusted by the distance between the back gate N active region and the source P active region.

[0017] In a possible implementation, under normal working conditions, the trigger voltage of the parasitic PNP tube is adjusted by the distance between the shallow N well covering the back gate N active area and the distance between the back gate N active area and the source P active area.

[0018] The ESD structure based on the high-voltage power PMOS tube provided by the present invention uses the outermost source of the high-voltage power PMOS tube as the emitter, the back gate of the high-voltage power PMOS tube as the base, and the P-type substrate externally grounded to the high-voltage power PMOS tube as the collector to form a large-area parasitic PNP tube as an ESD discharge device from the source of the high-voltage power PMOS tube to the ground. The base resistance of the parasitic PNP tube is adjusted by adjusting the base concentration of the parasitic PNP tube, thereby adjusting the trigger voltage of the parasitic PNP tube, thereby achieving the design requirements of low trigger voltage and high holding voltage of the high-voltage power PMOS tube. The present invention realizes ESD protection for the high-voltage power PMOS tube without adding additional ESD devices, effectively saving chip production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 An ESD protection structure diagram provided by an embodiment of the present invention;

[0020] Figure 2 A schematic longitudinal cross-sectional view of a high-voltage process without an N-type buried layer and without epitaxy provided in an embodiment of the present invention;

[0021] Figure 3 A schematic longitudinal cross-sectional view of a high-voltage epitaxial growth process with an N-type buried layer provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following detailed description of the embodiments of the present invention is further described in detail in conjunction with the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to exemplarily illustrate the principles of the present invention, but cannot be used to limit the scope of the present invention, that is, the present invention is not limited to the preferred embodiments described, and the scope of the present invention is defined by the claims.

[0023] In the description of the present invention, it should be noted that, unless otherwise specified, “plurality” means two or more than two; the terms “first”, “second”, etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance; for ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0024] Figure 1 The ESD protection structure diagram provided by the embodiment of the present invention is as follows: Figure 1 As shown, the ESD structure based on the high-voltage power PMOS tube provided by the present invention includes: a parasitic PNP tube for performing ESD protection from the input end of the high-voltage power PMOS tube to the ground; the parasitic PNP tube includes a source P active region of the high-voltage power PMOS tube as a base, an external P active region substrate grounding ring as a collector, and a back gate N active region ring of the high-voltage power PMOS tube as a base electrode. In the normal working state, the parasitic PNP tube is in a cut-off state; and when an electrostatic discharge event occurs, the parasitic PNP tube is turned on.

[0025] In a possible implementation, the source P active region is located in a deep N well. The back gate N active region of the high voltage power PMOS tube is located in a shallow N well. The shallow N well is located in a deep N well. The source P active region and the back gate N active region are short-circuited by metal and are at the same potential. The back gate N active region ring is located between the source P active region and the external P active region substrate grounding ring. The back gate N active region ring is formed by the P well led out of the P active region.

[0026] In a preferred embodiment, the trigger voltage of the parasitic PNP transistor can be adjusted by the distance between the shallow N well and the back gate N active region.

[0027] In a preferred embodiment, the trigger voltage of the parasitic PNP transistor can be adjusted by the distance between the back gate N active region and the source P active region.

[0028] In a preferred embodiment, the trigger voltage of the parasitic PNP transistor is adjusted by the distance between the shallow N well and the back gate N active region and the distance between the back gate N active region and the source P active region.

[0029] The embodiment of the present invention cleverly utilizes the structural characteristics of the high-voltage power PMOS tube itself, uses its outermost source as the emitter, the back gate as the base, and the externally grounded P-type substrate as the collector, thereby forming a large-area parasitic PNP tube. Under normal working conditions, the parasitic PNP tube is in a cut-off state and will not affect the normal function of the high-voltage power PMOS tube. When an electrostatic discharge (ESD) event occurs, the parasitic PNP tube can be quickly turned on to provide a low-resistance path from the source of the high-voltage power PMOS tube to the ground for the ESD current, thereby effectively protecting the high-voltage power PMOS tube from damage by ESD. The base concentration of the parasitic PNP tube has a direct impact on its base resistance. By adjusting the base concentration, the size of the base resistance can be changed. When the base resistance increases, the trigger voltage of the parasitic PNP tube will increase accordingly; conversely, when the base resistance decreases, the trigger voltage will decrease.

[0030] Example 1

[0031] Figure 2 A longitudinal cross-sectional schematic diagram of a high-voltage process without an N-type buried layer and without epitaxy is provided in an embodiment of the present invention, such as Figure 2 As shown, the source P active area and the back gate N active area of ​​the high-voltage power PMOS tube are short-circuited together by metal as the input end; the outermost source of the high-voltage power PMOS tube is used as the emitter, the back gate of the high-voltage power PMOS tube is used as the base, and the P-type substrate of the high-voltage power PMOS tube externally grounded is used as the collector. The parasitic PNP tube with a large area of ​​base and emitter short-circuited is used to provide ESD protection for the input end of the high-voltage power PMOS tube to the ground.

[0032] The high-voltage power PMOS tube is divided into a central high-voltage PMOS tube and a peripheral parasitic PNP tube.

[0033] Peripheral parasitic PNP tubes, including:

[0034] P-type substrate 101;

[0035] The first deep P-well region 111 is located on the P-type substrate 101

[0036] A first deep N-well region 112 located on the P-type substrate 101;

[0037] A first P-well region 121 located in the first deep P-well region 111;

[0038] A first heavily doped P-type active region 131 located in the first P-well region 121;

[0039] A first N-well region 122 located in the first deep N-well region 112;

[0040] A first heavily doped N-type active region 132 located in the first N-well region 122;

[0041] A second N-well region 123 located in the first deep N-well region 112;

[0042] A second heavily doped P-type active region 133 a located in the first deep N-well region 112 and overlapping with the second N-well region 123 ;

[0043] An oxide layer 141 located between the first heavily doped P-type active region 131 and the first heavily doped N-type active region 132;

[0044] An oxide layer 142 located between the first heavily doped N-type active region 132 and the second heavily doped P-type active region 133a;

[0045] The peripheral parasitic PNP tubes are located on both sides of the high-voltage power PMOS tube.

[0046] Central high voltage PMOS tube, including:

[0047] P-type substrate 101;

[0048] A first deep N-well region 112 located on the P-type substrate 101;

[0049] A second N-well region 123 located in the first deep N-well region 112;

[0050] A first P-type drift region 124 located in the first deep N-well region 112;

[0051] a third N-well region 125 located in the first deep N-well region 112;

[0052] A third heavily doped P-type active region 133 b located in the second N-well region 123 ;

[0053] a fourth heavily doped P-type active region 134 located in the first P-type drift region 124;

[0054] a fifth heavily doped P-type active region 135 located in the third N-well region 125;

[0055] The oxide layer 143 on the left side and the oxide layer 144 on the right side of the fourth heavily doped P-type active region 134 in the first P-type drift region 124;

[0056] A first gate oxide layer 151 located on the silicon surface of the second N-well region 123, the first P-type drift region 124 and the oxide layer 143;

[0057] A second gate oxide layer 152 located on the third N-well region 125 , the first P-type drift region 124 , and the silicon surface of the oxide layer 144 ;

[0058] A first polysilicon gate 161 located on the first gate oxide layer 151;

[0059] A second polysilicon gate 162 located on the second gate oxide layer 152;

[0060] The central high-voltage PMOS tube is located at the center of the high-voltage power PMOS tube as a repeated unit array.

[0061] The first heavily doped P-type active region 131 is connected to the ground through a metal line and serves as a collector of the parasitic PNP;

[0062] The first heavily doped N-type active region 132, the second heavily doped P-type active region 133a, the third heavily doped P-type active region 133b and the fifth heavily doped P-type active region 135 are connected to the input terminal through metal wires;

[0063] The first heavily doped N-type active region 132 serves as the base of the parasitic PNP transistor, the second heavily doped P-type active region 133a, and the third heavily doped P-type active region 133b serve as the emitter of the parasitic PNP transistor;

[0064] The first heavily doped N-type active region 132 also serves as the back gate of the high-voltage PMOS tube, the second heavily doped P-type active region 133a, the third heavily doped P-type active region 133b and the fifth heavily doped P-type active region 135 also serve as the source of the high-voltage PMOS tube;

[0065] The first polysilicon gate 161 and the second polysilicon gate 162 are connected to other devices inside the integrated circuit through metal wires;

[0066] The first polysilicon gate 161 and the second polysilicon gate 162 serve as gates of the high-voltage PMOS tube;

[0067] The fourth heavily doped P-type active region 134 is connected to other devices inside the integrated circuit through metal wires;

[0068] The fourth heavily doped P-type active region 134 serves as the drain of the high-voltage PMOS tube;

[0069] Example 2

[0070] Figure 3 A longitudinal cross-sectional schematic diagram of an N-type buried layer epitaxial high pressure process provided by an embodiment of the present invention is shown in FIG. Figure 3As shown, the source P active area and the back gate N active area of ​​the high-voltage power PMOS tube are short-circuited together by metal as the input end; the outermost source of the high-voltage power PMOS tube is used as the emitter, the back gate of the high-voltage power PMOS tube is used as the base, and the P-type substrate of the high-voltage power PMOS tube externally grounded is used as the collector. The parasitic PNP tube with a large area of ​​base and emitter short-circuited is used to provide ESD protection for the input end of the high-voltage power PMOS tube to the ground.

[0071] The high-voltage power PMOS tube is divided into a central high-voltage PMOS tube and a peripheral parasitic PNP tube.

[0072] Peripheral parasitic PNP tubes, including:

[0073] P-type substrate 101;

[0074] The first deep P-well region 111 is located on the P-type substrate 101

[0075] A first N buried layer region 113 located on the P substrate 101;

[0076] A first deep N-well region 112 located on the P-type substrate 101;

[0077] A first P-well region 121 located in the first deep P-well region 111;

[0078] A first heavily doped P-type active region 131 located in the first P-well region 121;

[0079] A first N-well region 122 located in the first deep N-well region 112;

[0080] A first heavily doped N-type active region 132 located in the first N-well region 122;

[0081] A second N-well region 123 located in the first deep N-well region 112;

[0082] A second heavily doped P-type active region 133 a located in the first deep N-well region 112 and overlapping with the second N-well region 123 ;

[0083] An oxide layer 141 located between the first heavily doped P-type active region 131 and the first heavily doped N-type active region 132;

[0084] An oxide layer 142 located between the first heavily doped N-type active region 132 and the second heavily doped P-type active region 133a;

[0085] The peripheral parasitic PNP tubes are located on both sides of the high-voltage power PMOS tube.

[0086] Central high voltage PMOS tube, including:

[0087] P-type substrate 101;

[0088] A first deep N-well region 112 located on the P-type substrate 101;

[0089] A second N-well region 123 located in the first deep N-well region 112;

[0090] A first P-type drift region 124 located in the first deep N-well region 112;

[0091] a third N-well region 125 located in the first deep N-well region 112;

[0092] A third heavily doped P-type active region 133 b located in the second N-well region 123 ;

[0093] a fourth heavily doped P-type active region 134 located in the first P-type drift region 124;

[0094] a fifth heavily doped P-type active region 135 located in the third N-well region 125;

[0095] The oxide layer 143 on the left side and the oxide layer 144 on the right side of the fourth heavily doped P-type active region 134 in the first P-type drift region 124;

[0096] A first gate oxide layer 151 located on the silicon surface of the second N-well region 123, the first P-type drift region 124 and the oxide layer 143;

[0097] A second gate oxide layer 152 located on the third N-well region 125 , the first P-type drift region 124 , and the silicon surface of the oxide layer 144 ;

[0098] A first polysilicon gate 161 located on the first gate oxide layer 151;

[0099] A second polysilicon gate 162 located on the second gate oxide layer 152;

[0100] The central high-voltage PMOS tube is located at the center of the high-voltage power PMOS tube as a repeated unit array.

[0101] The first heavily doped P-type active region 131 is connected to the ground through a metal line and serves as a collector of the parasitic PNP;

[0102] The first heavily doped N-type active region 132, the second heavily doped P-type active region 133a, the third heavily doped P-type active region 133b and the fifth heavily doped P-type active region 135 are connected to the input terminal through metal wires;

[0103] The first heavily doped N-type active region 132 serves as the base of the parasitic PNP transistor, the second heavily doped P-type active region 133a, and the third heavily doped P-type active region 133b serve as the emitter of the parasitic PNP transistor;

[0104] The first heavily doped N-type active region 132 also serves as the back gate of the high-voltage PMOS tube, the second heavily doped P-type active region 133a, the third heavily doped P-type active region 133b and the fifth heavily doped P-type active region 135 also serve as the source of the high-voltage PMOS tube;

[0105] The first polysilicon gate 161 and the second polysilicon gate 162 are connected to other devices inside the integrated circuit through metal wires;

[0106] The first polysilicon gate 161 and the second polysilicon gate 162 serve as gates of the high-voltage PMOS tube;

[0107] The fourth heavily doped P-type active region 134 is connected to other devices inside the integrated circuit through metal wires;

[0108] The fourth heavily doped P-type active region 134 serves as the drain of the high-voltage PMOS tube;

[0109] The present invention can adjust the trigger voltage by adjusting the distance between the first N-well region 122 and the first heavily doped N-type active region 132 and the distance between the first N-well region 122 and the second N-well region 123, thereby meeting the design requirements of low trigger voltage and high holding voltage of high-voltage power PMOS tube. This adjustment method does not require the addition of additional ESD devices, but can be achieved by optimizing the existing structure, which greatly saves the production cost of the chip.

[0110] Compared with the prior art, the ESD structure based on the high-voltage power PMOS tube provided by the present invention has the following beneficial effects:

[0111] 1) The present invention cleverly utilizes the structural characteristics of the high-voltage power PMOS tube itself, uses its outermost source as the emitter, the back gate as the base, and the externally grounded P-type substrate as the collector, forming a large-area parasitic PNP tube. Under normal working conditions, the parasitic PNP tube is in a cut-off state and will not affect the normal function of the high-voltage power PMOS tube. When an electrostatic discharge (ESD) event occurs, the parasitic PNP tube can be quickly turned on, providing a low-resistance path from the source of the high-voltage power PMOS tube to the ground for the ESD current, thereby effectively protecting the high-voltage power PMOS tube from damage by ESD.

[0112] 2) The base concentration of the parasitic PNP tube has a direct impact on its base resistance. By adjusting the base concentration, the size of the base resistance can be changed. When the base resistance increases, the trigger voltage of the parasitic PNP tube will increase accordingly; conversely, when the base resistance decreases, the trigger voltage will decrease. Therefore, the present invention can adjust the trigger voltage by adjusting the distance between the shallow N well covering the back gate N active area and the distance between the back gate N active area and the source P active area of ​​the high-voltage power PMOS tube, thereby meeting the design requirements of low trigger voltage and high holding voltage of the high-voltage power PMOS tube. This adjustment method does not require the addition of additional ESD devices, and can be achieved only by optimizing the existing structure, which greatly saves the production cost of the chip.

[0113] 3) The present invention does not need to use additional high-voltage devices or stacked low-voltage devices as ESD protection devices for high-voltage PMOS pins to achieve ESD protection for high-voltage PMOS pins, and does not need to occupy an additional large chip area. For high-voltage PMOS pins, the utilization rate of chip area can be effectively improved, and chip cost can be reduced.

[0114] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An ESD structure based on a high voltage power PMOS tube, characterized in that: include: Parasitic PNP tube used for ESD protection from the input end to ground of high-voltage power PMOS tube; The parasitic PNP tube includes a source P active region of a high-voltage power PMOS tube as a base, an external P active region substrate grounding ring as a collector, and a back gate N active region ring of a high-voltage power PMOS tube as a base electrode; Wherein, under normal working conditions, the parasitic PNP tube is in a cut-off state; and when an electrostatic discharge event occurs, the parasitic PNP tube is turned on.

2. The ESD structure according to claim 1, characterized in that: The source P active region is located in the deep N well.

3. The ESD structure according to claim 2, characterized in that: The back gate N active region of the high voltage power PMOS tube is located in a shallow N well.

4. The ESD structure according to claim 3, characterized in that , the shallow N-well is located in the deep N-well.

5. The ESD structure according to claim 3, characterized in that: The source P active region and the back gate N active region are short-circuited by metal and are at the same potential.

6. The ESD structure according to claim 1, characterized in that: The back gate N active area ring is located between the source P active area and the external P active area substrate grounding ring.

7. The ESD structure according to claim 1, characterized in that: The back gate N active region ring is formed by a P well led out from the P active region.

8. The ESD structure according to claim 1, characterized in that: The trigger voltage of the parasitic PNP tube is adjusted by the distance between the shallow N well and the back gate N active area.

9. The ESD structure according to claim 1, characterized in that: The trigger voltage of the parasitic PNP transistor is adjusted by the distance between the back gate N active region and the source P active region.

10. The ESD structure according to claim 1, characterized in that: The trigger voltage of the parasitic PNP tube is adjusted by the distance between the shallow N well and the back gate N active area and the distance between the back gate N active area and the source P active area.

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