Floating gate injection type ferroelectric transistor and preparation method thereof

Abstract

The invention discloses a floating gate injection type ferroelectric transistor and a preparation method thereof, and belongs to the field of semiconductor devices. According to the device, a metal floating gate layer and a top injection layer structure are arranged between a ferroelectric polarization layer and a gate, programming operation is completed in a gate injection mode, charges are injected and stored in a metal floating gate in an FN tunneling mode, and the ferroelectric polarization layer completes polarization overturning under the action of the charges injected into the floating gate. The thin top injection layer design can obtain enough high transmission probability, so that the device can quickly complete charge injection under programming operation, and the programming time is shortened; after the voltage is removed, even if the charges in the floating gate are reversely tunneled away from the top gate, the ferroelectric material is reversed, and due to the polarization maintaining capability of the ferroelectric material, the device shows the nonvolatile storage characteristic. The thickness ratio of the interface silicon oxide layer to the ferroelectric polarization layer can be adjusted to realize rapid charge injection and rapid polarization flipping. Due to the excellent characteristics, the memory device can be used as a nonvolatile embedded memory device.

Description

Technical Field

[0001] The present invention belongs to the field of high-performance non-volatile memory devices for AI large models and machine learning, and specifically relates to a floating gate injection ferroelectric transistor with fast programming operation capability and a preparation method thereof. Background Art

[0002] In recent years, the demand for computing performance and energy consumption of large models such as artificial intelligence (AI) and machine learning (ML) has been growing, and high-performance embedded memory devices and computing architectures have continued to receive attention. Generally speaking, it is difficult for memory devices to balance speed and capacity. High-speed storage units such as static random access memory (SRAM) and dynamic random access memory (DRAM) have the characteristic that data will be lost after power failure; while large-capacity storage media such as flash memory (NAND FLASH) are difficult to balance the function of fast operation. DRAM, as a medium for data transmission and communication, is usually used as the main memory of the CPU. Its access speed has a great impact on the processing power of the CPU and the access speed of the memory. Therefore, research on the design of high-performance embedded memory structures has attracted much attention.

[0003] The conventional DRAM structure consists of a transistor + a capacitor (1T1C). Data is stored in the capacitor in the form of charge and read by connecting transistors in series. However, due to the natural charging and discharging of the capacitor, DRAM needs to be dynamically refreshed continuously to maintain data. Such a refresh operation brings additional power consumption, and its reading process is destructive reading. Compared with traditional DRAM, ferroelectric random access memory (FeRAM) can still maintain data after power failure, does not require periodic refresh, and thus reduces power consumption. In addition, the polarization storage charge is much higher than the charge that can be stored on the capacitor plate, which reduces the requirements for the capacitor aspect ratio. However, its disadvantages include the high coercive field of ferroelectric materials leading to higher operating voltages, and the polarization pulses on the capacitor plates reduce the access speed. Ferroelectric transistors (FeFETs), which also use ferroelectric materials, have good application potential in memory application scenarios such as NAND FLASH because they can achieve a larger storage window. However, its programming speed is significantly inferior to DRAM, so it is difficult to use as main memory. Therefore, how to achieve fast, low-power non-volatile storage is of great significance. Summary of the invention

[0004] In view of the above problems, the object of the present invention is to provide a floating gate injection type ferroelectric memory device with non-volatility, fast writing speed and lossless reading and a preparation method thereof.

[0005] The general FeRAM structure is implemented through a 1T-1C architecture, in which a non-volatile ferroelectric capacitor (FeCAP) is selected as the capacitor, and the "write 0" and "write 1" operations are performed on the capacitor through a transistor. In the traditional 1T-1C FeRAM, reading the stored polarization charge switches the polarization state and generates a switching current. Similar destructive reading processes require a write-back operation after each read to restore the polarization, so the ferroelectric material needs to have almost unlimited durability. In addition, the charge-sensing-based 1T-1C FeRAM readout introduces DRAM scaling issues because the charge is negligible. The reading of FeFET is based on the change of the threshold voltage due to the inversion of the channel, and the channel current is obtained by applying a voltage to the drain, so the reading process can be regarded as a lossless operation.

[0006] The present invention provides a floating gate injection type ferroelectric transistor, which has a structure similar to that of FeFET, and completes programming operation by gate injection. Charges are injected and stored in a metal floating gate by FN tunneling, and the ferroelectric polarization layer completes polarization reversal under the action of charges injected by the floating gate. The thin gate injection layer design can obtain a sufficiently high transmission probability, so that the device can complete rapid charge injection, reducing the programming time. After the voltage is removed, even if the charge in the floating gate reversely tunnels away from the top gate, the ferroelectric material has completed the reversal, and the device exhibits non-volatile storage characteristics. Rapid charge injection and rapid polarization reversal can be achieved by adjusting the thickness ratio of the interface silicon oxide layer and the ferroelectric polarization layer.

[0007] Specifically, the present invention provides a floating gate injection ferroelectric transistor for non-volatile embedded storage, comprising a semiconductor substrate, a nanowire channel region, a source region, a drain region, an interlayer dielectric, a gate, an isolation layer and a metal lead-out layer, wherein the semiconductor substrate is an SOI substrate, the source region, the drain region and the nanowire channel region connecting the two are formed on the SOI substrate, the interlayer dielectric and the gate are above the nanowire channel region, and the isolation layer covers the surface of the synaptic transistor device; the metal lead-out layer forms metal lead-out lines connected to the source region, the drain region and the gate through through holes; it is characterized in that the interlayer dielectric comprises an interface oxide layer, a ferroelectric polarization layer, a metal floating gate layer and a top injection layer stacked in sequence on the nanowire channel region, wherein the thickness of the top injection layer is 2~4 nm, and the thickness ratio of the interface oxide layer to the ferroelectric polarization layer is 1:4~1:5.

[0008] In the above-mentioned floating gate injection ferroelectric transistor for non-volatile embedded storage, the material of the interface oxide layer is preferably silicon oxide (SiO2) or the like, and the thickness is preferably 1 to 2 nm.

[0009] In the above floating gate injection type ferroelectric transistor for non-volatile embedded storage, the material of the ferroelectric polarization layer is preferably hafnium zirconium oxide, and its thickness is about 7-8 nm.

[0010] In the above floating gate injection ferroelectric transistor for non-volatile embedded storage, the metal floating gate layer material located above the ferroelectric polarization layer is preferably titanium nitride, and its thickness is about 3-4 nm.

[0011] In the above floating gate injection type ferroelectric transistor for non-volatile embedded storage, the material of the top injection layer between the metal floating gate layer and the gate is preferably aluminum oxide or silicon oxide, with a thickness of 2-4 nm.

[0012] In the above-mentioned floating gate injection ferroelectric transistor for non-volatile embedded storage, the material of the gate is preferably titanium nitride (TiN), tantalum nitride (TaN), etc., and the thickness is preferably 50-100 nm.

[0013] The present invention also provides a method for preparing the above floating gate injection type ferroelectric transistor, comprising the following steps: 1) Using photolithography technology to pattern and etch a silicon nanowire channel region and a source region and a drain region connecting the two ends thereof, respectively, on an SOI substrate to obtain a dumbbell-shaped silicon structure, and then doping and annealing the source region and the drain region; 2) forming an interfacial oxide layer on the surface of the dumbbell-shaped silicon structure by oxidation; 3) Depositing a ferroelectric polarization layer, a metal floating gate layer and a top injection layer on the interface oxide layer in sequence; 4) Deposit metal gate material, form the gate through photolithography definition and etching, and complete ferroelectric activation annealing; 5) Deposit an isolation layer and planarize the surface, and then make metal leads for the source, drain and gate.

[0014] The above step 1) specifically includes: 1a) Spin-coating an inorganic negative photoresist, such as HSQ (HydrogenSilsesquioxane) electron beam glue containing hydrogen silicate, on the SOI substrate, and then patterning the inorganic negative photoresist as a nanowire hard mask by electron beam lithography; 1b) Spin-coating an organic positive photoresist and patterning the organic positive photoresist as a source and drain mask by photolithography technology; 1c) Using the nanowire hard mask (inorganic glue) and the source and drain mask (organic glue) as a mixed mask, anisotropically etch silicon to form a dumbbell-shaped silicon structure; 1d) Remove the source and drain masks, retain the nanowire hard mask, heavily dope the source and drain using ion implantation technology, then remove the nanowire hard mask using wet etching, and anneal to activate the source and drain impurities.

[0015] The annealing method may be one of rapid thermal annealing (RTA), laser annealing, flash annealing and spike annealing.

[0016] The oxidation method in the above step 2) can be dry oxygen oxidation or hydrogen-oxygen synthesis oxidation.

[0017] In the above step 3), the deposition method of the ferroelectric polarization layer, the metal floating gate layer and the top injection layer can be atomic layer deposition (ALD).

[0018] The metal gate material in the above step 4) can be deposited by physical vapor deposition (PVD) such as magnetron sputtering and metal evaporation.

[0019] In the above step 5), silicon oxide is preferably deposited as an isolation layer, and the deposition method may be low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD) etc. The planarization method is preferably chemical mechanical polishing (CMP).

[0020] In the above step 6), when making the metal lead of the source, drain and gate, first use the photolithography technology to define and etch the through holes of the source, drain and gate, then deposit metal to fill them, and after surface flattening, use the photolithography technology to define the metal lead line, etch the metal layer to the isolation layer to form the metal lead.

[0021] Furthermore, the photolithography technology used in the above preparation method is a photolithography technology that can define nanoscale, such as 193 nm ultraviolet photolithography technology; the etching technology used can be reactive ion etching (RIE) and inductively coupled plasma etching (ICPE) and other methods.

[0022] The advantages and positive effects of the present invention are as follows: 1) The floating gate injection type ferroelectric transistor proposed in the present invention has a metal floating gate and a floating gate top injection layer structure, and uses gate injection to complete programming operations. Charges are injected and stored in the metal floating gate by FN tunneling, which promotes the ferroelectric material to complete polarization reversal; 2) The thin top injection layer design can obtain a sufficiently high transmission probability, so that the device can quickly complete the charge injection under the programming operation, reducing the programming time and programming voltage; 3) After the voltage is removed, even if the charge in the floating gate tunnels away from the top gate in the reverse direction, the ferroelectric material has completed the inversion. Due to its polarization retention ability, the device exhibits non-volatile storage characteristics and has the ability to read without loss. 4) By adjusting the thickness ratio and number of the interface oxide layer and the ferroelectric polarization layer, rapid charge injection and rapid polarization reversal can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1-Figure 8 The present invention is a schematic diagram of the key process steps of the floating gate injection type ferroelectric transistor for fast programming operation. In each figure, (a) is a top view of the device, (b) is a cross-sectional view of the device along the A-A' direction of (a), and (c) is a cross-sectional view of the device along the B-B' direction of (a). Among them: Figure 1 The SOI substrate after spin coating of HSQ glue; Figure 2 Defining nanowire masks by electron beam lithography; Figure 3 To define the source and drain mask by using optical lithography technology, and to etch the source and drain and nanowire channel structure of dumbbell structure as a mixed mask with the nanowire mask; Figure 4 To generate an interface oxide layer by thermal oxidation, a ferroelectric polarization layer, a metal floating gate layer, a top implantation layer and a titanium nitride gate electrode layer are sequentially deposited; Figure 5 To define the gate electrode using photolithography technology, the gate electrode is etched to the top implantation layer; Figure 6 For depositing a silicon oxide isolation layer; Figure 7 Etching through holes to the source-drain silicon interface and the gate electrode surface; Figure 8 To deposit the metal layer, planarize it, and pattern it to form metal lead lines.

[0024] Fig. 9 for Figure 1 to Figure 8 Illustration of the materials used. DETAILED DESCRIPTION

[0025] The present invention will be described in detail below through specific examples in conjunction with the accompanying drawings.

[0026] like Figures 1 to 8 As shown, a floating gate injection type ferroelectric transistor is prepared according to the following steps: 1) Thin the silicon film of the SOI substrate. The specific operation method is to oxidize the surface silicon film with dry oxygen or hydrogen and oxygen to form a silicon oxide film, and then rinse the surface silicon oxide film with a hydrofluoric acid solution, and then spin-coat the HSQ glue, such as Figure 1 As shown; 2) Use electron beam lithography technology to define the nanowire mask. The width of the nanowire mask is the line width of the silicon nanowire channel formed later, such as Figure 2 As shown; 3) Use photolithography technology to define the source and drain mask, and form a mixed exposure mask with the hard mask above the nanowires to form a dumbbell-shaped structure, and then dry-etch to form a dumbbell-shaped structure, such as Figure 3 As shown; remove the organic mask above the source and drain, retain the inorganic hard mask above the silicon nanowire, heavily dope the source and drain through ion implantation technology, then remove the inorganic hard mask through wet etching, and activate the source and drain impurities through rapid thermal annealing; 4) A 2 nm thick silicon oxide film is generated on the surface of the silicon nanowire channel by thermal oxidation to form an interface oxide layer, and then a 7 nm thick ferroelectric polarization layer is deposited by atomic layer deposition (ALD). Then, a 3 nm thick titanium nitride is deposited by atomic layer deposition (ALD) to form a metal floating gate layer and a 3 nm thick silicon oxide is deposited to form a top injection layer. Finally, a 100 nm thick titanium nitride film is deposited by magnetron sputtering. Figure 4 As shown; 5) Use photolithography to define the gate electrode, use photoresist as a mask, and use inductively coupled plasma etching (ICPE) to etch the titanium nitride film to the top injection layer. The top injection layer is appropriately overetched to prevent metal short circuits, such as Figure 5 As shown; followed by ferroelectric activation annealing; 6) Use low-pressure chemical vapor deposition to deposit a 200 nm thick silicon oxide isolation layer, and use chemical mechanical polishing (CMP) to flatten the surface, such as Figure 6 As shown; 7) Use photolithography technology to define the through holes above the source, drain and gate. Use photoresist as a mask and use dry etching technology to etch away the silicon oxide isolation layer and interlayer dielectric in the source and drain through holes, as well as the silicon oxide isolation layer in the gate through hole. Figure 7 As shown; 8) Use magnetron sputtering to deposit metal titanium (adhesion layer) and metal aluminum to fill the through holes and form a metal film, use chemical mechanical polishing (CMP) to flatten the surface, use photolithography technology to define the metal lead wires, and use ICP to etch the metal layer to the silicon oxide isolation layer, such as Figure 8 shown.

[0027] The embodiments of the present invention are not intended to limit the present invention. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A floating gate injection ferroelectric transistor, comprising a semiconductor substrate, a nanowire channel region, a source region, a drain region, an interlayer dielectric, a gate, an isolation layer and a metal lead-out layer, wherein: The semiconductor substrate is an SOI substrate, the source region, the drain region and the nanowire channel region connecting the two are formed on the SOI substrate, the interlayer dielectric and the gate are above the nanowire channel region, and the isolation layer covers the surface of the device; the metal lead layer forms metal lead wires connected to the source region, the drain region and the gate through through holes; it is characterized in that the interlayer dielectric includes an interface oxide layer, a ferroelectric polarization layer, a metal floating gate layer and a top injection layer stacked in sequence on the nanowire channel region, wherein the thickness of the top injection layer is 2~4 nm, and the thickness ratio of the interface oxide layer to the ferroelectric polarization layer is 1:4~1:

5.

2. The floating gate injection type ferroelectric transistor according to claim 1, characterized in that: The material of the interface oxide layer is silicon oxide, and the thickness is 1-2 nm.

3. The floating gate injection type ferroelectric transistor according to claim 1, characterized in that: The ferroelectric polarization layer material is hafnium zirconium oxide, and its thickness is 7-8 nm.

4. The floating gate injection type ferroelectric transistor according to claim 1, wherein: The metal floating gate layer is made of titanium nitride and has a thickness of 3-4 nm.

5. The floating gate injection type ferroelectric transistor according to claim 1, wherein: The material of the top injection layer is aluminum oxide or silicon oxide.

6. The floating gate injection type ferroelectric transistor according to claim 1, wherein: The gate is made of titanium nitride or tantalum nitride with a thickness of 50-100 nm.

7. The method for preparing a floating gate injection type ferroelectric transistor according to any one of claims 1 to 6, comprising the following steps: 1) Using photolithography technology to pattern and etch a silicon nanowire channel region and a source region and a drain region connecting the two ends thereof, respectively, on an SOI substrate to obtain a dumbbell-shaped silicon structure, and then doping and annealing the source region and the drain region; 2) forming an interfacial oxide layer on the surface of the dumbbell-shaped silicon structure by oxidation; 3) Depositing a ferroelectric polarization layer, a metal floating gate layer and a top injection layer on the interface oxide layer in sequence; 4) Deposition of metal gate material, forming the gate by photolithographic definition and etching, followed by ferroelectric activation annealing; 5) Deposit an isolation layer and planarize the surface, and then make metal leads for the source, drain and gate.

8. The preparation method according to claim 7, characterized in that: Step 1) includes: 1a) Spin-coating an inorganic negative photoresist on an SOI substrate and then patterning the inorganic negative photoresist as a nanowire hard mask by electron beam lithography; 1b) Spin-coating an organic positive photoresist and patterning the organic positive photoresist as a source and drain mask by photolithography technology; 1c) Using the nanowire hard mask and the source-drain mask as a hybrid mask, anisotropically etching silicon to form a dumbbell-shaped silicon structure; 1d) Remove the source and drain masks, retain the nanowire hard mask, heavily dope the source and drain using ion implantation technology, then remove the nanowire hard mask using wet etching, and anneal to activate the source and drain impurities.

9. The preparation method according to claim 7, characterized in that: The oxidation method in step 2) is dry oxygen oxidation or hydrogen-oxygen synthesis oxidation; in step 3), the ferroelectric polarization layer, the metal floating gate layer and the top injection layer are deposited by atomic layer deposition; in step 4), the metal gate material is deposited by magnetron sputtering or evaporation; in step 5), when making the metal lead of the source, drain and gate, first use the photolithography technology to define and etch the through holes of the source, drain and gate, and then deposit metal for filling. After the surface is flattened, the metal lead line is defined by the photolithography technology, and the metal layer is etched to the isolation layer to form the metal lead.

10. Application of the floating gate injection ferroelectric transistor according to any one of claims 1 to 6 as a non-volatile memory device for AI large models and machine learning.

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