A floating-gate injection type ferroelectric transistor and a preparation method thereof

Abstract

The present invention discloses a floating-gate injection type ferroelectric transistor and a preparation method thereof, belonging to the field of semiconductor devices. This device has a metal floating-gate layer and a top injection layer structure between the ferroelectric polarization layer and the gate electrode, and the programming operation is completed by means of gate injection. Charges are injected and stored in the metal floating-gate through FN tunneling, and the ferroelectric polarization layer completes polarization reversal under the action of the charges injected into the floating-gate. The design of the thin top injection layer can obtain a sufficiently high transmission probability, enabling the device to quickly complete the injection of charges during the programming operation and reducing the programming time. After the voltage is removed, even if the charges in the floating-gate tunnel back from the top gate electrode, the ferroelectric material has completed inversion, and due to its polarization retention ability, the device exhibits non-volatile storage characteristics. By adjusting the thickness ratio of the interface silicon oxide layer to the ferroelectric polarization layer, rapid charge injection and rapid polarization reversal can be achieved. These excellent characteristics enable it to be used as a non-volatile embedded storage device.

Description

Technical Field

[0001] The present invention belongs to the field of high-performance non-volatile storage devices for AI large models and machine learning, and particularly relates to a floating-gate injection type ferroelectric transistor with fast programming operation ability and a preparation method thereof. Background Art

[0002] In recent years, the demand for computing performance and energy consumption of large models such as artificial intelligence (AI) and machine learning (ML) has been increasing day by day, and high-performance embedded storage devices and computing architectures have been continuously attracting attention. Generally, it is usually difficult for storage devices to balance speed and capacity. High-speed storage units such as static random access memory (SRAM) and dynamic random access memory (DRAM) both have the characteristic that data will be lost after power-off; while large-capacity storage media such as flash memory (NAND FLASH) are difficult to balance the function of fast operation. As a medium for data transmission and communication, DRAM is usually used as the main memory of the CPU, and its access speed has a great impact on the processing ability of the CPU and the access speed of the memory. Therefore, the research on the design of high-performance embedded memory structures has attracted much attention.

[0003] The conventional DRAM structure consists of a transistor + a capacitor (1T1C). Data is stored in the capacitor in the form of charge, and the read operation is performed in series through the transistor. However, due to the natural charge and discharge phenomenon of the capacitor, DRAM needs to be continuously refreshed dynamically to maintain data. Such a refresh operation brings additional power consumption, and its read process is a destructive read. Compared with traditional DRAM, ferroelectric random access memory (FeRAM) can still retain data after power-off and does not require periodic refreshing, thus reducing power consumption. Moreover, the polarization storage charge is much higher than the charge that can be stored on the capacitor plate, thus reducing the requirement for the aspect ratio of the capacitor. However, its disadvantages include that the high coercive field of the ferroelectric material will lead to a higher working voltage, and the polarization pulse on the capacitor plate will reduce the access speed. And the ferroelectric transistor (FeFET) that also uses ferroelectric materials has good application potential in memory application scenarios such as NAND FLASH because it can achieve a large storage window. However, its programming speed shows an obvious disadvantage compared with DRAM, so it is difficult to be used as the main memory. Therefore, how to achieve fast low-power non-volatile storage is of great significance. Summary of the Invention

[0004] Aiming at the above problems, the purpose of the present invention is to provide a floating-gate injection type ferroelectric storage device with non-volatility, fast writing speed and non-destructive reading, and a preparation method thereof.

[0005] A general FeRAM structure is implemented through a 1T-1C architecture, where the capacitor is a ferroelectric capacitor (FeCAP) with non-volatility. The operations of "writing 0" and "writing 1" to the capacitor are performed through a transistor. In a traditional 1T-1C FeRAM, reading the stored polarization charge will switch the polarization state and generate a switching current. A similar destructive reading process requires a write-back operation after each reading to restore the polarization. Therefore, almost infinite durability of the ferroelectric material is required. In addition, the 1T-1C FeRAM readout based on charge sensing introduces the scaling problem of DRAM due to negligible charge. While the reading of FeFET is based on the inversion of the channel, which changes the threshold voltage, and a channel current is obtained by applying a voltage at the drain end. Therefore, the reading process can be regarded as a non-destructive operation.

[0006] The present invention provides a floating-gate injection type ferroelectric transistor, whose structure is similar to that of FeFET. The programming operation is completed through gate injection. Charge is injected and stored in the metal floating gate in the way of FN tunneling. The ferroelectric polarization layer completes polarization inversion under the action of the charge injected into the floating gate. The design of a thin gate injection layer can obtain a sufficiently high transmission probability, enabling the device to complete rapid charge injection, reducing the programming time. After the voltage is removed, even if the charge in the floating gate tunnels back from the top gate, the ferroelectric material has completed inversion, and the device exhibits non-volatile storage characteristics. By adjusting the thickness ratio of the interfacial silicon oxide layer to the ferroelectric polarization layer, rapid charge injection and rapid polarization inversion can be achieved.

[0007] Specifically, a floating-gate injection type ferroelectric transistor for non-volatile embedded storage provided by the present invention includes a semiconductor substrate, a nanowire channel region, a source region, a drain region, an interlayer dielectric, a gate, an isolation layer, and a metal lead-out layer. Among them, the semiconductor substrate is a SOI substrate. The source region, the drain region, and the nanowire channel region connecting the two are formed on the SOI substrate. Above the nanowire channel region are the interlayer dielectric and the gate. The isolation layer covers the surface of the synaptic transistor device; the metal lead-out layer forms metal lead-out wires connected to the source region, the drain region, and the gate respectively through vias; its characteristic lies in that the interlayer dielectric includes an interfacial oxide layer, a ferroelectric polarization layer, a metal floating gate layer, and a top injection layer stacked in sequence above the nanowire channel region, where the thickness of the top injection layer is 2-4 nm, and the thickness ratio of the interfacial oxide layer to the ferroelectric polarization layer is 1:4-1:5.

[0008] In the above floating-gate injection type ferroelectric transistor for non-volatile embedded storage, the material of the interfacial oxide layer is preferably silicon oxide (SiO2), etc., and the thickness is preferably 1-2 nm.

[0009] In the above-mentioned floating-gate injection type ferroelectric transistor for non-volatile embedded memory, the ferroelectric polarization layer material is preferably hafnium zirconium oxide, and its thickness is about 7-8 nm.

[0010] In the above-mentioned floating-gate injection type ferroelectric transistor for non-volatile embedded memory, the metal floating-gate layer material located above the ferroelectric polarization layer is preferably titanium nitride, and its thickness is about 3-4 nm.

[0011] In the above-mentioned floating-gate injection type ferroelectric transistor for non-volatile embedded memory, the material of the top injection layer between the metal floating-gate layer and the gate is preferably alumina or silicon oxide, and the thickness is 2-4 nm.

[0012] In the above-mentioned floating-gate injection type ferroelectric transistor for non-volatile embedded memory, the material of the gate is preferably titanium nitride (TiN), tantalum nitride (TaN), etc., and the thickness is preferably 50-100 nm.

[0013] The present invention also provides a preparation method of the above-mentioned floating-gate injection type ferroelectric transistor, including the following steps:

[0014] 1) Use photolithography technology on the SOI substrate to pattern and etch to form a silicon nanowire channel region and source and drain regions respectively connected to both ends thereof, obtain a dumbbell-shaped silicon structure, and dope and anneal the source and drain regions;

[0015] 2) Form an interface oxide layer on the surface of the dumbbell-shaped silicon structure by oxidation;

[0016] 3) Deposit a ferroelectric polarization layer, a metal floating-gate layer and a top injection layer in sequence on the interface oxide layer;

[0017] 4) Deposit a metal gate material, define and etch through photolithography to form a gate, and complete ferroelectric activation annealing;

[0018] 5) Deposit an isolation layer and planarize the surface, and then fabricate metal leads for the source, drain and gate.

[0019] The above step 1) specifically includes:

[0020] 1a) Spin-coat an inorganic negative photoresist, such as HSQ (HydrogenSilsesquioxane) electron beam resist containing hydrogen silicate, on the SOI substrate, and then pattern the inorganic negative photoresist as a nanowire hard mask through electron beam lithography technology;

[0021] 1b) Spin-coat an organic positive photoresist, and pattern the organic positive photoresist as a source / drain mask through photolithography technology;

[0022] 1c) Use the nanowire hard mask (inorganic resist) and the source / drain mask (organic resist) as a combined mask, and anisotropically etch silicon to form a dumbbell-shaped silicon structure;

[0023] 1d) Remove the source-drain mask, retain the nanowire hard mask, perform heavy doping on the source-drain by ion implantation technology, then wet-etch to remove the nanowire hard mask, and anneal to activate the source-drain impurities.

[0024] Among them, the annealing method can be one of rapid thermal annealing (RTA), laser annealing, flash annealing, and spike annealing.

[0025] In the above step 2), the oxidation method can be dry oxidation or hydrogen-oxygen synthesis oxidation.

[0026] In the above step 3), the deposition methods of the ferroelectric polarization layer, the metal floating gate layer, and the top injection layer can choose atomic layer deposition (ALD).

[0027] In the above step 4), the deposition method of the metal gate material can adopt physical vapor deposition (PVD) methods such as magnetron sputtering and metal evaporation deposition.

[0028] In the above step 5), it is preferred to deposit silicon oxide as the isolation layer, and the deposition methods can adopt methods such as low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD). The planarization method is preferably chemical mechanical polishing (CMP).

[0029] In the above step 6), when making the metal leads of the source-drain and gate, first use photolithography technology to define and etch through holes for the source-drain and gate, then deposit metal for filling, and after surface planarization, define the metal lead wires by photolithography technology, and etch the metal layer to the isolation layer to form the metal leads.

[0030] Furthermore, the photolithography technology adopted in the above preparation method is a photolithography technology such as 193 nm ultraviolet photolithography technology that can define nanoscale; the etching technology adopted can be methods such as reactive ion etching (RIE) and inductively coupled plasma etching (ICPE).

[0031] The advantages and positive effects of the present invention are as follows:

[0032] 1) The floating-gate injection type ferroelectric transistor proposed by the present invention has a metal floating gate and a floating-gate top injection layer structure. The programming operation is completed by means of gate injection. Charges are injected and stored in the metal floating gate through FN tunneling, promoting the polarization reversal of the ferroelectric material.

[0033] 2) The design of the thin top injection layer can obtain a high enough transmission probability, enabling the device to quickly complete the injection of charges under the programming operation, reducing the programming time and programming voltage.

[0034] 3) After the voltage is removed, even if the charges in the floating gate tunnel back from the top gate, the ferroelectric material has already been reversed. Due to its polarization retention ability, the device exhibits non-volatile storage characteristics and has the ability of lossless reading.

[0035] 4) By adjusting the thickness ratio and number of layers of the interface oxide layer and the ferroelectric polarization layer, rapid charge injection and rapid polarization reversal can be achieved. Description of the Drawings

[0036] Figures 1 - 8 These are schematic diagrams of the key process steps of the floating-gate injection type ferroelectric transistor for rapid programming operation of the present invention. In each figure, (a) is a top view of the device, (b) is a cross-sectional view of the device along the A-A' direction of (a), and (c) is a cross-sectional view of the device along the B-B' direction of (a). Among them:

[0037] Figure 1 is the SOI substrate after spin-coating HSQ glue;

[0038] Figure 2 is to define the nanowire mask through electron beam lithography technology;

[0039] Figure 3 is to define the source-drain mask using optical lithography technology, and etch to form the source-drain and nanowire channel structures in a dumbbell shape with the nanowire mask as a hybrid mask;

[0040] Figure 4 is to thermally oxidize to generate the interface oxide layer, and sequentially deposit the ferroelectric polarization layer, metal floating gate layer, top injection layer, and titanium nitride gate electrode layer;

[0041] Figure 5 is to define the gate electrode using lithography technology and etch to form the gate electrode to the top injection layer;

[0042] Figure 6 is to deposit the silicon oxide isolation layer;

[0043] Figure 7 is to etch the via to the source-drain silicon interface and the surface of the gate electrode;

[0044] Figure 8 Deposit a metal layer, planarize it, and pattern it to form metal leads.

[0045] Figure 9 For Figures 1 - 8 Legend of the materials used in Specific implementation manners

[0046] The present invention will be described in detail below with reference to the accompanying drawings and through specific examples.

[0047] Such as Figures 1 through 8 shown, a floating gate injection type ferroelectric transistor is prepared according to the following steps:

[0048] 1) Thinning the silicon film of the SOI substrate. The specific operation method is to dry-oxidize or synthesize silicon on the surface with hydrogen and oxygen to form a silicon oxide film, and then wash away the surface silicon oxide film with a hydrofluoric acid solution, and then spin-coat HSQ glue, as Figure 1 shown;

[0049] 2) Define a nanowire mask using electron beam lithography technology. The width of the nanowire mask is the line width of the subsequent formed silicon nanowire channel, as Figure 2 shown;

[0050] 3) Define a source / drain mask using lithography technology, and form a hybrid exposure mask with a dumbbell structure together with the hard mask above the nanowire, and then dry-etch to form a dumbbell structure, as Figure 3 shown; Remove the organic mask above the source / drain, retain the inorganic hard mask above the silicon nanowire, heavily dope the source / drain by ion implantation technology, and then wet-etch to remove the inorganic hard mask, and perform rapid thermal annealing to activate the source / drain impurities;

[0051] 4) Generate a 2 nm thick silicon oxide film on the surface of the silicon nanowire channel by thermal oxidation to form an interface oxide layer, then deposit a 7 nm thick ferroelectric polarization layer by Atomic Layer Deposition (ALD) technology, then deposit a 3 nm thick titanium nitride by Atomic Layer Deposition (ALD) technology to form a metal floating gate layer and a 3 nm thick silicon oxide to form a top injection layer, and finally deposit a 100 nm thick titanium nitride film by Magnetron Sputtering technology, as Figure 4 shown;

[0052] 5) Define the gate electrode using photolithography technology. Using the photoresist as a mask, etch the titanium nitride film to the top injection layer by inductively coupled plasma etching (ICPE), and perform appropriate over-etching on the top injection layer to prevent metal short circuit, as Figure 5 shown; then perform ferroelectric activation annealing;

[0053] 6) Deposit a 200 nm thick silicon oxide isolation layer by low-pressure chemical vapor deposition, and perform surface planarization by chemical mechanical polishing (CMP), as Figure 6 shown;

[0054] 7) Define the vias above the source, drain, and gate using photolithography technology. Using the photoresist as a mask, etch away the silicon oxide isolation layer and the interlayer dielectric in the source-drain vias, and the silicon oxide isolation layer in the gate vias by dry etching technology, as Figure 7 shown;

[0055] 8) Deposit metal titanium (adhesion layer) and metal aluminum in sequence by magnetron sputtering to fill the vias and form a metal film, perform surface planarization by chemical mechanical polishing (CMP), define the metal lead-out line using photolithography technology, and etch the metal layer to the silicon oxide isolation layer by ICP, as Figure 8 shown.

[0056] The embodiments of the present invention are not intended to limit the present invention. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent embodiment with equivalent changes, without departing from the scope of the technical solution of the present invention. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A floating gate injection type ferroelectric transistor, comprising a semiconductor substrate, a nanowire channel region, a source region, a drain region, an interlayer dielectric, a gate, an isolation layer, and a metal lead-out layer, wherein, The semiconductor substrate is an SOI substrate. The source region, drain region, and the nanowire channel region connecting the two are formed on the SOI substrate. Above the nanowire channel region are the interlayer dielectric and the gate, and the isolation layer covers the surface of the device; the metal lead-out layer forms metal lead-out wires connected to the source region, drain region, and gate respectively through vias; it is characterized in that the interlayer dielectric includes an interface oxide layer, a ferroelectric polarization layer, a metal floating gate layer, and a top injection layer stacked in sequence above the nanowire channel region, wherein the material of the metal floating gate layer is titanium nitride; the material of the top injection layer is alumina or silicon oxide, and the thickness is 2 - 4 nm; the thickness ratio of the interface oxide layer to the ferroelectric polarization layer is 1:4 - 1:

5.

2. The floating gate injection type ferroelectric transistor according to claim 1, wherein The material of the interface oxide layer is silicon oxide, and the thickness is 1 - 2 nm.

3. The floating gate injection type ferroelectric transistor according to claim 1, wherein The material of the ferroelectric polarization layer is hafnium zirconium oxide, and its thickness is 7 - 8 nm.

4. The floating gate injection type ferroelectric transistor according to claim 1, wherein The thickness of the metal floating gate layer is 3 - 4 nm.

5. The floating gate injection type ferroelectric transistor according to claim 1, characterized in that, The material of the gate is titanium nitride or tantalum nitride, and the thickness is 50 - 100 nm.

6. The preparation method of the floating gate injection type ferroelectric transistor according to any one of claims 1 - 5, comprising the following steps: 1) On the SOI substrate, use photolithography technology to pattern and etch to form a silicon nanowire channel region and the source region and drain region respectively connecting its two ends, obtain a dumbbell-shaped silicon structure, and dope and anneal the source region and drain region; 2) Form an interface oxide layer on the surface of the dumbbell-shaped silicon structure by oxidation; 3) Deposit a ferroelectric polarization layer, a metal floating gate layer, and a top injection layer in sequence on the interface oxide layer; 4) Deposit a metal gate material, define and etch to form a gate through photolithography, and then perform ferroelectric activation annealing; 5) Deposit an isolation layer and planarize the surface, and then make the metal lead-outs of the source, drain, and gate.

7. The preparation method according to claim 6, characterized in that, Step 1) includes: 1a) Spin-coat an inorganic negative photoresist on the SOI substrate, and then pattern the inorganic negative photoresist as a nanowire hard mask through electron beam lithography technology; 1b) Spin-coat an organic positive photoresist, and pattern the organic positive photoresist as a source-drain mask through photolithography technology; 1c) Use the nanowire hard mask and the source-drain mask as a combined mask, and anisotropically etch silicon to form a dumbbell-shaped silicon structure; 1d) Remove the source-drain mask, retain the nanowire hard mask, perform heavy doping on the source and drain through ion implantation technology, then wet-etch to remove the nanowire hard mask, and anneal to activate the source-drain impurities.

8. The preparation method according to claim 6, characterized in that, The oxidation method in step 2) is dry oxygen oxidation or hydrogen oxygen synthesis oxidation; in step 3), atomic layer deposition is used to deposit the ferroelectric polarization layer, the metal floating gate layer, and the top injection layer; in step 4), magnetron sputtering or evaporation is used to deposit the metal gate material; in step 5), when making the metal lead-outs of the source, drain, and gate, first use photolithography technology to define and etch to form vias for the source, drain, and gate, then deposit metal for filling, and after surface planarization, define the metal lead-out wires through photolithography technology, and etch the metal layer to the isolation layer to form the metal lead-outs.

9. The application of the floating gate injection type ferroelectric transistor according to any one of claims 1 - 5 as a non-volatile memory device for AI large models and machine learning.

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