A SiC VDMOSFET device with a three-layer photomask and its manufacturing process

Abstract

The present invention relates to the field of MOS semiconductor technology, and discloses a SiC VDMOSFET device with three masks and its preparation process, which includes a plurality of MOS cells arranged side by side. Each MOS cell includes a drain, a semiconductor epitaxial layer, a metal gate, and a source. The semiconductor epitaxial layer includes an N substrate layer and an N drift layer. It is characterized in that: the metal gate includes an upper gate arranged longitudinally in the upper layer and a lower gate arranged transversely in the lower layer. By dividing the metal gate into an upper gate arranged longitudinally and a lower gate arranged transversely, and combining the P-well layer, P+-doped layer, N-well layer in the lateral source region and the upper P-well structure in the longitudinal source region, the present invention optimizes the electric field distribution and the carrier transmission path. This design improves the on-state efficiency of the device, reduces the leakage current, and at the same time enhances the breakdown voltage capability through the upper and lower partitioning of the N-well layer.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and particularly to a SiC VDMOSFET device with three-layer photomasks and its manufacturing process. Background Art

[0002] In the field of power electronics technology, due to the significant advantages of Si materials such as high reserves in nature, mature preparation and purification processes, stable single-crystal structures, high reliability, and low prices, Si-based power devices have always been the most important products in power electronic devices.

[0003] "Three-layer photomasks" refer to three photolithography steps, especially for the three-layer photolithography process of the gate and source. The manufacturing of SiCVDMOSFET usually requires multiple photolithography steps, but through process innovation, it can be reduced to three layers to reduce costs and improve yield.

[0004] A prior patent discloses a SiC VDMOSFET device and its manufacturing method (publication number CN118538611A), which relates to the field of semiconductor technology. In the SiC VDMOSFET device, the original gate is separated into two independent gates by metal. In the technology disclosed in this patent, the electric field is prone to concentration effect under high voltage conditions, which greatly reduces the breakdown voltage and anti-interference performance of the device. Summary of the Invention

[0005] The present invention provides a SiC VDMOSFET device with three-layer photomasks and its manufacturing process to solve the existing technical problems, and solves the problems in the above background art.

[0006] To solve the above technical problems, according to one aspect of the present invention, more specifically, a SiC VDMOSFET device with three-layer photomasks includes a plurality of MOS cells arranged in parallel. Each MOS cell includes a drain, a semiconductor epitaxial layer, a metal gate, and a source. The semiconductor epitaxial layer includes an N substrate layer and an N drift layer. It is characterized in that: the metal gate includes an upper gate arranged longitudinally in the upper layer and a lower gate arranged transversely in the lower layer;

[0007] A P-well layer, a P+ doped layer, and an N-well layer are formed in the lateral source region of a single MOS cell by ion implantation;

[0008] An upper P-well is formed by ion implantation inside the N-well layer in the longitudinal source region of a single MOS cell; wherein the upper P-well divides the N-well layer into an upper N-well and a lower N-well.

[0009] Further, a lower isolation cone, a first lower isolation ring, and a second lower isolation ring are sequentially formed by deposition from the inside out at the lower surface of the N substrate layer of a single MOS cell;

[0010] wherein the cross-sectional heights of the lower isolation cone, the first lower isolation ring, and the second lower isolation ring decrease in sequence.

[0011] Further, a doped cone is formed by ion implantation on the lower surface of the N substrate layer of a single MOS cell, wherein the doping concentration of the doped cone is lower than 2 to 3 times the doping concentration of the N drift layer.

[0012] Further, an upper isolation cone, a first upper isolation ring, and a second upper isolation ring are sequentially formed by ion implantation from the inside out in the upper region inside the N substrate layer of a single MOS cell;

[0013] wherein the cross-sectional heights of the upper isolation cone, the first upper isolation ring, and the second upper isolation ring increase in sequence.

[0014] A preparation process for a three-layer mask SiC VDMOSFET device includes the following steps:

[0015] S1. Perform the first layer of photolithography to define the source region, isolate the device region, and form MOS cells and a terminal protection region;

[0016] S2. Perform the second layer of photolithography to form the gate structure, and define the gate region to form a gate oxide layer and a metal gate;

[0017] S3. Perform the third layer of photolithography to make the source or the metal gate in contact and metallize it, thereby forming an ohmic contact of the source or the metal gate and completing the metal interconnection;

[0018] S4. Perform electrical performance detection on the SiC VDMOSFET device that has completed the metal interconnection, and package the devices that are initially detected to be qualified.

[0019] Further, in the step S4, according to the switching loss, turn-on delay time, and change amount of the on-resistance of the SiC VDMOSFET device, the electrical performance of the SiC VDMOSFET device is determined as follows:

[0020]

[0021] In the formula, h represents the performance coefficient of the detected SiC VDMOSFET device, e represents the energy loss amount when the detected device is turned on, t represents the turn-on delay time of the detected device, and r represents the resistance change amount of the detected device from 20 °C to 150 °C.

[0022] Further, when h≥46%, it indicates that the electrical performance of the device meets the initial detection requirements;

[0023] When h < 46%, it indicates that the electrical performance of the device does not meet the preliminary detection requirements.

[0024] A SiC VDMOSFET device with three-layer photomasks and its preparation process provided by the present invention. Compared with the prior art, the effects achieved by this method are as follows:

[0025] 1. In the present invention, the metal gate is divided into an upper gate arranged longitudinally and a lower gate arranged transversely, and combined with the P-well layer, P+-doped layer, N-well layer of the lateral source region and the upper P-well structure of the longitudinal source region, optimizing the electric field distribution and carrier transport path. This design improves the on-state efficiency of the device, reduces the leakage current, and at the same time enhances the breakdown voltage capability through the upper and lower partitioning of the N-well layer, being applicable to high-power scenarios.

[0026] 2. In the present invention, a lower isolation cone, a first lower isolation ring and a second lower isolation ring with gradually decreasing cross-sectional height are sequentially deposited on the lower surface of the N-substrate layer. This stepped isolation structure significantly improves the electrical isolation effect between different regions of the device, reduces the parasitic capacitance and leakage risk, thereby improving the stability and reliability of the device, especially showing better performance under high-voltage working conditions.

[0027] 3. In the present invention, a low-concentration doped cone (the concentration is 2-3 times lower than that of the N-drift layer) is implanted on the lower surface of the N-substrate layer, effectively adjusting the resistance gradient between the drift layer and the substrate. This improvement optimizes the current distribution, suppresses the formation of local hot spots, improves the heat dissipation performance of the device, and at the same time reduces the resistance change under high-temperature environments, enhancing the long-term working stability.

[0028] 4. In the present invention, an upper isolation cone, a first upper isolation ring and a second upper isolation ring with gradually increasing cross-sectional height are formed in the upper region inside the N-substrate layer. This structure further enhances the uniformity of the internal electric field distribution of the device, reduces the electric field concentration effect under high-voltage conditions, enhances the breakdown voltage capability and anti-interference performance of the device, and is applicable to harsh working conditions such as high frequency and high temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic structural diagram of the SiC VDMOSFET device in the present invention;

[0030] Figure 2 For the present invention Figure 1 Cross-sectional view of region A;

[0031] Figure 3 For the present invention Figure 1 Cross-sectional view of region B;

[0032] Figure 4 It is a schematic structural diagram of the second embodiment in the present invention;

[0033] Figure 5 For the present invention Figure 4 Cross-sectional view of region C in the present invention;

[0034] Figure 6 Schematic structural diagram of the third embodiment in the present invention;

[0035] Figure 7 Schematic structural diagram of the fourth embodiment in the present invention.

[0036] In the figure: 1, drain; 2, N substrate layer; 3, N drift layer; 4, metal gate; 5, source; 6, P-well layer; 7, P+ doping layer; 8, N-well layer; 9, lower isolation cone; 10, first lower isolation ring; 11, second lower isolation ring; 12, doping cone; 13, upper isolation cone; 14, first upper isolation ring; 15, second upper isolation ring; 41, upper gate; 42, lower gate; 61, upper P-well; 81, upper N-well; 82, lower N-well. Detailed implementation manners

[0037] To make the technical solution of the present invention clearer, the following further describes the present invention in detail with reference to the accompanying drawings and specific embodiments.

[0038] As Figure 1-7 shown, a manufacturing process of a three-mask SiC VDMOSFET device includes the following steps:

[0039] Step 1: Use the first lithography to define the source region, isolate the device region, and form MOS cells and terminal protection regions.

[0040] Step 2: Use the second lithography to form the gate structure, define the gate region to form the gate oxide layer and the metal gate 4.

[0041] Step 3: Use the third lithography to make the source 5 or the metal gate 4 in contact and metallize, thereby forming the ohmic contact of the source 5 or the metal gate 4 and completing the metal interconnection.

[0042] Step 4: Perform electrical performance detection on the SiC VDMOSFET device that has completed the metal interconnection, and package the devices that are initially detected to be qualified. According to the switching loss, turn-on delay time, and change in on-resistance of the SiC VDMOSFET device, the electrical performance of the SiC VDMOSFET device is determined as follows:

[0043]

[0044] In the formula, h represents the performance coefficient of the detected SiC VDMOSFET device, e represents the energy loss amount when the detected device is turned on, t represents the turn-on delay time of the detected device, and r represents the resistance change amount of the detected device from 20°C to 150°C.

[0045] When h≥46%, it indicates that the electrical performance of the device meets the preliminary detection requirements; when h<46%, it indicates that the electrical performance of the device does not meet the preliminary detection requirements.

[0046] Among them, the electrical performance of any SiC VDMOSFET device is detected. For the detected device, the energy loss during turn-on is taken as e = 160 (μJ), the turn-on delay time is taken as t = 22 (ns), and the resistance change amount of the detected device from 20°C to 150°C is taken as r = 20% (resistance change amount = (device resistance at 150°C - device resistance at 20°C) ÷ device resistance at 20°C × 100%). Then there is:

[0047]

[0048] It can be known from the above calculations that the performance coefficient of the detected SiC VDMOSFET device is h = 66.7%, so the electrical performance of the SiC VDMOSFET device meets the preliminary detection requirements.

[0049] Example 1

[0050] As Figure 1 -3 shows, according to one aspect of the present invention, a SiC VDMOSFET device with three-layer photomasks is provided, including a number of MOS cells arranged side by side. The MOS cell includes a drain 1, a semiconductor epitaxial layer, a metal gate 4, and a source 5. The semiconductor epitaxial layer includes an N substrate layer 2 and an N drift layer 3. The metal gate 4 includes an upper gate 41 arranged longitudinally in the upper layer and a lower gate 42 arranged horizontally in the lower layer; a P-well layer 6, a P+-doped layer 7, and an N-well layer 8 are formed in the lateral source region of a single MOS cell by ion implantation; an upper P-well 61 is formed by ion implantation inside the N-well layer 8 in the longitudinal source region of a single MOS cell; wherein the upper P-well 61 divides the N-well layer 8 into an upper N-well 81 and a lower N-well 82. By dividing the metal gate into an upper gate arranged longitudinally and a lower gate arranged horizontally, and combining the P-well layer, P+-doped layer, N-well layer in the lateral source region and the upper P-well structure in the longitudinal source region, the electric field distribution and the carrier transport path are optimized. This design improves the on-state efficiency of the device, reduces the leakage current, and at the same time enhances the breakdown voltage capability through the upper and lower partitioning of the N-well layer, and is suitable for high-power scenarios.

[0051] Example 2

[0052] As Figure 4 、 5As shown, a lower isolation cone 9, a first lower isolation ring 10, and a second lower isolation ring 11 are sequentially formed by deposition from the inside out at the lower surface of the N substrate layer 2 of a single MOS cell; among them, the cross-sectional heights of the lower isolation cone 9, the first lower isolation ring 10, and the second lower isolation ring 11 decrease in sequence. The lower isolation cone 9, the first lower isolation ring 10, and the second lower isolation ring 11 with decreasing cross-sectional heights are sequentially deposited on the lower surface of the N substrate layer 2. This stepped isolation structure significantly improves the electrical isolation effect between different regions of the device, reduces the parasitic capacitance and leakage risk, thereby improving the stability and reliability of the device, especially showing better performance under high-voltage working conditions.

[0053] Example 3

[0054] As Figure 6 shown, a doped cone 12 is formed by ion implantation on the lower surface of the N substrate layer 2 of a single MOS cell, where the doping concentration of the doped cone 12 is 2 to 3 times lower than the doping concentration of the N drift layer 3. By implanting a low-concentration doped cone 12 (with a concentration 2 to 3 times lower than that of the N drift layer 3) on the lower surface of the N substrate layer 2, the resistance gradient between the drift layer and the substrate is effectively adjusted. This improvement optimizes the current distribution, suppresses the formation of local hot spots, improves the heat dissipation performance of the device, and at the same time reduces the resistance change under high-temperature environments, enhancing the long-term working stability.

[0055] Example 4

[0056] As Figure 7 shown, an upper isolation cone 13, a first upper isolation ring 14, and a second upper isolation ring 15 are sequentially formed by ion implantation from the inside out in the upper layer region inside the N substrate layer 2 of a single MOS cell; among them, the cross-sectional heights of the upper isolation cone 13, the first upper isolation ring 14, and the second upper isolation ring 15 increase in sequence. The upper isolation cone 13, the first upper isolation ring 14, and the second upper isolation ring 15 with increasing cross-sectional heights are formed in the upper layer region inside the N substrate layer 2. This structure further strengthens the uniformity of the internal electric field distribution of the device, reduces the electric field concentration effect under high-voltage conditions, enhances the voltage withstand capacity and anti-interference performance of the device, and is suitable for harsh working conditions such as high frequency and high temperature.

[0057] The above-described embodiments merely represent several implementation manners of the present invention, and their descriptions are relatively specific and detailed, but should not be construed as limiting the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims

1. A SiC VDMOSFET device with a three-layer mask, comprising a plurality of MOS cells arranged side by side, each MOS cell including a drain (1), a semiconductor epitaxial layer, a metal gate (4), and a source (5), the semiconductor epitaxial layer including an N substrate layer (2) and an N drift layer (3), characterized in that: The metal gate (4) includes an upper gate (41) arranged longitudinally in the upper layer and a lower gate (42) arranged transversely in the lower layer; A P-well layer (6), a P+-doped layer (7), and an N-well layer (8) are formed in the lateral source region of a single MOS cell by ion implantation; An upper P-well (61) is formed by ion implantation inside the N-well layer (8) in the longitudinal source region of a single MOS cell; wherein the upper P-well (61) divides the N-well layer (8) into an upper N-well (81) and a lower N-well (82).

2. The SiC VDMOSFET device with a three-layer photomask according to claim 1, wherein: A lower isolation cone (9), a first lower isolation ring (10), and a second lower isolation ring (11) are sequentially formed by deposition from the inside out at the lower surface of the N-substrate layer (2) of a single MOS cell; Wherein the cross-sectional heights of the lower isolation cone (9), the first lower isolation ring (10), and the second lower isolation ring (11) decrease in sequence.

3. The SiC VDMOSFET device with a three-layer photomask according to claim 1, characterized in that: A doped cone (12) is formed by ion implantation at the lower surface of the N-substrate layer (2) of a single MOS cell, wherein the doping concentration of the doped cone (12) is lower than 2 to 3 times the doping concentration of the N-drift layer (3).

4. The SiC VDMOSFET device with a three-layer photomask according to claim 1, wherein: An upper isolation cone (13), a first upper isolation ring (14), and a second upper isolation ring (15) are sequentially formed by ion implantation from the inside out in the upper layer region inside the N-substrate layer (2) of a single MOS cell; Wherein the cross-sectional heights of the upper isolation cone (13), the first upper isolation ring (14), and the second upper isolation ring (15) increase in sequence.

5. A manufacturing process of a three-layer mask SiC VDMOSFET device, characterized in that, Applied to the SiC VDMOSFET device described in any one of claims 1-4, the manufacturing process of the SiC VDMOSFET device with three-layer photomasks includes the following steps: S1. The first layer of photolithography is used to define the source region, isolate the device region, and form MOS cells and terminal protection regions; S2. The second layer of photolithography is used to form the gate structure, define the gate region to form a gate oxide layer and a metal gate (4); S3. The third layer of photolithography is used to make the source electrode (5) or the metal gate (4) in contact and metallize, thereby forming an ohmic contact of the source electrode (5) or the metal gate (4) and completing metal interconnection; S4. Electrical performance detection is performed on the SiC VDMOSFET device that has completed metal interconnection, and the devices that are initially detected to be qualified are packaged.

6. The manufacturing process of the three-layer mask SiC VDMOSFET device according to claim 5, characterized in that: In the step S4, according to the switching loss, turn-on delay time, and change amount of the on-resistance of the SiC VDMOSFET device, the electrical performance of the SiC VDMOSFET device is determined as follows: In the formula, h represents the performance coefficient of the detected SiC VDMOSFET device, e represents the energy loss amount when the detected device is turned on, t represents the turn-on delay time of the detected device, and r represents the resistance change amount of the detected device from 20 °C to 150 °C.

7. The manufacturing process of the three-layer mask SiC VDMOSFET device according to claim 6, characterized in that: When h ≥ 46%, it indicates that the electrical performance of the device meets the initial detection requirements; When h < 46%, it indicates that the electrical performance of the device does not meet the initial detection requirements.

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