Integrated device and integrated passive device including magnetic material

Abstract

A device includes: a die substrate; a plurality of interconnects over the die substrate, wherein the plurality of interconnects are configured to operate as inductors; at least one magnetic layer surrounding at least a portion of the plurality of interconnects; and at least one dielectric layer surrounding the at least one magnetic layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional application S / N. 17 / 855,492 filed in the U.S. Patent Office on June 30, 2022, the entire contents of which are incorporated herein by reference as if fully set forth in its entirety below and for all applicable purposes.

[0003] field

[0004] Various features relate to packaging, integrated devices and / or integrated passive devices.

[0005] background

[0006] A package may include a substrate, an integrated device, and an integrated passive device. The substrate may include a plurality of interconnects. The integrated device and / or the integrated passive device may be coupled to the interconnects of the substrate. There is a need to provide a smaller package with improved performance.

[0007] Overview

[0008] Various features relate to packaging, integrated devices and / or integrated passive devices.

[0009] One example provides a device comprising: a die substrate; a plurality of interconnects over the die substrate, wherein the plurality of interconnects are configured to operate as an inductor; at least one magnetic layer surrounding at least a portion of the plurality of interconnects; and at least one dielectric layer surrounding the at least one magnetic layer.

[0010] Another example provides a device comprising: a die substrate; a plurality of interconnects over the die substrate, wherein the plurality of interconnects are configured to operate as inductors; at least one dielectric layer surrounding at least a portion of the plurality of interconnects; and at least one magnetic layer surrounding the at least one dielectric layer.

[0011] Another example provides a method, the method includes providing a tube core substrate. The method forms a plurality of interconnects located on the tube core substrate, wherein the plurality of interconnects are configured to operate as an inductor. The method forms at least one magnetic layer around at least a portion of the plurality of interconnects. The method forms at least one dielectric layer around the at least one magnetic layer.

[0012] Another example provides a method, the method includes providing a die substrate. The method forms a plurality of interconnects located on the die substrate, wherein the plurality of interconnects are configured to operate as inductors. The method forms at least one dielectric layer surrounding and contacting at least a portion of the plurality of interconnects. The method forms at least one magnetic layer surrounding and contacting the at least one dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Various features, characteristics and advantages will become apparent when the detailed description set forth below is read in conjunction with the accompanying drawings in which like reference numerals designate corresponding features throughout.

[0015] Figure 1 An exemplary cross-sectional view of a package including a substrate, an integrated device, and integrated passive devices is illustrated.

[0016] Figure 2 An exemplary cross-sectional view of an integrated passive device including magnetic material surrounding an interconnect is illustrated.

[0017] Figure 3 An exemplary plan view of an integrated passive device including magnetic material surrounding an interconnect is illustrated.

[0018] Figure 4 An exemplary cross-sectional view of an integrated passive device including magnetic material surrounding a dielectric layer around an interconnect is illustrated.

[0019] Figure 5 An exemplary plan view of an integrated passive device including magnetic material surrounding a dielectric layer around an interconnect is illustrated.

[0020] Figure 6 An exemplary cross-sectional view of an integrated device including magnetic material surrounding an interconnect is illustrated.

[0021] Figure 7 An exemplary cross-sectional view of an integrated device including a magnetic material surrounding a dielectric layer around an interconnect is illustrated.

[0022] Figure 8 An exemplary plan view of an integrated passive device including magnetic material surrounding an interconnect is illustrated.

[0023] Fig. 9 An exemplary plan view of an integrated passive device including magnetic material surrounding a dielectric layer around an interconnect is illustrated.

[0024] Figures 10A-10E An exemplary process for fabricating an integrated passive device including a magnetic material and a dielectric layer surrounding an interconnect is illustrated.

[0025] Fig.11 An exemplary flow chart of a method for fabricating an integrated passive device including a magnetic material surrounding a dielectric layer around an interconnect is illustrated.

[0026] Figures 12A-12E An exemplary process for fabricating an integrated device including a magnetic material surrounding an interconnect is illustrated.

[0027] Fig.13An exemplary flow chart of a method for fabricating an integrated device including a magnetic material surrounding an interconnect is illustrated.

[0028] Fig.14 Another exemplary flow chart of a method for fabricating an integrated device including a magnetic material is illustrated.

[0029] Fig.15 An exemplary flow chart of a method for fabricating a package including a substrate, an integrated device, and an integrated passive device is illustrated.

[0030] Fig.16 An exemplary flow chart of a method for fabricating a package including a substrate, an integrated device, and an integrated passive device is illustrated.

[0031] Fig.17 Various electronic devices are illustrated into which the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein may be integrated.

[0032] Detailed Description

[0033] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those of ordinary skill in the art that these aspects can be practiced without these specific details. For example, circuits may be shown with block diagrams to avoid burying these aspects in unnecessary details. In other examples, well-known circuits, structures, and techniques may not be shown in detail to avoid burying these aspects of the present disclosure.

[0034] The present disclosure describes a device comprising: a die substrate; a plurality of interconnects located on the die substrate, wherein the plurality of interconnects are configured to operate as an inductor; at least one magnetic layer surrounding at least a portion of the plurality of interconnects; and at least one dielectric layer surrounding the at least one magnetic layer. In some implementations, a device comprises: a die substrate; a plurality of interconnects located on the die substrate, wherein the plurality of interconnects are configured to operate as an inductor; at least one dielectric layer surrounding at least a portion of the plurality of interconnects; and at least one magnetic layer surrounding the at least one dielectric layer. The at least one magnetic layer comprises an insulating layer, a dielectric layer, and / or a non-conductive material. The at least one magnetic layer has a magnetic permeability value (e.g., a relative magnetic permeability value) greater than 1. The magnetic layer is configured to help improve (e.g., increase) the quality factor (Q) and / or inductance of the inductor. As will be further described below, by helping to improve the quality factor and / or inductance of an inductor, an inductor may be formed having a smaller form factor (e.g., size) while still having a quality factor and / or inductance that is equal to or better than that of a larger inductor.

[0035] Exemplary integrated devices including magnetic materials

[0036] Figure 1 A cross-sectional view of a package 100 is illustrated including a substrate 102, an integrated device 103, and an integrated passive device 105 (IPD). The package 100 is coupled to a board 106 through a plurality of solder interconnects 110. The board 106 includes at least one board dielectric layer 160 and a plurality of board interconnects 162. The board 106 may include a printed circuit board (PCB).

[0037] The substrate 102 includes at least one dielectric layer 120 (e.g., a substrate dielectric layer), a plurality of interconnects 122 (e.g., substrate interconnects), a solder mask 140, and a solder mask 142. The integrated device 103 may be coupled to the substrate 102 via a plurality of solder interconnects 130. The integrated device 103 may be coupled to the substrate 102 via a plurality of solder pillar interconnects 132 and a plurality of solder interconnects 130. The integrated passive device 105 may be coupled to the substrate 102 via a plurality of solder interconnects 150. The integrated passive device 105 may be coupled to the substrate 102 via a plurality of solder pillar interconnects 152 and a plurality of solder interconnects 150. The substrate may have a different number of metal layers. Different implementations may use different substrates. The substrate may include an embedded trace substrate (ETS). The at least one dielectric layer 120 may include a prepreg.

[0038] The package (e.g., 100) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The package (e.g., 100) may be configured to provide wireless fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The package (e.g., 100) may be configured to support a global system for mobile communications (GSM), a universal mobile telecommunications system (UMTS), and / or long term evolution (LTE). The package (e.g., 100) may be configured to transmit and receive signals having different frequencies and / or communication protocols.

[0039] As will be further described below, the integrated device 103 and / or the integrated passive device 105 may include at least one magnetic layer. The at least one magnetic layer is configured to improve the inductance and / or quality factor of an inductor located in and / or surrounded by the magnetic layer. With improved inductor performance, smaller and more compact inductors can be formed in the integrated device 103 and / or the integrated passive device 105. The magnetic layer and / or the dielectric layer can be configured to provide a coaxial interconnect.

[0040] Figure 2An exemplary cross-sectional profile view of an integrated passive device 201 is illustrated. The integrated passive device 201 includes a die substrate 200, a dielectric layer 210, a dielectric layer 220, a dielectric layer 230, a dielectric layer 250, a dielectric layer 260, at least one magnetic layer 240. The integrated passive device 201 may also include a plurality of interconnects 202. The plurality of interconnects 202 may include at least one interconnect 221, at least one interconnect 222, at least one interconnect 232, at least one interconnect 251, at least one interconnect 261, and / or at least one interconnect 262. As will be further described below, at least some of the interconnects from the plurality of interconnects 202 are configured to operate as inductors (e.g., solenoid inductors). The integrated passive device 201 may be an example of the integrated passive device 105.

[0041] The die substrate 200 may include silicon (Si). The die substrate 200 may include a wafer. The die substrate 200 may not have transistors. The dielectric layer 210 is coupled to the surface of the die substrate 200. The dielectric layer 210, the dielectric layer 220, the dielectric layer 230, the dielectric layer 250, and the dielectric layer 260 may be represented as one or more dielectric layers. Therefore, in some implementations, one dielectric layer may represent the dielectric layer 210, the dielectric layer 220, the dielectric layer 230, the dielectric layer 250, and / or the dielectric layer 260. In some implementations, two or more dielectric layers may represent the dielectric layer 210, the dielectric layer 220, the dielectric layer 230, the dielectric layer 250, and / or the dielectric layer 260. The dielectric layer 210, the dielectric layer 220, the dielectric layer 230, the dielectric layer 250, and / or the dielectric layer 260 may include one or more polyimides (PI). In some implementations, dielectric layer 260 can include a passivation layer.

[0042] The at least one interconnect 221 is located on the dielectric layer 210. The at least one interconnect 222 is coupled to the at least one interconnect 232 and the at least one interconnect 221. The at least one interconnect 232 is coupled to the at least one interconnect 251. The at least one interconnect 251 is coupled to the at least one interconnect 261. The at least one interconnect 261 is coupled to the at least one interconnect 262. The at least one interconnect 221, the at least one interconnect 222, the at least one interconnect 232, the at least one interconnect 251, and the at least one interconnect 261 may include copper. In some implementations, the at least one interconnect 262 may include nickel and / or gold. The at least one interconnect 221, the at least one interconnect 222, the at least one interconnect 232, the at least one interconnect 251, the at least one interconnect 261, and / or the at least one interconnect 262 may be configured to operate as an inductor (e.g., a solenoid inductor).

[0043] The plurality of interconnects 202 may include a plurality of metallized interconnects. That is, for example, in some implementations, at least some of the interconnects from the plurality of interconnects 202 may be implemented as a plurality of metallized interconnects. The plurality of metallized interconnects may include a plurality of redistribution interconnects (e.g., redistribution layer (RDL) interconnects). The at least one interconnect 232 includes an interconnect 232a and an interconnect 232b. The interconnect 232b is planar with the interconnect 232a. The interconnect 232a may be a through-hole interconnect (e.g., a first through-hole interconnect). The interconnect 232b may be a through-hole interconnect (e.g., a second through-hole interconnect).

[0044] As mentioned above, the integrated passive device 201 includes at least one magnetic layer 240. The at least one magnetic layer 240 may include one or more magnetic layers. The at least one magnetic layer 240 includes an insulating layer, a dielectric layer and / or a non-conductive material (e.g., a non-conductive material). The at least one magnetic layer 240 may be both a dielectric material and a magnetic material. Therefore, the at least one magnetic layer 240 may have both dielectric properties and magnetic properties. The at least one magnetic layer 240 may include one or more materials. The at least one magnetic layer 240 has a magnetic permeability value greater than 1 (e.g., about 10 or greater, ranging from 6-12). The magnetic layer 240 may have different magnetic permeability values ​​at different frequencies. As described in the present disclosure, the magnetic permeability value of the magnetic material and / or magnetic layer is a relative magnetic permeability value, which is defined as the ratio of the magnetic permeability of the material to the magnetic permeability of free space. Therefore, the permeability values ​​described for the magnetic materials and / or magnetic layers explained and / or described in the present disclosure may represent relative permeability values ​​relative to a defined permeability value of free space (e.g., a reference permeability value). In some implementations, free space may be defined as having a defined permeability value of μ0=4π×10-7H / m (henry per meter). Materials having relative permeability values ​​greater than 1 may be considered magnetic materials. Similarly, material layers having relative permeability values ​​greater than 1 may be considered magnetic layers. The at least one magnetic layer 240 may include a magnetic loss tangent value in the range of about 0.01-0.04. For example, the at least one magnetic layer may include a magnetic loss tangent value in the range of about 0.01-0.04 for frequencies up to 100 MHz. The at least one magnetic layer 240 may include various magnetic materials. For example, the at least one magnetic layer 240 may include an Ajinomoto magnetic film (AMF). The at least one magnetic layer 240 is configured to improve the inductance and / or quality factor of an inductor located in and / or surrounded by the at least one magnetic layer 240. With improved inductor performance, smaller and more compact inductors can be formed in integrated passive devices and / or integrated devices.

[0045] The at least one magnetic layer 240 includes a magnetic layer 240a (e.g., a first magnetic layer, a first magnetic layer portion) and a magnetic layer 240b (e.g., a second magnetic layer, a second magnetic layer portion). The magnetic layer 240a laterally surrounds and contacts the interconnect 232a. The magnetic layer 240b laterally surrounds and contacts the interconnect 232b. The dielectric layer 230 laterally surrounds and contacts the magnetic layer 240. For example, the dielectric layer 230 laterally surrounds and contacts the magnetic layer 240a and / or the magnetic layer 240b. A portion of the dielectric layer 230 is laterally located between the magnetic layer 240a and the magnetic layer 240b.

[0046] Using dielectric layer 230 to laterally surround magnetic layer 240a and magnetic layer 240b helps reduce leakage current that may occur due to one or more currents flowing through interconnect 232a and / or interconnect 232b. Thus, using dielectric layer 230 helps provide better isolation between one or more currents flowing through the interconnect.

[0047] Figure 3 2 illustrates a plan view of a cross section AA of a portion of the integrated passive device 201. Figure 3 As shown in , magnetic layer 240a laterally surrounds and contacts interconnect 232a, while magnetic layer 240b laterally surrounds and contacts interconnect 232b. In addition, dielectric layer 230 laterally surrounds and contacts magnetic layer 240a and magnetic layer 240b. Dielectric layer 230 may indirectly and laterally surround interconnect 232a and interconnect 232b. Figure 3 2, dielectric layer 230 does not contact the lateral sides of interconnect 232a and interconnect 232b. Note, however, that in some implementations, magnetic layer 240a and / or magnetic layer 240b may not completely surround the lateral sides of interconnect 232a and / or interconnect 232b. In this case, dielectric layer 230 may contact portions of the lateral sides of interconnect 232a and / or portions of the lateral sides of interconnect 232b.

[0048] Figure 4An exemplary cross-sectional profile view of an integrated passive device 401 is illustrated. The integrated passive device 401 includes a die substrate 200, a dielectric layer 210, a dielectric layer 220, a dielectric layer 230, a dielectric layer 250, a dielectric layer 260, and at least one magnetic layer 240. The dielectric layer 230 includes a dielectric layer 230a and a dielectric layer 230b. The integrated passive device 201 may also include a plurality of interconnects 202. The plurality of interconnects 202 may include at least one interconnect 221, at least one interconnect 222, at least one interconnect 232, at least one interconnect 251, at least one interconnect 261, and at least one interconnect 262. At least some of the interconnects from the plurality of interconnects 202 are configured to operate as inductors (e.g., solenoid inductors). For example, the at least one interconnect 221, the at least one interconnect 222, the at least one interconnect 232, the at least one interconnect 251, the at least one interconnect 261, and / or the at least one interconnect 262 may be configured to operate as an inductor (e.g., a solenoid inductor). The integrated passive device 401 may be an example of the integrated passive device 105. In some implementations, one dielectric layer may represent the dielectric layer 210, the dielectric layer 220, the dielectric layer 230 (which includes the dielectric layer 230a and the dielectric layer 230b), the dielectric layer 250, and / or the dielectric layer 260. In some implementations, two or more dielectric layers may represent the dielectric layer 210, the dielectric layer 220, the dielectric layer 230, the dielectric layer 250, and / or the dielectric layer 260.

[0049] Integrated passive device 401 is similar to integrated passive device 201. Thus, integrated passive device 401 may include interconnects configured in the same and / or similar manner as the interconnects from integrated passive device 201. Figure 4 As shown in FIG. 1 , dielectric layer 230a laterally surrounds and contacts interconnect 232a, while dielectric layer 230b laterally surrounds and contacts interconnect 232b. Magnetic layer 240 laterally surrounds and contacts dielectric layer 230a and dielectric layer 230b. A portion of magnetic layer 240 is laterally located between dielectric layer 230a and dielectric layer 230b. Dielectric layer 230a and / or dielectric layer 230b in combination with magnetic layer 240 help reduce leakage current that may occur due to one or more currents flowing through interconnect 232a and / or interconnect 232b.

[0050] Figure 5 4 illustrates a plan view of a cross section AA of a portion of an integrated passive device 401. Figure 5 As shown in , dielectric layer 230a laterally surrounds and contacts interconnect 232a, while dielectric layer 230b laterally surrounds and contacts interconnect 232b. In addition, magnetic layer 240 laterally surrounds and contacts dielectric layer 230a and dielectric layer 230b. Magnetic layer 240 may indirectly and laterally surround interconnect 232a and interconnect 232b. Figure 52, magnetic layer 240 does not contact the lateral sides of interconnect 232a and interconnect 232b. Note, however, that in some implementations, dielectric layer 230a and / or dielectric layer 230b may not completely surround the lateral sides of interconnect 232a and / or interconnect 232b. In this case, magnetic layer 240 may contact portions of the lateral sides of interconnect 232a and / or portions of the lateral sides of interconnect 232b.

[0051] Figure 6 An exemplary cross-sectional profile view of an integrated device 601 is illustrated. The integrated device 601 includes a die substrate 200, an active portion 602, a die interconnect portion 603, a dielectric layer 220, a dielectric layer 230, a dielectric layer 250, a dielectric layer 260, and at least one magnetic layer 240. The integrated device 601 may also include a plurality of interconnects 202. The plurality of interconnects 202 may include at least one interconnect 221, at least one interconnect 222, at least one interconnect 232, at least one interconnect 251, at least one interconnect 261, and at least one interconnect 262. At least some interconnects from the plurality of interconnects 202 are configured to operate as inductors (e.g., solenoid inductors). For example, the at least one interconnect 221, at least one interconnect 222, at least one interconnect 232, at least one interconnect 251, at least one interconnect 261, and / or at least one interconnect 262 may be configured to operate as inductors (e.g., solenoid inductors). The integrated device 601 may be an example of the integrated device 103.

[0052] The integrated device 601 is similar to the integrated passive device 201 in terms of using and having the magnetic layer 240. The integrated device 601 includes an active portion 602 and a die interconnect portion 603.

[0053] The active portion 602 is located in and on the die substrate 200. The active portion 602 may include at least a portion of the die substrate 200 and a plurality of transistors 620. The plurality of transistors 620 may be formed in and / or located in and / or on the die substrate 200. The die substrate 200 may include silicon (Si). The plurality of transistors 620 may form and / or define one or more logic blocks. The plurality of transistors 620 may be any type of transistor (e.g., CMOS transistors, planar transistors, field effect transistors). Note that the active portion 602 may include other components not shown.

[0054] The die interconnect portion 603 is coupled to the active portion 602, the die substrate 200, and the plurality of transistors 620. The die interconnect portion 603 includes at least one die dielectric layer (not shown) and a plurality of die interconnects (not shown). The plurality of die interconnects may be configured to be electrically coupled to the plurality of transistors 620. The die interconnect portion 603 includes a plurality of pad interconnects 632 and a dielectric layer 630. The plurality of pad interconnects 632 may be configured to be electrically coupled to the plurality of transistors 620 through the plurality of die interconnects (not shown) of the die interconnect portion 603. The plurality of pad interconnects 632 are coupled to the at least one interconnect 221. The dielectric layer 220 is located on the dielectric layer 630. The dielectric layer 630 may include a passivation layer.

[0055] Magnetic layer 240a laterally surrounds and contacts interconnect 232a, while magnetic layer 240b laterally surrounds and contacts interconnect 232b. In addition, dielectric layer 230 laterally surrounds and contacts magnetic layer 240a and magnetic layer 240b. Dielectric layer 230 may indirectly and laterally surround interconnect 232a and interconnect 232b. Figure 6 2, dielectric layer 230 does not contact the lateral sides of interconnect 232a and interconnect 232b. Note, however, that in some implementations, magnetic layer 240a and / or magnetic layer 240b may not completely surround the lateral sides of interconnect 232a and / or interconnect 232b. In this case, dielectric layer 230 may contact portions of the lateral sides of interconnect 232a and / or portions of the lateral sides of interconnect 232b.

[0056] Figure 7 An exemplary cross-sectional view of an integrated device 701 is illustrated. The integrated device 701 includes a die substrate 200, an active portion 602, a die interconnect portion 603, a dielectric layer 220, a dielectric layer 230, a dielectric layer 250, a dielectric layer 260, and at least one magnetic layer 240. The integrated device 601 may also include a plurality of interconnects 202. The plurality of interconnects 202 may include at least one interconnect 221, at least one interconnect 222, at least one interconnect 232, at least one interconnect 251, at least one interconnect 261, and at least one interconnect 262. At least some interconnects from the plurality of interconnects 202 are configured to operate as inductors (e.g., solenoid inductors). For example, the at least one interconnect 221, at least one interconnect 222, at least one interconnect 232, at least one interconnect 251, at least one interconnect 261, and / or at least one interconnect 262 may be configured to operate as inductors (e.g., solenoid inductors). The integrated device 701 may be an example of the integrated device 103.

[0057] The integrated device 701 is similar to the integrated passive device 401 in terms of using and having the magnetic layer 240. The integrated device 701 includes an active portion 602 and a die interconnect portion 603.

[0058] like Figure 7 As shown in FIG, dielectric layer 230a laterally surrounds and contacts interconnect 232a, while dielectric layer 230b laterally surrounds and contacts interconnect 232b. In addition, magnetic layer 240 laterally surrounds and contacts dielectric layer 230a and dielectric layer 230b. Magnetic layer 240 may indirectly and laterally surround interconnect 232a and interconnect 232b. A portion of magnetic layer 240 is laterally located between dielectric layer 230a and dielectric layer 230b. Figure 7 2, magnetic layer 240 does not contact the lateral sides of interconnect 232a and interconnect 232b. Note, however, that in some implementations, dielectric layer 230a and / or dielectric layer 230b may not completely surround the lateral sides of interconnect 232a and / or interconnect 232b. In this case, magnetic layer 240 may contact portions of the lateral sides of interconnect 232a and / or portions of the lateral sides of interconnect 232b.

[0059] Figure 8 A plan view of an integrated passive device 801 is illustrated. The integrated passive device 801 may be similar to the integrated passive device 201. The plan view of the integrated passive device 801 may span a cross section similar to the cross section AA of the integrated passive device 201. The integrated passive device 801 includes a plurality of interconnects 202, at least one dielectric layer 230, and at least one magnetic layer 240. The plurality of interconnects 202 include the plurality of interconnects 232, a plurality of interconnects 812, and a plurality of interconnects 814. The plurality of interconnects 232, the plurality of interconnects 812, and the plurality of interconnects 814 are configured to operate as inductors (e.g., solenoid inductors). The plurality of interconnects 232 are coupled (e.g., directly coupled, indirectly coupled) to the plurality of interconnects 812 and the plurality of interconnects 814. The plurality of interconnects 812 and / or the plurality of interconnects 814 may include pad interconnects and / or trace interconnects. The plurality of interconnects 232 may include one or more through-hole interconnects laterally surrounded by the magnetic layer 240. The magnetic layer 240 contacts the lateral sides of the plurality of interconnects 232. The dielectric layer 230 laterally surrounds and contacts the lateral sides of the magnetic layer 240. The plurality of interconnects 812 may be located on a first metal layer (e.g., a bottom metal layer) of the integrated passive device 801. The plurality of interconnects 814 may be located on a second metal layer (e.g., a top metal layer) of the integrated passive device 801. Thus, in one implementation, the plurality of interconnects 812 are located below the plurality of interconnects 232, and the plurality of interconnects 814 are located above the plurality of interconnects 232.

[0060] In some implementations, each interconnect from the plurality of interconnects 232 is laterally and completely surrounded by the magnetic layer 240. However, in some implementations, one or more interconnects from the plurality of interconnects 232 may be laterally and partially surrounded by the magnetic layer 240, such that the magnetic layer 240 contacts some but not all lateral sides of an interconnect from the plurality of interconnects 232. In some implementations, one or more interconnects from the plurality of interconnects 232 are not laterally surrounded by the magnetic layer 240, such that the magnetic layer 240 does not contact any portion of the lateral sides of an interconnect from the plurality of interconnects 232.

[0061] Note that the configuration of the integrated passive device 801 may be applicable to an integrated device including a plurality of transistors. For example, the configuration of the integrated passive device 801 may be applicable to the integrated device 601.

[0062] Fig. 9 A plan view of an integrated passive device 901 is illustrated. The integrated passive device 901 may be similar to the integrated passive device 401. The plan view of the integrated passive device 901 may span a cross section similar to the cross section AA of the integrated passive device 401. The integrated passive device 901 includes a plurality of interconnects 202, at least one dielectric layer 230, and at least one magnetic layer 240. The plurality of interconnects 202 include the plurality of interconnects 232, a plurality of interconnects 812, and a plurality of interconnects 814. The plurality of interconnects 232, the plurality of interconnects 812, and the plurality of interconnects 814 are configured to operate as inductors (e.g., solenoid inductors). The plurality of interconnects 232 are coupled (e.g., directly coupled, indirectly coupled) to the plurality of interconnects 812 and the plurality of interconnects 814. The plurality of interconnects 812 and / or the plurality of interconnects 814 may include pad interconnects and / or trace interconnects. The plurality of interconnects 232 may include one or more through-hole interconnects laterally surrounded by the dielectric layer 230. The dielectric layer 230 contacts the lateral sides of the plurality of interconnects 232. The magnetic layer 240 laterally surrounds and contacts the lateral sides of the dielectric layer 230. The plurality of interconnects 812 may be located on a first metal layer (e.g., a bottom metal layer) of the integrated passive device 901. The plurality of interconnects 814 may be located on a second metal layer (e.g., a top metal layer) of the integrated passive device 901. Thus, in one implementation, the plurality of interconnects 812 are located below the plurality of interconnects 232, and the plurality of interconnects 814 are located above the plurality of interconnects 232.

[0063] In some implementations, each interconnect from the plurality of interconnects 232 is laterally and completely surrounded by the dielectric layer 230. However, in some implementations, one or more interconnects from the plurality of interconnects 232 may be laterally and partially surrounded by the dielectric layer 230, such that the dielectric layer 230 contacts some but not all lateral sides of an interconnect from the plurality of interconnects 232. In some implementations, one or more interconnects from the plurality of interconnects 232 are not laterally surrounded by the dielectric layer 230, such that the dielectric layer 230 does not contact any portion of the lateral sides of an interconnect from the plurality of interconnects 232.

[0064] Note that the configuration of the integrated passive device 901 may be applicable to an integrated device including a plurality of transistors. For example, the configuration of the integrated passive device 901 may be applicable to the integrated device 701.

[0065] The integrated device (e.g., 103, 601, 701) may include a die (e.g., a bare semiconductor die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, an integrated device based on gallium arsenide (GaAs), a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or a combination thereof. The integrated device (e.g., 103, 601, 701) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. The integrated device may be an example of an electrical component and / or an electrical device. In some implementations, the integrated device may include a core particle. The core particles can be manufactured using a process that provides better yields than other processes used to manufacture other types of integrated devices, which can reduce the overall cost of manufacturing the core particles. Different core particles can have different sizes and / or shapes. Different core particles can be configured to provide different functions. Different core particles can have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several core particles can be used to perform the functionality of one or more chips (e.g., one or more integrated devices). Relative to using a single chip to perform all the functions of a package, using several core particles that perform several functions can reduce the overall cost of the package.

[0066] Having described various integrated devices and / or integrated passive devices having at least one magnetic layer, processes for fabricating an integrated device having at least one magnetic layer will now be described.

[0067] Exemplary process for making an integrated passive device including a magnetic layer

[0068] Figures 10A-10E Exemplary processes for providing or manufacturing an integrated passive device including at least one magnetic layer are illustrated. In some implementations, Figures 10A-10E The process may be used to provide or manufacture the integrated passive device 105 and / or the integrated passive device 401 described in the present disclosure. In some implementations, Figures 10A-10E The process may be used to provide or manufacture the integrated device 103 and / or the integrated device 701 described in the present disclosure.

[0069] It should be noted that Figures 10A-10E The processes of the present invention may combine one or more stages to simplify and / or clarify the processes for providing or manufacturing the integrated passive device. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of these processes may be replaced or substituted without departing from the spirit of the present disclosure. Different implementations may manufacture the integrated passive device differently. Figures 10A-10E The process shown in can be implemented on a wafer (eg, a silicon wafer) and then divided into several integrated passive devices. A similar approach can be implemented for integrated devices with a magnetic layer.

[0070] like Fig. 10A As shown in , stage 1 illustrates a state after providing a die substrate 200. The die substrate 200 may include silicon (Si). A dielectric layer 210 may be located on a surface of the die substrate 200. The die substrate 200 may be provided with a dielectric layer 210. In some implementations, the dielectric layer 210 may be formed on a surface of the die substrate 200. Providing the die substrate 200 may include providing a wafer (e.g., a silicon wafer). In some implementations, the die substrate 200 may be provided with a plurality of transistors.

[0071] Stage 2 illustrates a state after at least one interconnect 221 is formed over the dielectric layer 210. The at least one interconnect 221 may be formed using a plating process and a patterning process.

[0072] Stage 3 illustrates a state after forming and patterning at least one dielectric layer 220. The at least one dielectric layer 220 may be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. The at least one dielectric layer 220 may be formed over and around the at least one interconnect 221. The at least one dielectric layer 220 may include at least one through hole 1020.

[0073] like Fig. 10BAs shown in , stage 4 illustrates a state after forming at least one interconnect 222 and at least one interconnect 232. The at least one interconnect 222 and the at least one interconnect 232 may be formed using a plating process and a patterning process. Forming the at least one interconnect 222 may include forming a through-hole interconnect in the at least one through-hole 1020 of the at least one dielectric layer 220. The at least one interconnect 222 may be coupled to the at least one interconnect 221 and the at least one interconnect 232. The at least one interconnect 232 includes an interconnect 232a and an interconnect 232b. The width of the at least one interconnect 232 may be greater than the width of the at least one interconnect 222.

[0074] Stage 5 illustrates a state after at least one dielectric layer 230 is formed and patterned. The at least one dielectric layer 230 may be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. The at least one dielectric layer 230 may be formed on and around the at least one interconnect 232. The at least one dielectric layer 230 includes a dielectric layer 230a and a dielectric layer 230b. The at least one dielectric layer 230a laterally surrounds and contacts the interconnect 232a. The at least one dielectric layer 230a is located on the interconnect 232a. The at least one dielectric layer 230b laterally surrounds and contacts the interconnect 232b. The at least one dielectric layer 230b is located on the interconnect 232b.

[0075] like Fig. 10C As shown in FIG. 6 , stage 6 illustrates a state after forming a magnetic layer 240 over dielectric layer 220 and dielectric layer 230 (which includes dielectric layer 230a and dielectric layer 230b). A lamination process may be used to form magnetic layer 240. A printing process may be used to form a slurry of magnetic layer 240 over dielectric layer 220 and dielectric layer 230.

[0076] Stage 7 illustrates a state after portions of the magnetic layer 240 and portions of the dielectric layer 230 are removed. The portions of the magnetic layer 240 and portions of the dielectric layer 230 may be removed using a polishing process and / or a grinding process. Removing portions of the magnetic layer 240 and portions of the dielectric layer 230 exposes the at least one interconnect 232. Note that portions of the at least one interconnect 232 may also be removed by a polishing process and / or a grinding process.

[0077] like Fig. 10D , stage 8 illustrates a state after forming and patterning at least one dielectric layer 250. The at least one dielectric layer 250 may be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. The at least one dielectric layer 250 may be formed over and around the at least one interconnect 232, the dielectric layer 230, and the magnetic layer 240. The at least one dielectric layer 250 may include at least one through hole 1050.

[0078] Stage 9 illustrates a state after forming the at least one interconnect 251 and the at least one interconnect 261. The at least one interconnect 251 and the at least one interconnect 261 may be formed using a plating process and a patterning process. Forming the at least one interconnect 251 may include forming a through-hole interconnect in the at least one through-hole 1050 of the at least one dielectric layer 250. The at least one interconnect 251 may be coupled to the at least one interconnect 232 and the at least one interconnect 261.

[0079] like Fig. 10E As shown in FIG. 1 , stage 10 illustrates a state after forming the at least one interconnect 262. The at least one interconnect 262 may be formed using a plating process and a patterning process. The at least one interconnect 262 is formed and coupled to the at least one interconnect 261. The at least one interconnect 262 may include nickel and / or gold.

[0080] Stage 11 illustrates a state after forming and patterning at least one dielectric layer 260. The at least one dielectric layer 260 may be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. The at least one dielectric layer 260 may include at least one opening 1060 configured as an opening in the dielectric layer 260 and exposing the interconnect 261 and / or the interconnect 262. The solder interconnect may be configured to couple to the interconnect 262 and / or the interconnect 261 through the opening in the dielectric layer 260.

[0081] As mentioned above, the above process can be performed on a wafer (e.g., a silicon wafer) so that several integrated passive devices are formed simultaneously, and then the wafer is divided to form individual integrated passive devices including a magnetic layer. The above process can be manufactured in one facility or at several facilities. For example, when the wafer includes an active portion and an interconnect portion, a portion including a magnetic layer can be manufactured above the interconnect portion. A wafer including an active portion, an interconnect portion, and a magnetic layer can be divided to form several integrated devices.

[0082] Exemplary flow chart of a method for manufacturing an integrated passive device including a magnetic layer

[0083] In some implementations, fabricating an integrated device includes several processes. Fig.11 An exemplary flow chart of a method 1100 for providing or manufacturing an integrated passive device including at least one magnetic layer is illustrated. In some implementations, Fig.11 The method 1100 may be used to provide or manufacture the integrated passive device 105 and / or the integrated passive device 401. The method 1100 may be implemented on a wafer (eg, a silicon wafer) and then divided into several integrated passive devices.

[0084] It should be noted that Fig.11The method 1100 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing an integrated passive device. In some implementations, the order of the processes may be changed or modified. In addition, Fig.11 The method 1100 may be implemented to provide or manufacture an integrated device (eg, 103 ) having at least one magnetic layer.

[0085] The method provides (at 1105) a die substrate (e.g., 200). The die substrate 200 may include silicon (Si). The die substrate 200 may include a wafer (e.g., a silicon wafer). A dielectric layer may be formed and / or located on the die substrate 200. A plurality of transistors 620 may be formed in and / or on the die substrate 200. A plurality of logic blocks may be formed and / or defined by the plurality of transistors 620. When manufacturing integrated passive devices, the die substrate 200 may be free of the plurality of transistors (e.g., free of active devices). Fig. 10A Stage 1 of the present invention illustrates and describes an example of providing a die substrate.

[0086] The method forms (at 1110) a plurality of interconnects (e.g., 202) over a die substrate, wherein at least some of the plurality of interconnects (e.g., 202) are configured to operate as inductors. The at least one interconnect 202 may be formed using a plating process and a patterning process. The plurality of interconnects 202 may include the plurality of interconnects 232. The plurality of interconnects may be formed in and / or over at least one dielectric layer.

[0087] The method forms and patterns (at 1115) at least one dielectric layer (e.g., 220, 230, 250, 260). The at least one dielectric layer 230 may laterally surround and contact at least some of the interconnects from the plurality of interconnects 232. The at least one die dielectric layer (e.g., 220, 230, 250, 260) may be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. Note that the formation of the plurality of interconnects and the at least one dielectric layer may be performed iteratively. That is, a dielectric layer may be formed, followed by the formation of a plurality of interconnects, followed by the formation of another dielectric layer, and then another plurality of interconnects. Thus, the method of forming (at 1110) the plurality of interconnects and forming (at 1115) the at least one dielectric layer may be performed iteratively for as many layers as desired. In some implementations, a dielectric layer is formed, followed by the formation of the plurality of interconnects. At least one of the dielectric layers (eg, 230) is formed such that the dielectric layer (eg, 230) laterally surrounds and contacts at least some lateral sides from some of the plurality of interconnects. Fig. 10A Phase 2 to Fig. 10B Stage 5 and Fig. 10D Stage 8 to Fig. 10EStage 11 of the present invention illustrates and describes an example of forming a plurality of interconnects and forming at least one dielectric layer.

[0088] The method forms (at 1120) at least one magnetic layer (e.g., 240). A printing process that provides the magnetic layer as a slurry can be used to provide and form the at least one magnetic layer 240. The at least one magnetic layer 240 can be formed between when the plurality of interconnects are formed and when the at least one dielectric layer is formed. For example, the magnetic layer 240 can be formed after forming the at least one dielectric layer and forming the plurality of interconnects. In some implementations, once the magnetic layer 240 is formed, additional dielectric layers and additional plurality of interconnects can be formed. Fig. 10C Stages 6 and 7 of FIG. 1 illustrate and describe an example of forming a magnetic layer.

[0089] Exemplary process for making an integrated device including a magnetic layer

[0090] Figures 12A-12E Exemplary processes for providing or manufacturing an integrated device including at least one magnetic layer are described. In some implementations, Figures 12A-12E The process may be used to provide or manufacture the integrated device 103 and / or the integrated device 601 described in the present disclosure. In some implementations, Figures 12A-12E The process may be used to provide or manufacture the integrated passive device 105 and / or the integrated passive device 201 described in the present disclosure.

[0091] It should be noted that Figures 12A-12E The processes of the present invention may combine one or more stages to simplify and / or clarify the processes for providing or manufacturing an integrated device. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of these processes may be replaced or substituted without departing from the spirit of the present disclosure. Different implementations may manufacture integrated devices differently. Figures 12A-12E The process shown in can be implemented on a wafer (eg, a silicon wafer) and then divided into several integrated devices. A similar approach can be implemented for integrated passive devices with a magnetic layer.

[0092] like Fig. 12AAs shown in , stage 1 illustrates a state after providing a die substrate 200. The die substrate 200 may include silicon (Si). The die substrate 200 may be part of an integrated device (e.g., 601). The integrated device 601 may include the die substrate 200, an active portion 602, and a die interconnect portion 603. The active portion 602 may include a plurality of transistors 620. The die interconnect portion 603 is coupled to the active portion 602, the die substrate 200, and the plurality of transistors 620. The die interconnect portion 603 includes at least one die dielectric layer (not shown) and a plurality of die interconnects (not shown). The plurality of die interconnects may be configured to be electrically coupled to the plurality of transistors 620. The die interconnect portion 603 includes a plurality of pad interconnects 632 and a dielectric layer 630. The plurality of pad interconnects 632 may be configured to be electrically coupled to the plurality of transistors 620 through a plurality of die interconnects (not shown) of the die interconnect portion 603. The dielectric layer 630 may include a passivation layer. Stage 1 may illustrate a state after providing and / or manufacturing at least a portion of an integrated device.

[0093] Stage 2 illustrates a state after the at least one interconnect 221 is formed over the plurality of pad interconnects 632. The at least one interconnect 221 may be formed using a plating process and a patterning process. The at least one interconnect 221 is coupled to the plurality of pad interconnects 632.

[0094] Stage 3 illustrates a state after forming and patterning at least one dielectric layer 220. The at least one dielectric layer 220 may be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. The at least one dielectric layer 220 may be formed on and around the at least one interconnect 221. The at least one dielectric layer 220 may be formed on the dielectric layer 630. The at least one dielectric layer 220 may include at least one through hole 1020.

[0095] like Fig. 12B As shown in , stage 4 illustrates a state after forming the at least one interconnect 222 and the at least one interconnect 232. The at least one interconnect 222 and the at least one interconnect 232 may be formed using a plating process and a patterning process. Forming the at least one interconnect 222 may include forming a through-hole interconnect in the at least one through-hole 1020 of the at least one dielectric layer 220. The at least one interconnect 222 may be coupled to the at least one interconnect 221 and the at least one interconnect 232. The at least one interconnect 232 includes an interconnect 232a and an interconnect 232b. The width of the at least one interconnect 232 may be greater than the width of the at least one interconnect 222.

[0096] Stage 5 illustrates a state after at least one dielectric layer 230 is formed and patterned. The at least one dielectric layer 230 may be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. The at least one dielectric layer 230 may be formed on and around the at least one interconnect 232. A plurality of cavities 1230 are formed in the at least one dielectric layer 230. The plurality of cavities 1230 include cavities 1230a and cavities 1230b. Cavity 1230a laterally surrounds interconnect 232a. Cavity 1230b laterally surrounds interconnect 232b. Cavity 1230a may be formed so that interconnect 232a is located in cavity 1230a. Cavity 1230b may be formed so that interconnect 232b is located in cavity 1230b.

[0097] like Fig. 12C As shown in FIG. 6 , stage 6 illustrates a state after forming a magnetic layer 240 over the dielectric layer 220 and the dielectric layer 230. The magnetic layer 240 may be formed using a lamination process. A printing process may be used to form a slurry of the magnetic layer 240 over the dielectric layer 220 and the dielectric layer 230. The magnetic layer 240 may be formed in the plurality of cavities 1230. For example, the magnetic layer 240 may be formed in the cavity 1230a and the cavity 1230b of the dielectric layer 230. The magnetic layer 240 may laterally surround and contact the lateral side of the interconnect 232a and the lateral side of the interconnect 232b.

[0098] Stage 7 illustrates a state after portions of the magnetic layer 240 and portions of the dielectric layer 230 are removed. The portions of the magnetic layer 240 and portions of the dielectric layer 230 may be removed using a polishing process and / or a grinding process. Removing portions of the magnetic layer 240 and portions of the dielectric layer 230 exposes the at least one interconnect 232. Note that portions of the at least one interconnect 232 may also be removed by a polishing process and / or a grinding process.

[0099] like Fig.12D , stage 8 illustrates a state after forming and patterning at least one dielectric layer 250. The at least one dielectric layer 250 may be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. The at least one dielectric layer 250 may be formed over and around the at least one interconnect 232, the dielectric layer 230, and the magnetic layer 240. The at least one dielectric layer 250 may include at least one through hole 1250.

[0100] Stage 9 illustrates a state after forming the at least one interconnect 251 and the at least one interconnect 261. The at least one interconnect 251 and the at least one interconnect 261 may be formed using a plating process and a patterning process. Forming the at least one interconnect 251 may include forming a through-hole interconnect in the at least one through-hole 1250 of the at least one dielectric layer 250. The at least one interconnect 251 may be coupled to the at least one interconnect 232 and the at least one interconnect 261.

[0101] like Fig.12E As shown in FIG. 1 , stage 10 illustrates a state after forming the at least one interconnect 262. The at least one interconnect 262 may be formed using a plating process and a patterning process. The at least one interconnect 262 is formed and coupled to the at least one interconnect 261. The at least one interconnect 262 may include nickel and / or gold.

[0102] Stage 11 illustrates a state after forming and patterning at least one dielectric layer 260. The at least one dielectric layer 260 may be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. The at least one dielectric layer 260 may include at least one opening 1260 configured as an opening in the dielectric layer 260 and exposing the interconnect 261 and / or the interconnect 262. The solder interconnect may be configured to couple to the interconnect 262 and / or the interconnect 261 through the opening in the dielectric layer 260.

[0103] As mentioned above, the above process can be performed on a wafer (e.g., a silicon wafer) so that several integrated devices are formed simultaneously, and then the wafer is divided to form individual integrated devices including a magnetic layer. The above process can be manufactured in one facility or at several facilities. For example, when the wafer includes an active portion and an interconnection portion, a portion including a magnetic layer can be manufactured above the interconnection portion. A wafer including an active portion, an interconnection portion, and a magnetic layer can be divided to form several integrated devices.

[0104] Exemplary flow chart of a method for manufacturing an integrated device including a magnetic layer

[0105] In some implementations, fabricating an integrated device includes several processes. Fig.13 An exemplary flow chart of a method 1300 for providing or manufacturing an integrated device including at least one magnetic layer is illustrated. In some implementations, Fig.13 The method 1300 may be used to provide or manufacture the integrated device 103 and / or the integrated device 601. The method 1300 may be implemented on a wafer (eg, a silicon wafer) and then divided into several integrated devices.

[0106] It should be noted that Fig.11The method 1300 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing an integrated device. In some implementations, the order of the processes may be changed or modified. In addition, Fig.13 The method 1300 may be implemented to provide or manufacture an integrated passive device (eg, 105, 701) having at least one magnetic layer.

[0107] The method provides (at 1105) a die substrate (e.g., 200). The die substrate 200 may include silicon (Si). The die substrate 200 may include a wafer (e.g., a silicon wafer). A dielectric layer may be formed and / or located on the die substrate 200. A plurality of transistors 620 may be formed in and / or on the die substrate 200. A plurality of logic blocks may be formed and / or defined by the plurality of transistors 620. The die substrate 200 may be part of an integrated device including the die substrate 200, the active portion 602, and the die interconnect portion 603. When manufacturing an integrated passive device, the die substrate 200 may be free of the plurality of transistors (e.g., free of active devices). Fig. 12A An example of providing a die substrate is illustrated and described in Stage 1 of FIG. 1. In some implementations, providing a die substrate may include providing at least a portion of an integrated device.

[0108] The method forms (at 1310) a plurality of interconnects (e.g., 202) over a die substrate, wherein at least some of the plurality of interconnects (e.g., 202) are configured to operate as inductors. The at least one interconnect 202 may be formed using a plating process and a patterning process. The plurality of interconnects 202 may include the plurality of interconnects 232. The plurality of interconnects may be formed in and / or over at least one dielectric layer.

[0109] The method forms and patterns (at 1315) at least one dielectric layer (e.g., 220, 230, 250, 260). The at least one dielectric layer 230 may laterally surround and contact at least some of the interconnects from the plurality of interconnects 232. The at least one die dielectric layer (e.g., 220, 230, 250, 260) may be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. Note that the formation of the plurality of interconnects and the at least one dielectric layer may be performed iteratively. That is, a dielectric layer may be formed, followed by a plurality of interconnects, followed by another dielectric layer, and then another plurality of interconnects. Thus, the method of forming (at 1310) the plurality of interconnects and forming (at 1315) the at least one dielectric layer may be performed iteratively for as many layers as desired. In some implementations, a dielectric layer is formed, followed by the plurality of interconnects. The dielectric layer may be formed so that a portion of the dielectric layer may laterally surround and contact the at least one magnetic layer. Fig. 12A Phase 2 to Fig. 12B Stage 5 and Fig.12DStage 8 to Fig.12E Stage 11 of the present invention illustrates and describes an example of forming a plurality of interconnects and forming at least one dielectric layer.

[0110] The method forms (at 1320) at least one magnetic layer (e.g., 240). A printing process that provides the magnetic layer as a slurry may be used to provide and form the at least one magnetic layer 240. The magnetic layer 240 is formed such that the magnetic layer 240 laterally surrounds and contacts at least some lateral sides from some of the plurality of interconnects. The at least one magnetic layer 240 may be formed between when the plurality of interconnects are formed and when the at least one dielectric layer is formed. For example, the magnetic layer 240 may be formed after forming the at least one dielectric layer and forming the plurality of interconnects. In some implementations, once the magnetic layer 240 is formed, additional dielectric layers and additional plurality of interconnects may be formed. Fig. 12C Stages 6 and 7 of FIG. 1 illustrate and describe an example of forming a magnetic layer.

[0111] Exemplary flow chart of a method for manufacturing an integrated device including a magnetic layer

[0112] In some implementations, fabricating an integrated device includes several processes. Fig.14 An exemplary flow chart of a method 1400 for providing or manufacturing an integrated device including at least one magnetic layer is illustrated. In some implementations, Fig.14 The method 1400 may be used to provide or manufacture the integrated device 103. The method 1400 may be implemented on a wafer (eg, a silicon wafer) and then divided into several integrated devices.

[0113] It should be noted that Fig.14 The method 1400 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing an integrated device. For example, one or more processes of the method 1400 may include one or more processes of the method 1100 and / or the method 1300. In some implementations, the order of the processes may be changed or modified. In addition, Fig.14 The method 1400 may be implemented to provide or fabricate an integrated passive device (eg, 105 ) having at least one magnetic layer.

[0114] The method provides (at 1405) a die substrate (e.g., 200). The die substrate 200 may include silicon (Si). The die substrate 200 may include a wafer (e.g., a silicon wafer). A plurality of transistors 620 may be formed in and / or on the die substrate 200. A plurality of logic blocks may be formed and / or defined by the plurality of transistors 620. The die substrate 200 may be part of an active portion (e.g., 602) of an integrated device and / or define a portion of an active portion of an integrated device. When manufacturing an integrated passive device, the die substrate 200 may be free of the plurality of transistors (e.g., free of active devices).

[0115] The method forms (at 1410) a die interconnect portion (e.g., 603) over a die substrate (e.g., 200), wherein forming the die interconnect portion 603 includes forming at least one die dielectric layer and forming a plurality of die interconnects. The die interconnect portion 603 may be coupled to the die substrate 200. Forming the die interconnect portion 603 may include forming at least one die dielectric layer and forming and patterning at least one die interconnect.

[0116] The method forms (at 1415) a packaging portion over the die interconnect portion (eg, 603), wherein forming the packaging portion includes forming a plurality of interconnects coupled to the plurality of die interconnects, and forming at least one magnetic layer. The packaging portion may be coupled to the die interconnect portion 603.

[0117] Forming the package portion may include forming and patterning a plurality of interconnects (e.g., 202), forming a magnetic layer (e.g., 240, 240a, 240b), and forming at least one dielectric layer (e.g., 220, 230, 250, 260). The package portion may include an inductor defined by at least one interconnect from the plurality of interconnects (e.g., 202). The at least one magnetic layer includes an insulating layer, a dielectric layer, and / or a non-conductive material. The at least one magnetic layer has a magnetic permeability value (e.g., a relative magnetic permeability value) greater than 1.

[0118] In some implementations, the magnetic layer can laterally surround and contact one or more interconnects, and the at least one dielectric layer can laterally surround and contact the magnetic layer in a manner similar to that described for integrated device 601. In some implementations, the at least one dielectric layer can laterally surround and contact one or more interconnects, and the magnetic layer can laterally surround and contact the at least one dielectric layer in a manner similar to that described for integrated device 701.

[0119] The method 1400 may iteratively repeat the following processes for as many layers as desired: (i) forming and patterning interconnects and (ii) forming and polishing dielectric and / or magnetic layers.

[0120] As mentioned above, method 1400 may be performed on a wafer (eg, a silicon wafer) such that several integrated devices are formed simultaneously, and then the wafer may be singulated to form individual integrated devices including a magnetic layer.

[0121] Exemplary process for making a package including an integrated device and an integrated passive device

[0122] Fig.15 Exemplary processes for providing or manufacturing a package including an integrated device including a magnetic layer and / or an integrated passive device including a magnetic layer are described. In some implementations, Fig.15The process may be used to provide or manufacture a package 100 including an integrated device and / or an integrated passive device.

[0123] It should be noted that Fig.15 The process of one or more stages can be combined to simplify and / or clarify the process for providing or manufacturing a package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be replaced or substituted without departing from the scope of the present disclosure. Fig.15 The process can be used to manufacture one package or several packages at a time (as part of a wafer).

[0124] like Fig.15 As shown in , stage 1 illustrates a state after providing substrate 102. Substrate 102 can be provided by a supplier or manufactured. Substrate 102 includes at least one dielectric layer 120 and multiple interconnects 122, solder resist layer 140 and solder resist layer 142. Substrate 102 may include an embedded trace substrate (ETS). In some implementations, the at least one dielectric layer 120 may include (all) prepreg layers.

[0125] Stage 2 illustrates a state after the integrated device 103 is coupled to the first surface (e.g., top surface) of the substrate 102. The integrated device 103 may be coupled to the substrate 102 via a plurality of solder pillar interconnects 132 and a plurality of solder interconnects 130. In some implementations, the plurality of solder pillar interconnects 132 may be optional. The plurality of solder interconnects 130 are coupled to the plurality of interconnects 122. A solder reflow process may be used to couple the integrated device 103 to the plurality of interconnects 122 via the plurality of solder interconnects 130.

[0126] Stage 2 also illustrates a state after the integrated passive device 105 is coupled to the first surface (e.g., top surface) of the substrate 102. The integrated passive device 105 can be coupled to the substrate 102 through a plurality of solder pillar interconnects 152 and a plurality of solder interconnects 150. In some implementations, the plurality of solder pillar interconnects 152 can be optional. The plurality of solder interconnects 150 are coupled to the plurality of interconnects 122. A solder reflow process can be used to couple the integrated passive device 105 to the plurality of interconnects 122 through the plurality of solder interconnects 150.

[0127] Stage 3 illustrates a state after coupling the plurality of solder interconnects 110 to the substrate 102. The plurality of solder interconnects 110 may be coupled to interconnects located on the second surface of the at least one dielectric layer 120. A solder reflow process may be used to couple the plurality of solder interconnects 110 to the substrate 102. Stage 3 may illustrate the package 100. The packages (e.g., 100) described in the present disclosure may be manufactured one at a time, or may be manufactured together (as part of one or more wafers) and subsequently singulated into individual packages.

[0128] Exemplary flow chart of a method for manufacturing a package including an integrated device and an integrated passive device

[0129] In some implementations, fabricating a package including an integrated device including a magnetic layer and / or an integrated passive device including a magnetic layer includes several processes. Fig.16 An exemplary flow chart of a method 1600 for providing or manufacturing a package including an integrated device including a magnetic layer and / or an integrated passive device including a magnetic layer is illustrated. In some implementations, Fig.16 The method 1600 may be used to provide or manufacture the Figure 1 However, the method 1600 may be used to provide or manufacture any package described in the present disclosure.

[0130] It should be noted that Fig.16 The method may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package including an integrated device including a magnetic layer and / or an integrated passive device including a magnetic layer. In some implementations, the order of the processes may be changed or modified.

[0131] The method provides (at 1605) a substrate (e.g., 102). The substrate 102 may be provided by a supplier or fabricated. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include an embedded trace substrate (ETS). In some implementations, at least one dielectric layer 120 may include a prepreg layer. Fig.15 Stage 1 of the present invention illustrates and describes an example of providing a substrate having an escape interconnect.

[0132] The method (at 1610) couples at least one integrated device (e.g., 103) to a first surface of a substrate (e.g., 102). For example, the integrated device 103 can be coupled to the substrate 102 via a plurality of solder pillar interconnects 132 and a plurality of solder interconnects 130. The plurality of solder pillar interconnects 132 can be optional. The plurality of solder interconnects 130 are coupled to the plurality of interconnects 122. A solder reflow process can be used to couple the integrated device 103 to the plurality of interconnects via the plurality of solder interconnects 130.

[0133] The method also couples (at 1610) at least one integrated device (e.g., 105) to the first surface of the substrate (e.g., 102). For example, the integrated passive device 105 can be coupled to the substrate 102 via the plurality of solder pillar interconnects 152 and the plurality of solder interconnects 150. The plurality of solder pillar interconnects 152 can be optional. The plurality of solder interconnects 150 are coupled to the plurality of interconnects 122. A solder reflow process can be used to couple the integrated passive device 105 to the plurality of interconnects via the plurality of solder interconnects 150. Fig.15Stage 2 of the present invention illustrates and describes examples of integrated devices and integrated passive devices coupled to a substrate.

[0134] The method couples (at 1615) a plurality of solder interconnects (eg, 110) to a second surface of a substrate (eg, 102). A solder reflow process may be used to couple the plurality of solder interconnects 110 to the substrate. Fig.15 Stage 3 of the present invention illustrates and describes an example of coupling a solder interconnect to a substrate.

[0135] Exemplary Electronic Devices

[0136] Fig.17 Various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or systems-on-chip (SoC) are illustrated. For example, a mobile phone device 1702, a laptop computer device 1704, a fixed location terminal device 1706, a wearable device 1708, or a motor vehicle 1710 may include a device 1700 as described herein. The device 1700 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Fig.17 The devices 1702, 1704, 1706, and 1708, and the vehicle 1710 illustrated in the figure are merely exemplary. Other electronic devices can also feature the device 1700, including, but not limited to, a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), devices enabled with a global positioning system (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0137] Figure 1-9 , 10A-10E, 11, 12A-12E and / or 13-17, one or more of the components, processes, features and / or functions illustrated in the drawings may be rearranged and / or combined into a single component, process, feature or function, or implemented in several components, processes or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figure 1-9, 10A-10E, 11, 12A-12E, and / or 13-17 and their corresponding descriptions in this disclosure are not limited to die and / or IC. In some implementations, Figure 1-9 , 10A-10E, 11, 12A–12E, and / or 13-17 and their corresponding descriptions may be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat sink, and / or an interposer.

[0138] Note that the drawings in this disclosure may represent actual representations and / or conceptual representations of various components, assemblies, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, for clarity, not all components and / or parts are shown. In some instances, the positioning, location, size, and / or shape of the various components and / or assemblies in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0139] The wording "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any implementation or aspect described herein as "exemplary" is not necessarily to be interpreted as superior or superior to other aspects of the present disclosure. Likewise, the term "aspect" does not require that all aspects of the present disclosure include the discussed features, advantages, or modes of operation. The term "coupling" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered to be coupled to each other - even if they are not in direct physical contact with each other. The term "electrical coupling" may mean that two objects are directly or indirectly coupled together so that current (e.g., signal, power, ground) can be transferred between the two objects. Two electrically coupled objects may or may not have current transfer between the two objects. The use of the terms "first", "second", "third", and "fourth" (and / or anything higher than the fourth) is arbitrary. Any component described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may be a first component, a second component, a third component, or a fourth component. The term "encapsulation" means that an object may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be above a component located at the bottom. A top component may be considered a bottom component and vice versa. As described in the present disclosure, a first component located "above" a second component may mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of the second component, wherein the second surface is opposite to the first surface. Further note that the term "above" as used in the context of a component being located above another component in this application may be used to indicate that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, a first component is above a second component may mean: (1) the first component is above the second component, but not directly contacting the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component that is "in" a second component may be partially in the second component or completely in the second component. As used in this disclosure, the term "about 'value X'" or "approximately value X" means within ten percent of 'value X'. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0140] In some implementations, interconnection is an element or component that allows or facilitates electrical connection between two points, elements and / or components in a device or package. In some implementations, interconnection may include traces, through-holes, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnections. In some implementations, interconnection may include a conductive material that can be configured to provide an electrical path for a signal (e.g., a data signal), grounding, and / or power. Interconnection may include more than one element or component. Interconnection may be defined by one or more interconnections. Interconnection may include one or more metal layers. Interconnection may be part of a circuit. Different implementations may use different processes and / or procedures to form interconnection. In some implementations, chemical vapor deposition (CVD) processes, physical vapor deposition (PVD) processes, sputtering processes, spraying, and / or electroplating processes may be used to form interconnection.

[0141] It should also be noted that the various disclosures contained herein may be described as processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although a flow chart may describe an operation as a sequential process, many operations may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process terminates when its operations are completed.

[0142] Further examples are described below to facilitate understanding of the present disclosure.

[0143] Aspect: 1: A device includes: a die substrate; a plurality of interconnects located above the die substrate, wherein the plurality of interconnects are configured to operate as inductors; at least one magnetic layer surrounding at least a portion of the plurality of interconnects; and at least one dielectric layer surrounding the at least one magnetic layer.

[0144] Aspect: 2: A device as described in Aspect 1, wherein the multiple interconnects include a first through-hole interconnect and a second through-hole interconnect, and wherein the at least one magnetic layer includes a first magnetic layer that laterally surrounds and contacts the first through-hole interconnect, and a second magnetic layer that laterally surrounds and contacts the second through-hole interconnect.

[0145] Aspect: 3: A device as described in Aspect 2, wherein the at least one dielectric layer laterally surrounds the first magnetic layer and the second magnetic layer.

[0146] Aspect: 4: A device as described in aspects 2 to 3, wherein the first through-hole interconnection and the second through-hole interconnection are in a plane.

[0147] Aspect: 5: A device as described in aspects 1 to 4, wherein the at least one dielectric layer surrounds and contacts at least a portion of the plurality of interconnects.

[0148] Aspect: 6: The device as described in aspects 1 to 5 further includes a plurality of transistors located in the tube core substrate.

[0149] Aspect: 7: A device as described in aspects 1 to 6, wherein the at least one magnetic layer includes an insulating layer and / or a dielectric layer.

[0150] Aspect: 8: A device as described in aspects 1 to 7, wherein the at least one magnetic layer comprises a non-conductive material.

[0151] Aspect: 9: A device as described in aspects 1 to 8, wherein at least one magnetic layer has a relative magnetic permeability value greater than 1.

[0152] Aspect: 10: A device as described in aspects 1 to 9, wherein the at least one magnetic layer has a magnetic loss tangent value in the range of 0.01-0.04 for frequencies up to 100 MHz.

[0153] Aspect: 11: A device comprises: a die substrate; a plurality of interconnects located above the die substrate, wherein the plurality of interconnects are configured to operate as inductors; at least one dielectric layer surrounding at least a portion of the plurality of interconnects; and at least one magnetic layer surrounding the at least one dielectric layer.

[0154] Aspect: 12: A device as described in Aspect 11, wherein the multiple interconnects include a first through-hole interconnect and a second through-hole interconnect, and wherein the at least one dielectric layer includes a first dielectric layer that laterally surrounds and contacts the first through-hole interconnect, and a second dielectric layer that laterally surrounds and contacts the second through-hole interconnect.

[0155] Aspect: 13: A device as described in Aspect 12, wherein the at least one magnetic layer laterally surrounds and contacts the first dielectric layer and the second dielectric layer.

[0156] Aspect: 14: A device as described in aspects 12 to 13, wherein the first through-hole interconnection and the second through-hole interconnection are in a plane.

[0157] Aspect: 15: A device as described in aspects 11 to 14, wherein the at least one dielectric layer contacts at least a portion of the plurality of interconnects.

[0158] Aspect: 16: The device as described in aspects 11 to 15 further includes a plurality of transistors located in the tube core substrate.

[0159] Aspect: 17: A device as described in aspects 11 to 16, wherein the at least one magnetic layer includes an insulating layer and / or a dielectric layer.

[0160] Aspect: 18: A device as described in aspects 11 to 17, wherein the at least one magnetic layer comprises a non-conductive material.

[0161] Aspect: 19: A device as described in aspects 11 to 18, wherein at least one magnetic layer has a relative magnetic permeability value greater than 1.

[0162] Aspect: 20: A device as described in Aspects 11 to 19, wherein the device is selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0163] Aspect: 21: A method includes providing a die substrate. The method forms a plurality of interconnects located above the die substrate, wherein the plurality of interconnects are configured to operate as inductors. The method forms at least one magnetic layer surrounding at least a portion of the plurality of interconnects. The method forms at least one dielectric layer surrounding the at least one magnetic layer.

[0164] Aspect: 22: A method as described in Aspect 21, wherein the multiple interconnects include a first through-hole interconnect and a second through-hole interconnect, and wherein the at least one magnetic layer includes a first magnetic layer that laterally surrounds and contacts the first through-hole interconnect, and a second magnetic layer that laterally surrounds and contacts the second through-hole interconnect.

[0165] Aspect: 23: A method as described in Aspect 22, wherein the at least one dielectric layer laterally surrounds the first magnetic layer and the second magnetic layer.

[0166] Aspect: 24: A method as described in aspects 21 to 23, wherein the tube core substrate includes a plurality of transistors.

[0167] Aspect: 25: A method as described in Aspects 21 to 24, wherein the at least one magnetic layer includes an insulating layer, a dielectric layer and / or a non-conductive material, and wherein the at least one magnetic layer has a relative magnetic permeability value greater than 1.

[0168] Aspect: 26: A method includes providing a die substrate. The method forms a plurality of interconnects located above the die substrate, wherein the plurality of interconnects are configured to operate as inductors. The method forms at least one dielectric layer surrounding and contacting at least a portion of the plurality of interconnects. The method forms at least one magnetic layer surrounding and contacting the at least one dielectric layer.

[0169] Aspect: 27: A method as described in Aspect 26, wherein the multiple interconnects include a first through-hole interconnect and a second through-hole interconnect, and wherein the at least one dielectric layer includes a first dielectric layer that laterally surrounds and contacts the first through-hole interconnect, and a second dielectric layer that laterally surrounds and contacts the second through-hole interconnect.

[0170] Aspect: 28: A method as described in Aspect 27, wherein the at least one magnetic layer laterally surrounds and contacts the first dielectric layer and the second dielectric layer.

[0171] Aspect: 29: A method as described in aspects 26 to 28, wherein the tube core substrate includes a plurality of transistors.

[0172] Aspect: 30: A method as described in Aspects 26 to 29, wherein the at least one magnetic layer includes an insulating layer, a dielectric layer and / or a non-conductive material, and wherein the at least one magnetic layer has a relative magnetic permeability value greater than 1.

[0173] The various features of the present disclosure described herein may be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative rather than limiting the scope of the appended claims. Thus, the teachings of the present disclosure may be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A device comprising: die substrate; a plurality of interconnects over the die substrate, wherein the plurality of interconnects are configured to operate as inductors; at least one magnetic layer surrounding at least a portion of the plurality of interconnects; as well as At least one dielectric layer surrounds the at least one magnetic layer.

2. The device according to claim 1, wherein the plurality of interconnects comprises a first through-hole interconnect and a second through-hole interconnect, and The at least one magnetic layer includes a first magnetic layer laterally surrounding and contacting the first through-via interconnection, and a second magnetic layer laterally surrounding and contacting the second through-via interconnection. 3 . The device of claim 2 , wherein the at least one dielectric layer laterally surrounds the first magnetic layer and the second magnetic layer.

4. The device of claim 2, wherein the first through-via interconnect and the second through-via interconnect are in a planar configuration.

5. The device of claim 1, wherein the at least one dielectric layer surrounds and contacts at least a portion of the plurality of interconnects.

6. The device of claim 1, further comprising a plurality of transistors located in the die substrate.

7. The device of claim 1, wherein the at least one magnetic layer comprises an insulating layer and / or a dielectric layer.

8. The device of claim 1, wherein the at least one magnetic layer comprises a non-conductive material.

9. The device of claim 1, wherein the at least one magnetic layer has a relative permeability value greater than 1.

10. The device of claim 1, wherein the at least one magnetic layer has a magnetic loss tangent value in the range of 0.01-0.04 for frequencies up to 100 MHz.

11. A device comprising: die substrate; a plurality of interconnects over the die substrate, wherein the plurality of interconnects are configured to operate as inductors; at least one dielectric layer surrounding at least a portion of the plurality of interconnects; as well as At least one magnetic layer surrounds the at least one dielectric layer.

12. The device according to claim 11, wherein the plurality of interconnects comprises a first through-hole interconnect and a second through-hole interconnect, and The at least one dielectric layer includes a first dielectric layer laterally surrounding and contacting the first through-via interconnect, and a second dielectric layer laterally surrounding and contacting the second through-via interconnect.

13. The device of claim 12, wherein the at least one magnetic layer laterally surrounds and contacts the first dielectric layer and the second dielectric layer.

14. The device of claim 12, wherein the first through-via interconnect is planar with the second through-via interconnect.

15. The device of claim 11, wherein the at least one dielectric layer contacts at least a portion of the plurality of interconnects.

16. The device of claim 11, further comprising a plurality of transistors located in the die substrate.

17. The device of claim 11, wherein the at least one magnetic layer comprises an insulating layer and / or a dielectric layer.

18. The device of claim 11, wherein the at least one magnetic layer comprises a non-conductive material.

19. The device of claim 11, wherein the at least one magnetic layer has a relative permeability value greater than 1.

20. The device of claim 11, wherein the device is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

21. A method comprising: providing a die substrate; forming a plurality of interconnects over the die substrate, wherein the plurality of interconnects are configured to operate as inductors; forming at least one magnetic layer surrounding at least a portion of the plurality of interconnects; as well as At least one dielectric layer is formed surrounding the at least one magnetic layer.

22. The method of claim 21, wherein the plurality of interconnects comprises a first through-hole interconnect and a second through-hole interconnect, and The at least one magnetic layer includes a first magnetic layer laterally surrounding and contacting the first through-via interconnection, and a second magnetic layer laterally surrounding and contacting the second through-via interconnection.

23. The method of claim 22, wherein the at least one dielectric layer laterally surrounds the first magnetic layer and the second magnetic layer.

24. The method of claim 21, wherein the die substrate comprises a plurality of transistors.

25. The method of claim 21, wherein the at least one magnetic layer comprises an insulating layer, a dielectric layer and / or a non-conductive material, and Wherein the at least one magnetic layer has a relative magnetic permeability value greater than 1.

26. A method comprising: providing a die substrate; forming a plurality of interconnects over the die substrate, wherein the plurality of interconnects are configured to operate as inductors; forming at least one dielectric layer surrounding and contacting at least a portion of the plurality of interconnects; as well as At least one magnetic layer is formed surrounding and contacting the at least one dielectric layer.

27. The method of claim 26, wherein the plurality of interconnects comprises a first through-hole interconnect and a second through-hole interconnect, and The at least one dielectric layer includes a first dielectric layer laterally surrounding and contacting the first through-via interconnect, and a second dielectric layer laterally surrounding and contacting the second through-via interconnect.

28. The method of claim 27, wherein the at least one magnetic layer laterally surrounds and contacts the first dielectric layer and the second dielectric layer.

29. The method of claim 26, wherein the die substrate comprises a plurality of transistors.

30. The method of claim 26, wherein the at least one magnetic layer comprises an insulating layer, a dielectric layer and / or a non-conductive material, and Wherein the at least one magnetic layer has a relative magnetic permeability value greater than 1.

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