Wafer-level lithium niobate heterogeneous bonding method

Abstract

The embodiment of the invention provides a wafer-level lithium niobate heterogeneous bonding method, which relates to the technical field of silicon optical heterogeneous integration, and comprises the following steps: respectively preparing a silicon optical wafer, a circuit wafer and a lithium niobate wafer; bonding the first SiO2 cladding of the silicon optical wafer with the first side of the lithium niobate film of the lithium niobate wafer; and bonding the second SiO2 cladding of the circuit wafer with the second side of the lithium niobate film of the lithium niobate wafer. According to the scheme, the problems that the wafer is difficult to process and the bonding difficulty is increased due to the fact that an optical / electric functional structure intersects in the wafer manufacturing process are solved, photoelectric separation in the silicon optical-lithium niobate heterogeneous integrated wafer manufacturing process is achieved, and efficient bonding is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon-optical heterogeneous integration, and in particular to a wafer-level lithium niobate heterogeneous bonding method. Background Art

[0002] Lithium niobate thin film materials have extremely low light absorption loss and good linear electro-optical effect, and have good application prospects in the field of integrated optoelectronics; the silicon photonics technology platform based on CMOS technology and low-loss silicon nitride can manufacture high-precision, low-loss silicon photonics devices and realize the integration of various passive devices. Therefore, combining lithium niobate thin films with excellent optoelectronic properties with silicon photonics technology with mature process technology to realize silicon photonics-lithium niobate modulation devices with good optoelectronic properties, and then realizing silicon photonics heterogeneous integration, is of great significance to the development and application of silicon-based optoelectronics technology.

[0003] Among the existing technical solutions, Solution 1: Lithium niobate waveguides are etched after bonding lithium niobate wafers with silicon photonic wafers, but there is a problem of difficulty in etching lithium niobate waveguides, mainly because the waveguide line width is difficult to meet the requirements; Solution 2: Metal graphic processing is performed on lithium niobate wafers, but there is a problem of difficulty in post-process metal processing; Solution 3: The method of bonding lithium niobate chips with silicon photonic wafers is used to set circuits on the periphery of the lithium niobate chips, but there are problems of low bonding efficiency and uneven bonding interface. Therefore, the existing technical solutions have the problems of difficulty in bonding lithium niobate etching, difficulty in metal processing, and low bonding efficiency. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a wafer-level lithium niobate heterogeneous bonding method to solve the technical problems of difficult etching of bonded lithium niobate, difficult metal processing and low bonding efficiency in the prior art. The method includes:

[0005] Prepare silicon photonic wafers, circuit wafers and lithium niobate wafers respectively;

[0006] Bonding the first SiO2 cladding layer 11 of the silicon photonic wafer to the first side of the lithium niobate film 31 of the lithium niobate wafer;

[0007] The second SiO2 cladding layer 21 of the circuit wafer is bonded to the second side of the lithium niobate film 31 of the lithium niobate wafer.

[0008] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above-mentioned technical solutions adopted in the embodiments of this specification include at least: proposing to prepare silicon photonic wafers, circuit wafers and lithium niobate wafers separately, avoiding the intersection of optical / electrical functional structures in wafer manufacturing, which leads to difficulties in wafer processing and increased bonding difficulty, and realizing the photoelectric separation in silicon photonic-lithium niobate heterogeneous integrated wafer manufacturing; in addition, the wafer-level bonding technology is adopted to ensure that the bonding interface has a high flatness, thereby realizing efficient bonding of silicon photonic wafers, lithium niobate wafers and circuit wafers. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0010] Figure 1 It is a flow chart of a wafer-level lithium niobate heterogeneous bonding method provided by an embodiment of the present invention;

[0011] Figure 2 Schematic diagram of the cross-sectional structure of a silicon photonic wafer A provided in an embodiment of the present invention;

[0012] Figure 3 is a schematic diagram of a cross-sectional structure of a circuit wafer B provided by an embodiment of the present invention;

[0013] Figure 4 Schematic diagram of the cross-sectional structure of a lithium niobate wafer C provided in an embodiment of the present invention;

[0014] Figure 5 It is a schematic diagram of a cross-sectional structure of a lithium niobate wafer C bonded to a silicon photonic wafer A provided by an embodiment of the present invention;

[0015] Figure 6 It is a schematic diagram of a cross-sectional structure of removing a third substrate 33 and a third thermal oxide layer 32 of a lithium niobate wafer C provided by an embodiment of the present invention;

[0016] Figure 7 It is a schematic diagram of the cross-sectional structure of a circuit wafer B bonded to a silicon photo-lithium niobate thin film heterogeneous integrated wafer A+C provided by an embodiment of the present invention;

[0017] Figure 8 It is a schematic diagram of a cross-sectional structure of removing the second silicon substrate 23 of the circuit wafer B and thinning the second SiO2 thermal oxide layer 22 provided by an embodiment of the present invention;

[0018] Fig. 9It is a schematic cross-sectional structure diagram of performing PAD windowing on a metal electrode 20 of a circuit wafer B provided by an embodiment of the present invention;

[0019] Fig.10 It is a schematic structural diagram of obtaining an LN film by removing the third substrate 33 and the third thermal oxide layer 32 of a lithium niobate wafer C provided by an embodiment of the present invention;

[0020] Fig.11 It is a structural schematic diagram of a circuit thin film obtained by removing the second silicon substrate 23 of the circuit wafer B provided by an embodiment of the present invention;

[0021] Fig.12 It is a schematic diagram of a structure in which a silicon photonic wafer A and a circuit film are bonded to both sides of an LN film at one time, provided by an embodiment of the present invention;

[0022] Fig.13 It is a schematic diagram of adding alignment marks on the front and back sides of a lithium niobate wafer C provided by an embodiment of the present invention;

[0023] Fig.14 It is a schematic cross-sectional structure diagram of adding a first filling structure 101 on a silicon photonic wafer A provided by an embodiment of the present invention;

[0024] Fig.15 It is a schematic cross-sectional structure diagram of adding a second filling structure 201 on a circuit wafer B provided by an embodiment of the present invention;

[0025] Fig.16 It is a top view of a structure in which a first etching groove 111 is provided on a silicon photonic wafer A according to an embodiment of the present invention;

[0026] Fig.17 It is a top view of a structure in which a second etching groove 211 is provided on a circuit wafer B according to an embodiment of the present invention;

[0027] Fig.18 It is a schematic diagram of a network structure formed by etching grooves provided in an embodiment of the present invention.

[0028] Reference numerals in the figures:

[0029] 10. Silicon nitride waveguide; 11. First SiO2 cladding; 12. First SiO2 thermal oxide layer; 13. First silicon substrate; 20. Metal electrode; 21. Second SiO2 cladding; 22. Second SiO2 thermal oxide layer; 23. Second silicon substrate; 31. Lithium niobate film; 32. Third SiO2 thermal oxide layer; 33. Third substrate; 40. First bonding interface; 60. Second bonding interface; 80. PAD window; 101. First filling structure; 201. Second filling structure; 111. First etching groove; 211. Second etching groove. DETAILED DESCRIPTION

[0030] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0031] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0032] In an embodiment of the present invention, a wafer-level lithium niobate heterogeneous bonding method is provided, such as Figure 1 As shown, the method includes:

[0033] Step S101: preparing a silicon photonic wafer, a circuit wafer and a lithium niobate wafer respectively;

[0034] Step S102: bonding the first SiO2 cladding layer 11 of the silicon photonic wafer to the first side of the lithium niobate film 31 of the lithium niobate wafer;

[0035] Step S103: bonding the second SiO2 cladding layer 21 of the circuit wafer to the second side of the lithium niobate film 31 of the lithium niobate wafer.

[0036] Depend on Figure 1 As can be seen from the process shown, in an embodiment of the present invention, it is proposed to prepare silicon photonic wafers, circuit wafers and lithium niobate wafers separately, so as to avoid the intersection of optical / electrical functional structures in wafer manufacturing, which may lead to difficulties in wafer processing and increased bonding difficulty, thereby realizing the photoelectric separation in silicon photonic-lithium niobate heterogeneous integrated wafer manufacturing; in addition, wafer-level bonding technology is used to ensure that the bonding interface has a high flatness, thereby realizing efficient bonding of silicon photonic wafers, lithium niobate wafers and circuit wafers.

[0037] In a specific implementation, a CMOS platform can be used to process and prepare a silicon photonic wafer A. For example, a first SiO2 thermal oxide layer 12 is deposited on a first silicon substrate 13, and then a silicon nitride waveguide 10 is prepared on the top surface of the first SiO2 thermal oxide layer 12 (for example, a silicon nitride layer is first deposited, and then the silicon nitride layer is patterned to obtain the silicon nitride waveguide 10). Finally, a first SiO2 cladding layer 11 is deposited to cover the silicon nitride waveguide 10 and the first SiO2 thermal oxide layer 12, so as to obtain a silicon photonic wafer A. Figure 2 shown.

[0038] Specifically, the silicon nitride waveguide 10 is a single-layer SiN waveguide, and the thickness of the silicon nitride waveguide 10 is 200-450nm; the thickness of the first SiO2 cladding layer 11 is 300-550nm; the thickness of the first SiO2 thermal oxide layer 12 is 2-8μm; the thickness of the first silicon substrate 13 is 500-800μm.

[0039] In a specific implementation, a CMOS platform can be used to process and prepare a circuit wafer B. For example, a second SiO2 thermal oxide layer 22 is deposited on a second silicon substrate 23, and then a metal electrode 20 is prepared on the top surface of the second SiO2 thermal oxide layer 22 (for example, a metal layer is first deposited, and then the metal layer is patterned to obtain the metal electrode 20). Finally, a second SiO2 cladding layer 21 is deposited to cover the metal electrode 20 and the second SiO2 thermal oxide layer 22, so as to obtain a circuit wafer B such as Figure 3 shown.

[0040] Specifically, the material of the metal electrode 20 is one of Al, Cu or AlCu; the thickness of the metal electrode 20 is 0.5-1.5 μm; the thickness of the second SiO2 cladding layer 21 is 0.6-1.6 μm; the thickness of the second SiO2 thermal oxide layer 22 is 2-8 μm; the thickness of the second silicon substrate 13 is 500-800 μm.

[0041] In a specific implementation, a conventional method for preparing a lithium niobate wafer can be used to prepare a lithium niobate wafer C. For example, a third SiO2 thermal oxide layer 32 is deposited on a third substrate 33, and a lithium niobate film 31 is then prepared on the top surface of the third SiO2 thermal oxide layer 32 to obtain a lithium niobate wafer C. Figure 4 shown.

[0042] Specifically, the thickness of the lithium niobate film 31 is 200-500 nm; the thickness of the third SiO2 thermal oxide layer 32 is 0.2-5 μm; the third substrate 33 is a silicon substrate or a quartz substrate, and the thickness of the third substrate 33 is 500-800 μm.

[0043] In a specific implementation, after preparing the silicon photonic wafer A, the circuit wafer B and the lithium niobate wafer C respectively, bonding can be performed twice, and the first SiO2 cladding layer 11 of the silicon photonic wafer is bonded to the first side of the lithium niobate film 31 of the lithium niobate wafer, and the second SiO2 cladding layer 21 of the circuit wafer is bonded to the second side of the lithium niobate film 31 of the lithium niobate wafer. For example, the two bonding processes are as follows:

[0044] First, the lithium niobate wafer C is bonded to the silicon photonic wafer A. For example, the bonding surfaces of the lithium niobate wafer C and the silicon photonic wafer A, namely, the lithium niobate film 31 and the surface of the first SiO2 cladding layer 11, are activated by plasma, respectively, and a wafer to wafer bonding method is adopted, at 100 to 300° C., for a bonding time of 1 hour to 12 hours, to bond one side of the lithium niobate film 31 of the lithium niobate wafer C to the surface of the first SiO2 cladding layer 11 of the silicon photonic wafer A to form a first bonding interface 40, as shown in FIG. Figure 5 Then, the third substrate 33 and the third SiO2 thermal oxide layer 32 of the lithium niobate wafer C are removed to obtain a silicon photo-lithium niobate thin film heterogeneous integrated wafer (ie, wafer A+C), as shown. Figure 6 shown.

[0045] Next, the circuit wafer B is bonded to the silicon photo-lithium niobate thin film heterogeneous integrated wafer A+C. For example, the bonding surfaces of the silicon photo-lithium niobate thin film heterogeneous integrated wafer A+C and the circuit wafer B, i.e., the lithium niobate thin film 31 and the surface of the second SiO2 cladding layer 21, are activated by plasma, respectively, and a wafer to wafer bonding method is adopted, at 100 to 300° C., for a bonding time of 1 h to 12 h, and the surface of the second SiO2 cladding layer 21 of the circuit wafer B is bonded to the other side of the lithium niobate thin film 31 of the silicon photo-lithium niobate thin film heterogeneous integrated wafer to form a second bonding interface 60, as shown in FIG. Figure 7 Then, the second silicon substrate 23 of the circuit wafer B is removed, and the second SiO2 thermal oxide layer 22 is thinned to obtain a silicon photo-lithium niobate film-circuit heterogeneous integrated wafer A+C+B, as shown in FIG. Figure 8 shown.

[0046] Finally, the second SiO2 thermal oxide layer 22 after thinning of the silicon photonic-lithium niobate film-circuit heterogeneous integrated wafer A+C+B is etched to form a PAD window 80 of the metal electrode 20, and the following can be obtained: Fig. 9 The target wafer structure shown is a silicon photonics-lithium niobate thin film-circuit heterogeneous integrated wafer with separated optoelectronics.

[0047] In specific implementation, after preparing silicon photonic wafer A, circuit wafer B and lithium niobate wafer C respectively, in order to further improve bonding efficiency and shorten bonding time, it is proposed that in one bonding operation, the first SiO2 cladding 11 of the silicon photonic wafer is bonded to the first side of the lithium niobate film 31 of the lithium niobate wafer, and the second SiO2 cladding 21 of the circuit wafer is bonded to the second side of the lithium niobate film 31 of the lithium niobate wafer. For example, the third SiO2 thermal oxide layer 32 and the third substrate 33 of the lithium niobate wafer C are removed to obtain the lithium niobate film 31; in one bonding operation, the first SiO2 cladding 11 of the silicon photonic wafer A is bonded to the first side of the lithium niobate film 31, and the second SiO2 cladding 21 of the circuit wafer B is bonded to the second side of the lithium niobate film 31.

[0048] In a specific implementation, the third SiO2 thermal oxide layer 32 and the third substrate 33 of the lithium niobate wafer C are removed to obtain the lithium niobate film 31, such as Fig.10 As shown, the thickness of the LN film (ie, lithium niobate film 31) is 200-500 nm.

[0049] In a specific implementation, before bonding the second SiO2 cladding layer 21 of the circuit wafer B to the second side of the lithium niobate film 31, the second silicon substrate 23 of the circuit wafer B may be removed to obtain the circuit film. Fig.11 As shown, the circuit film includes a metal electrode 20, a second SiO2 cladding layer 21 and a second SiO2 thermal oxide layer 22, and the thickness of the circuit film is 2.6-9.6 μm.

[0050] In a specific implementation, the bonding surfaces of the silicon photonic wafer A and the circuit wafer B are activated by plasma, and both the front and back surfaces of the lithium niobate wafer C are activated by plasma. The first SiO2 cladding 11 of the silicon photonic wafer A, the lithium niobate film 31 of the lithium niobate wafer C, and the second SiO2 cladding 21 of the circuit wafer B (i.e., the second SiO2 cladding 21 of the circuit film) are sequentially bonded. Fig.12 As shown, annealing and bonding at 100-300℃, bonding time 1h-12h, the effect after bonding and Figure 8 The method is consistent, and two bonding steps are simplified into one bonding step, which can improve the bonding efficiency and shorten the bonding time.

[0051] In specific implementation, in order to achieve accurate one-time bonding of the three wafers, the optical path pattern on the silicon photonic wafer A and the circuit pattern on the circuit wafer B need to be accurately aligned. Since the lithium niobate wafer C has a certain thickness, if the mark on the circuit wafer B is directly aligned with the mark on the silicon photonic wafer A, there will be an alignment deviation problem. Therefore, the present application proposes that marks can be added on both sides of wafer C to achieve alignment of the silicon photonic wafer A and the circuit wafer B and achieve bonding in one go. For example, in a one-time bonding operation, the first SiO2 cladding 11 of the silicon photonic wafer is bonded to the first side of the lithium niobate film 31, and the second SiO2 cladding 21 of the circuit wafer is bonded to the second side of the lithium niobate film 31, including:

[0052] A first mark MA is set on the first side of the lithium niobate film 31, and a second mark MB is set on the second side of the lithium niobate film 31, the first mark MA corresponds to the alignment mark on the silicon photonic wafer, and the second mark MB corresponds to the alignment mark on the circuit wafer, and the first mark MA and the second mark MB are used to align the optical path pattern on the silicon photonic wafer with the circuit pattern on the circuit wafer; after aligning the first mark MA with the alignment mark on the silicon photonic wafer, and aligning the second mark MB with the alignment mark on the circuit wafer, in one bonding operation, the first SiO2 cladding 11 of the silicon photonic wafer is bonded to the first side of the lithium niobate film 31, and the second SiO2 cladding 21 of the circuit wafer is bonded to the second side of the lithium niobate film 31.

[0053] In specific implementation, alignment marks are added on both sides of the wafer C such as Fig.13 As shown, the first mark MA is the front alignment mark of the lithium niobate wafer C, corresponding to the corresponding alignment mark on the silicon photonic wafer A; the second mark MB is the back alignment mark of the lithium niobate wafer C, corresponding to the corresponding alignment mark on the circuit wafer B. By adding alignment marks on the lithium niobate wafer C, the alignment accuracy of the silicon photonic wafer A and the circuit wafer B can be improved when they are separated by the lithium niobate wafer C, which is beneficial to improving the stability of the bonding process.

[0054] In specific implementation, during the one-time bonding process of the above three wafers, silicon photonic wafer A and circuit wafer B may have stress concentration problems caused by the superposition of thin film layers, which will manifest as wafer micro-warping problems on the entire wafer. If silicon photonic wafer A and circuit wafer B are bonded in two steps, stress can be released by annealing after each bonding step; but when silicon photonic wafer A and circuit wafer B are bonded simultaneously in one step, silicon photonic wafer A, circuit wafer B and lithium niobate wafer C will have stress mismatch problems, especially stress mismatch between silicon photonic wafer A and circuit wafer B. In order to avoid stress mismatch between silicon photonic wafer A and circuit wafer B, it is proposed that before bonding the first SiO2 cladding 11 of the silicon photonic wafer A to the first side of the lithium niobate film 31 and bonding the second SiO2 cladding 21 of the circuit wafer B to the second side of the lithium niobate film 31, stress release structures are respectively arranged in the silicon photonic wafer A and the circuit wafer B, so that the stress between the silicon photonic wafer A and the circuit wafer B is balanced.

[0055] In a specific implementation, the stress release structure may include a filling structure or an etched groove.

[0056] In a specific implementation, a stress release structure is provided in the silicon photonic wafer and the circuit wafer respectively by releasing stress through a filling structure, including: if the stress release structure is a filling structure, a plurality of first filling structures 101 are evenly distributed in the first SiO2 cladding layer 11 of the silicon photonic wafer A, such as Fig.14 As shown; a plurality of second filling structures 201 are evenly distributed in the second SiO2 cladding layer 21 of the circuit wafer, such as Fig.15 As shown. By adding a first filling structure 101 and a second filling structure 201 to the silicon photonic wafer A and the circuit wafer B respectively, the stress and warpage of the wafer can be controlled by adding the filling structure, so that the warpage BOW_A of the silicon photonic wafer A and the warpage BOW_B of the circuit wafer B are similar, that is, BOW_A≈BOW_B. Based on this method, stress matching between the silicon photonic wafer A, the circuit wafer B and the lithium niobate wafer C can be achieved, and the bonding robustness can be improved.

[0057] In a specific implementation, the material of the first filling structure 101 is silicon nitride, and the material of the second filling structure 201 is the same as the material of the metal electrode 20 in the circuit wafer.

[0058] In specific implementation, in order to further improve the robustness of the one-time bonding process of the above three wafers, the stress imbalance state between silicon photonics wafer A and circuit wafer B can also be balanced by adjusting the graphic density of silicon photonics wafer A and circuit wafer B. For example, the first graphic density on the silicon photonics wafer A and the second graphic density on the circuit wafer B are adjusted to reach preset densities respectively, so that the stress between the silicon photonics wafer A and the circuit wafer B is balanced, wherein the first graphic density is the ratio of the total area of ​​the optical path pattern of the silicon photonics wafer A and the first filling structure 101 to the area of ​​the silicon photonics wafer A, and the second graphic density is the ratio of the total area of ​​the circuit pattern of the circuit wafer B and the second filling structure 201 to the area of ​​the circuit wafer B.

[0059] In a specific implementation, the preset density may be 40%-60%.

[0060] In a specific implementation, stress is released by etching grooves, and stress release structures are respectively set in the silicon photonic wafer and the circuit wafer, including: if the stress release structure is an etching groove, first etching grooves 111 are evenly distributed in the first SiO2 cladding 11 and the first SiO2 thermal oxide layer 12 of the silicon photonic wafer A, and second etching grooves 211 are evenly distributed in the second SiO2 cladding 21 and the second SiO2 thermal oxide layer 22 of the circuit wafer B, and the first etching grooves 111 penetrate the first SiO2 cladding 11 and the first SiO2 thermal oxide layer 12, as shown in FIG. Fig.16 As shown; the second etching groove 211 penetrates the second SiO2 cladding layer 21 and the second SiO2 thermal oxide layer 22, as shown Fig.17 shown.

[0061] Specifically, Fig.16 , Fig.17 As shown, groove etching is performed on silicon photonic wafer A and circuit wafer B respectively. Taking silicon photonic wafer A as an example, the etching needs to penetrate the first SiO2 cladding layer 11 and the first SiO2 thermal oxide layer 12 and stop on the first silicon substrate 13 to form a first etched groove 111. The first etched groove 111 can release the stress at the edge of the etched groove, so that certain stress damage is generated in the groove and at the edge of the groove, but the stress of the entire wafer will be reduced, so that the bonding failure problem caused by stress concentration during wafer bonding can be avoided.

[0062] In a specific implementation, the widths of the first etching groove 111 and the second etching groove 211 may be 10-100 micrometers respectively.

[0063] In a specific implementation, all the first etching grooves intersect to form a network structure, and all the second etching grooves intersect to form a network structure, such as Fig.18As shown, on the silicon photonic wafer A or the circuit wafer B, all the etching grooves are crisscrossed to form a mesh structure.

[0064] The embodiments of the present invention achieve the following technical effects: it proposes to prepare silicon photonic wafers, circuit wafers and lithium niobate wafers separately, thereby avoiding the problem of difficulty in wafer processing and increased bonding difficulty caused by the intersection of optical / electrical functional structures in wafer manufacturing, and realizing the photoelectric separation in silicon photonic-lithium niobate heterogeneous integrated wafer manufacturing; in addition, the wafer-level bonding technology is used to ensure that the bonding interface has a high flatness, thereby realizing efficient bonding of silicon photonic wafers, lithium niobate wafers and circuit wafers.

[0065] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A wafer-level lithium niobate heterogeneous bonding method, characterized in that: include: Prepare silicon photonic wafers, circuit wafers and lithium niobate wafers respectively; Bonding the first SiO2 cladding layer (11) of the silicon photonic wafer to the first side of the lithium niobate film (31) of the lithium niobate wafer; The second SiO2 cladding layer (21) of the circuit wafer is bonded to the second side of the lithium niobate film (31) of the lithium niobate wafer.

2. The wafer-level lithium niobate heterogeneous bonding method according to claim 1, characterized in that: Bonding the first SiO2 cladding (11) of the silicon photonic wafer to the first side of the lithium niobate film (31) of the lithium niobate wafer; bonding the second SiO2 cladding (21) of the circuit wafer to the second side of the lithium niobate film (31) of the lithium niobate wafer, comprising: Removing the third SiO2 thermal oxide layer (32) and the third substrate (33) of the lithium niobate wafer to obtain the lithium niobate film (31); In one bonding operation, the first SiO2 cladding (11) of the silicon photonic wafer is bonded to the first side of the lithium niobate film (31), and the second SiO2 cladding (21) of the circuit wafer is bonded to the second side of the lithium niobate film (31).

3. The wafer-level lithium niobate heterogeneous bonding method according to claim 2, characterized in that: In one bonding operation, the first SiO2 cladding layer (11) of the silicon photonic wafer is bonded to the first side of the lithium niobate film (31), and the second SiO2 cladding layer (21) of the circuit wafer is bonded to the second side of the lithium niobate film (31), comprising: A first mark is provided on a first side of the lithium niobate film (31), and a second mark is provided on a second side of the lithium niobate film (31), the first mark corresponds to an alignment mark on the silicon photonic wafer, the second mark corresponds to an alignment mark on the circuit wafer, and the first mark and the second mark are used to align an optical path pattern on the silicon photonic wafer with a circuit pattern on the circuit wafer; After aligning the first mark with the alignment mark on the silicon photonic wafer and aligning the second mark with the alignment mark on the circuit wafer, in one bonding operation, the first SiO2 cladding (11) of the silicon photonic wafer is bonded to the first side of the lithium niobate film (31), and the second SiO2 cladding (21) of the circuit wafer is bonded to the second side of the lithium niobate film (31).

4. The wafer-level lithium niobate heterogeneous bonding method according to claim 2, characterized in that: Also includes: Before bonding the first SiO2 cladding (11) of the silicon photonic wafer to the first side of the lithium niobate film (31), and bonding the second SiO2 cladding (21) of the circuit wafer to the second side of the lithium niobate film (31), stress release structures are respectively provided in the silicon photonic wafer and the circuit wafer, so that stress between the silicon photonic wafer and the circuit wafer is balanced.

5. The wafer-level lithium niobate heterogeneous bonding method according to claim 4, characterized in that: The stress release structure includes a filling structure or an etched groove.

6. The wafer-level lithium niobate heterogeneous bonding method according to claim 4, characterized in that: Stress release structures are respectively arranged in the silicon photonic wafer and the circuit wafer, including: If the stress release structure is a filling structure, a plurality of first filling structures (101) are evenly distributed in the first SiO2 cladding (11) of the silicon photonic wafer, and a plurality of second filling structures (201) are evenly distributed in the second SiO2 cladding (21) of the circuit wafer.

7. The wafer-level lithium niobate heterogeneous bonding method according to claim 6, characterized in that: The material of the first filling structure (101) is silicon nitride, and the material of the second filling structure (201) is the same as the material of the metal electrode (20) in the circuit wafer.

8. The wafer-level lithium niobate heterogeneous bonding method according to claim 6, characterized in that: Also includes: The first graphic density on the silicon photonics wafer and the second graphic density on the circuit wafer are adjusted to reach preset densities respectively, so that the stress between the silicon photonics wafer and the circuit wafer is balanced, wherein the first graphic density is the ratio of the total area of ​​the optical path pattern of the silicon photonics wafer and the first filling structure (101) to the area of ​​the silicon photonics wafer, and the second graphic density is the ratio of the total area of ​​the circuit pattern of the circuit wafer and the second filling structure (201) to the area of ​​the circuit wafer.

9. The wafer-level lithium niobate heterogeneous bonding method according to claim 4, characterized in that: Stress release structures are respectively arranged in the silicon photonic wafer and the circuit wafer, including: If the stress release structure is an etching groove, first etching grooves are evenly distributed in the first SiO2 cladding (11) and the first SiO2 thermal oxide layer (12) of the silicon photonic wafer, and second etching grooves are evenly distributed in the second SiO2 cladding (21) and the second SiO2 thermal oxide layer (22) of the circuit wafer, the first etching grooves penetrate the first SiO2 cladding (11) and the first SiO2 thermal oxide layer (12), and the second etching grooves penetrate the second SiO2 cladding (21) and the second SiO2 thermal oxide layer (22).

10. The wafer-level lithium niobate heterogeneous bonding method according to claim 9, characterized in that: All the first etching grooves (111) are crossed to form a network structure, and all the second etching grooves (211) are crossed to form a network structure.

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