Phase-locked loop
By designing a phase-locked loop including digital signal selector, CNC delay chain, frequency sampling module, frequency difference accumulation module and XOR gate, the problem of long response time of traditional phase-locked loop is solved, and fast start-up and response is achieved, with low power consumption and fast response.
Patent Information
- Application Number
- CN202510131699.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-06
- Publication Date
- 2025-05-16
AI Technical Summary
The traditional analog phase-locked loop has a long response time, cannot start quickly, and cannot respond quickly and adapt to rapidly changing frequency requirements.
A phase-locked loop including a digital signal selector, a CNC delay chain, a frequency sampling module, a frequency difference accumulation module and an exclusive-OR gate are designed. By receiving the start pulse signal, the digital signal selector triggers the CNC delay chain to generate the start clock. The frequency sampling module and the frequency difference accumulation module are used to correct the start clock. The XOR gate ensures continuous output of the signal.
It realizes fast start and response of the phase-locked loop, can quickly start under the trigger of the start pulse signal, and realizes continuous signal output and signal correction, with low power consumption and fast response.
Smart Images
Figure CN120017047A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of phase-locked loops, and in particular to a phase-locked loop. Background Art
[0002] A phase-locked loop is a negative feedback control system that uses the voltage generated by phase synchronization to tune a voltage-controlled oscillator to generate a target frequency. Most traditional phase-locked loops are analog phase-locked loops, which include a phase detector, a frequency divider, and a voltage-controlled oscillator. The phase detector requires the oscillator to be at a specific frequency to generate a stable oscillation signal, has a long response time, and cannot start quickly. Summary of the invention
[0003] Based on this, it is necessary to provide a phase-locked loop that can start quickly.
[0004] A phase-locked loop, comprising:
[0005] A digital signal selector, wherein the first input terminal of the digital signal selector is used to receive a start pulse signal;
[0006] A digitally controlled delay chain, wherein a first input terminal of the digitally controlled delay chain is connected to an output terminal of the digital signal selector;
[0007] A frequency sampling module, wherein a first input terminal of the frequency sampling module is connected to an output terminal of the digital control delay chain, and a second input terminal of the frequency sampling module is used to access a reference clock; the frequency sampling module is used to convert an output signal of the digital control delay chain into corresponding frequency data according to the reference clock;
[0008] A frequency difference accumulation module, wherein the first input end of the frequency difference accumulation module is connected to the output end of the frequency difference sampling module, the second input end of the frequency difference accumulation module is used to access the target frequency, and the output end of the frequency difference accumulation module is connected to the second input end of the numerical control delay chain; the frequency difference accumulation module is used to determine and output the frequency difference between the target frequency and the frequency data, so that the numerical control delay chain delays the output signal of the digital signal selector based on the frequency difference;
[0009] An XOR gate, wherein the first input end of the XOR gate is connected to the output end of the digital signal selector, the second input end of the XOR gate is connected to the output end of the digital control delay chain, and the output end of the XOR gate is connected to the second input end of the digital signal selector, so that the digital signal selector continuously outputs a signal after a single trigger of the start pulse signal.
[0010] In one embodiment, the digitally controlled delay chain comprises:
[0011] A plurality of delay chains connected in series; wherein the input end of the first delay chain is connected to the output end of the digital signal selector, and the output end of the last delay chain is connected to the first input end of the frequency sampling module;
[0012] A control logic circuit, wherein the input end of the control logic circuit is connected to the output end of the frequency difference accumulation module, and the multiple output ends of the control logic circuit are respectively connected to the controlled ends of each level of delay chain; the control logic circuit is used to determine the control signal according to the frequency difference, and the control signal is used to determine the delay time of each delay chain.
[0013] In one embodiment, each delay chain includes:
[0014] A plurality of delay modules connected in series; wherein the types of the delay modules are all the same;
[0015] A multiplexer, wherein the multiple input terminals of the multiplexer are respectively connected to the output terminals of the delay modules and the input terminals of the first delay module in a one-to-one correspondence, the output terminal of the multiplexer is connected to the input terminal of the first delay module in the next-level delay chain, and the controlled terminal of the multiplexer is connected to the output terminal of the control logic circuit to select and turn on one of the input terminals and the output terminal of the multiplexer under the drive of the control signal.
[0016] In one embodiment, each delay chain satisfies the following conditions:
[0017] N i ≥D i+1
[0018] Among them, N i is the number of delay modules in the i-th delay chain, D i+1 is a multiple of the delay time of the delay module in the (i+1)th delay chain and the delay time of the delay module in the i-th delay chain, where i is an integer greater than or equal to 1.
[0019] In one embodiment, the frequency sampling module includes:
[0020] A clock divider, wherein an input end of the clock divider is connected to an output end of the digitally controlled delay chain;
[0021] A reference clock counter, the reference clock counter is used to access the reference clock; the reference clock counter is used to determine the time length corresponding to the reference clock;
[0022] A start-up clock counter, wherein a first input terminal of the start-up clock counter is connected to an output terminal of the clock frequency divider, and a second input terminal of the start-up clock counter is connected to an output terminal of a reference clock counter; the start-up clock counter is used to determine an actual count value of an output signal of a numerical control delay chain within a time length;
[0023] A frequency calculation logic circuit, wherein the first input end of the frequency calculation logic circuit is connected to the output end of the oscillation start clock counter, the second input end of the frequency calculation logic circuit is connected to the output end of the reference clock counter, and the output end of the frequency calculation logic circuit is connected to the first input end of the frequency difference accumulation module; the frequency calculation logic circuit is used to output frequency data according to the actual count value and time length.
[0024] In one embodiment, the frequency difference accumulation module is a PID controller, and the PID controller is used to:
[0025] According to the frequency data and the target frequency, determine the corresponding frequency difference;
[0026] Perform PID adjustment on the frequency difference to obtain the PID adjustment result;
[0027] The PID adjustment result is delayed by a unit to determine the accumulated frequency difference.
[0028] In one embodiment, the phase-locked loop further comprises:
[0029] A noise shaping module, the input end of the noise shaping module is connected to the output end of the frequency difference accumulation module, and the output end of the noise shaping module is connected to the second input end of the numerical control delay chain; the noise shaping module is used to receive and perform noise shaping on the frequency difference.
[0030] In one embodiment, the noise shaping module includes:
[0031] A noise generation module, the noise generation module is used to generate white noise;
[0032] The adder has a first input end connected to the output end of the frequency difference accumulation module, a second input end connected to the output end of the noise generation module, and an output end of the adder connected to the second input end of the digital control delay chain.
[0033] In one embodiment, the phase-locked loop further comprises:
[0034] A digital low-pass filter, wherein the input end of the digital low-pass filter is connected to the output end of the noise shaping module, and the output end of the digital low-pass filter is connected to the second input end of the digital control delay chain.
[0035] In one embodiment, the output signal of the XOR gate is a square wave signal.
[0036] The above phase-locked loop includes a digital signal selector, a digital control delay chain, a frequency sampling module, a frequency difference accumulation module and an XOR gate, wherein the digital signal selector can trigger the digital control delay chain to generate a start-up clock based on the output signal of the digital selector by receiving a start pulse signal, the frequency sampling module can output corresponding frequency data according to the start-up clock and the input reference clock, and the frequency difference accumulation module can output the corresponding frequency difference to the digital control delay chain according to the frequency data and the input target frequency, so that the digital control delay chain corrects the output start-up clock based on the frequency difference under the triggering of the XOR gate output signal, thereby determining an accurate start-up clock. The phase-locked loop is a pure digital circuit. Compared with the traditional analog phase-locked loop, it saves the oscillator and analog phase detector therein, has low power consumption, fast response, and can achieve rapid start-up; and can quickly start under the triggering of the start pulse signal, and achieve continuous signal output and continuous signal correction. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0038] Figure 1 One of the structural block diagrams of a phase-locked loop according to an embodiment;
[0039] Figure 2 This is a second structural block diagram of a phase-locked loop according to an embodiment;
[0040] Figure 3 The third structural block diagram of a phase-locked loop of an embodiment;
[0041] Figure 4 The figure is an operational logic diagram of a PID controller according to an embodiment.
[0042] Figure 5 This is a fourth structural block diagram of a phase-locked loop according to an embodiment. DETAILED DESCRIPTION
[0043] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0045] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.
[0046] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.
[0047] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.
[0048] In one embodiment, Figure 1 As shown, a phase-locked loop 10 is provided, comprising: a digital signal selector 110 , a digitally controlled delay chain 120 , a frequency sampling module 130 , a frequency difference accumulation module 140 and an XOR gate 150 .
[0049] The first input terminal of the digital signal selector is used to connect the start pulse signal (see Figure 1 The digital signal selector may be a one-to-one selector.
[0050] The first input terminal of the digitally controlled delay chain is connected to the output terminal of the digital signal selector.
[0051] The first input terminal of the frequency sampling module is connected to the output terminal of the digital control delay chain, and the second input terminal of the frequency sampling module is used to access the reference clock (see Figure 1 Signal B shown); the frequency sampling module is used to convert the output signal of the digital control delay chain into corresponding frequency data according to the reference clock.
[0052] The first input end of the frequency difference accumulation module is connected to the output end of the frequency difference sampling module, and the second input end of the frequency difference accumulation module is used to access the target frequency (see Figure 1The output end of the frequency difference accumulation module is connected to the second input end of the digital control delay chain; the frequency difference accumulation module is used to determine and output the frequency difference between the target frequency and the frequency data, so that the digital control delay chain delays the output signal of the digital signal selector based on the frequency difference. The digital control delay chain delays the single-bit digital signal selected by the digital signal selector to output the start-up clock.
[0053] The first input of the XOR gate (see Figure 1 Port x in the figure is connected to the output of the digital signal selector and the second input of the XOR gate (see Figure 1 Port y in the digital control system is connected to the output end of the digital control delay chain, and the output end of the XOR gate is connected to the second input end of the digital signal selector, so that the digital signal selector continuously outputs the signal after the start pulse signal is triggered once.
[0054] The start pulse signal is a signal including at least a single pulse.
[0055] When the digital signal selector receives a start pulse signal, the numerical control delay chain generates a start clock according to the start pulse signal output by the digital signal selector; the start clock is the output of the phase-locked loop. The frequency sampling module receives and determines the frequency data of the start clock within the time length corresponding to the reference clock based on the start clock and the reference clock; the frequency difference accumulation module receives and determines the frequency difference between the frequency data and the target frequency based on the frequency data and the target frequency; the numerical control delay chain receives and corrects the output start clock based on the frequency difference to achieve accurate clock synchronization. In the above process, the generation of the start clock is triggered by the input start pulse signal.
[0056] The phase-locked loop also includes an XOR gate. After the start pulse signal is input into the digital signal selector and the numerically controlled delay chain generates a start clock based on the start pulse signal, since the output signal of the digital signal selector flows to the numerically controlled delay chain at the rear end, port x shows a low level; since the output end of the numerically controlled delay chain outputs the start clock, port y shows a high level. At this time, according to the characteristics of the XOR gate, the XOR gate generates an output signal to the second input end of the digital selector, so that the digital selector can still trigger the signal generation of the numerically controlled delay chain without receiving the start pulse signal, thereby realizing the continuous generation and continuous correction of the start clock.
[0057] Therefore, the above phase-locked loop includes a digital signal selector, a digital control delay chain, a frequency sampling module, a frequency difference accumulation module and an XOR gate, wherein the digital signal selector can trigger the digital control delay chain to generate a start-up clock based on the output signal of the digital selector by receiving a start pulse signal, the frequency sampling module can output corresponding frequency data according to the start-up clock and the input reference clock, and the frequency difference accumulation module can output the corresponding frequency difference to the digital control delay chain according to the frequency data and the input target frequency, so that the digital control delay chain corrects the output start-up clock based on the frequency difference under the triggering of the XOR gate output signal, thereby determining an accurate start-up clock. The phase-locked loop is a pure digital circuit. Compared with the traditional analog phase-locked loop, it saves the oscillator and analog phase detector therein, has low power consumption, fast response, and can achieve rapid start-up; and can quickly start under the triggering of the start pulse signal, and achieve continuous signal output and continuous signal correction.
[0058] In one embodiment, Figure 2 As shown, the digitally controlled delay chain includes: a multi-stage delay chain 122 connected in series and a control logic circuit 124 .
[0059] The input end of the first-stage delay chain is connected to the output end of the digital signal selector, and the output end of the last-stage delay chain is connected to the first input end of the frequency sampling module.
[0060] The input end of the control logic circuit is connected to the output end of the frequency difference accumulation module, and the multiple output ends of the control logic circuit are respectively connected to the controlled ends of each level of delay chain; the control logic circuit is used to determine the control signal according to the frequency difference, and the control signal is used to determine the delay time of each delay chain.
[0061] The delay time of each level of delay chain can be the same or different. The control logic circuit determines the delay time required for each level of delay chain based on the frequency difference, so that the sum of the delay times of all delay chains is the total delay time required for the output signal of the numerically controlled delay chain, that is, the starting clock.
[0062] The delay time corresponding to each level of the delay chain can be determined according to the actual application requirements of the phase-locked loop.
[0063] In one embodiment, Figure 2 As shown, each delay chain includes: a plurality of delay modules 1222 connected in series and a multiplexer 1224 .
[0064] Among them, the types of various delay modules are consistent.
[0065] The types of each delay module are consistent, which can be understood as: the delay time of each delay module in any level is the same. Exemplarily, each delay module in the first-level delay chain can achieve a delay of 1 times; similarly, each delay module in the second-level delay chain can achieve a delay of 3 times; however, the delay time of each delay module in the first-level delay chain is different from the delay time of each delay module in the second-level delay chain. The characteristics of each delay module in the delay chain of other levels are consistent with the above content and will not be repeated here.
[0066] The multiple input ends of the multiplexer are connected to the output ends of each delay module and the input end of the first delay module respectively, the output end of the multiplexer is connected to the input end of the first delay module in the next level delay chain, and the controlled end of the multiplexer is connected to the output end of the control logic circuit to select one of the input ends and output ends of the multiplexer to be turned on under the drive of the control signal.
[0067] Since one input terminal of the multiplexer is connected to the input terminal of the first delay module, in the first-stage delay module, there is a situation where the signal is directly output without passing through any delay module, that is, this stage of the delay chain does not delay the signal.
[0068] In one embodiment, each delay chain satisfies the following conditions:
[0069] N i ≥D i+1
[0070] Among them, N i is the number of delay modules in the i-th delay chain, D i+1 is a multiple of the delay time of the delay module in the (i+1)th delay chain and the delay time of the delay module in the i-th delay chain, where i is an integer greater than or equal to 1.
[0071] Exemplarily, if the numerically controlled delay chain includes three-stage delay chains, and the number of delay modules in each stage of the delay chain is set to 8 (i.e., N1 is 8), and the delay multiple of the delay module in the first-stage delay chain is 1, then correspondingly, the delay multiple of the delay module in the second-stage delay chain is 8 times (i.e., D2 is 8x1), and the delay multiple of the delay module in the third delay chain is 64 times (i.e., D3 is 8x8). Therefore, when the output signal of the numerical control delay module needs to be delayed 7 times, the control logic circuit selects to access 7 delay modules in the first-level delay chain, 0 delay modules in the second-level delay chain, and 0 delay modules in the third-level delay chain based on the control signal; when the output signal of the numerical control delay module needs to be delayed 15 times, the control logic circuit selects to access 7 delay modules in the first-level delay chain, 1 delay module in the second-level delay chain, and 0 delay modules in the third-level delay chain based on the control signal; when the output signal of the numerical control delay module needs to be delayed 78 times, the control logic circuit selects to access 6 delay modules in the first-level delay chain, 1 delay module in the second-level delay chain, and 1 delay module in the third-level delay chain based on the control signal; the control logic for other multiples that need to be delayed is the same as the above content and will not be repeated here.
[0072] The conditions of each delay chain can make the delay range generated by the i-th delay chain overlap with the delay range generated by the i+1-th delay chain, so that the output of the i+1-th delay chain can be supplemented by the output of the i-th delay chain, so as to ensure that the delay multiples of the final output signal of the digital control delay chain are accurate, thereby improving the reliability of the phase-locked loop.
[0073] Furthermore, the conditions of each delay chain can make the phase-locked loop adapt to the design requirements of different integrated circuit processes, thereby eliminating the delay variation caused by the OCV (on-chip variation) factor.
[0074] In one embodiment, Figure 3 As shown, the frequency sampling module includes: a clock divider 132 , a reference clock counter 134 , an oscillation start clock counter 136 and a frequency calculation logic circuit 138 .
[0075] The input end of the clock divider is connected to the output end of the digitally controlled delay chain.
[0076] The clock divider is used to reduce the frequency of the high-frequency output signal of the digitally controlled delay chain to facilitate the subsequent counting of the number of cycles of the output signal of the digitally controlled delay chain.
[0077] The reference clock counter is used to access the reference clock; the reference clock counter is used to determine the time length corresponding to the reference clock.
[0078] The first input end of the start-up clock counter is connected to the output end of the clock divider, and the second input end of the start-up clock counter is connected to the output end of the reference clock counter; the start-up clock counter is used to determine the actual count value of the output signal of the digital control delay chain within the time length.
[0079] The first input end of the frequency calculation logic circuit is connected to the output end of the oscillation start clock counter, the second input end of the frequency calculation logic circuit is connected to the output end of the reference clock counter, and the output end of the frequency calculation logic circuit is connected to the first input end of the frequency difference accumulation module; the frequency calculation logic circuit is used to output frequency data according to the actual count value and time length.
[0080] The frequency data is the frequency of the output signal of the digital control delay chain within the time length corresponding to the reference clock.
[0081] Furthermore, the selection of the reference clock can be determined according to the actual application requirements and the response speed. Generally, the longer the time length corresponding to the reference clock is, the longer the time it takes for the frequency sampling module to determine the frequency data. However, if the reference clock is too short, the output signal of the CNC delay chain may have fewer cycles in a short time length. In extreme cases, there may not even be a complete number of cycles in a short time length. Therefore, the selection of the reference clock needs to take into account both efficiency and data reliability.
[0082] In one embodiment, Figure 4 As shown, the frequency difference accumulation module is a PID (Proportional-Integral-Derivative) controller.
[0083] PID controllers are used to:
[0084] According to the frequency data and the target frequency, a corresponding frequency difference is determined. The frequency difference can be determined based on the operation logic of the subtractor.
[0085] The frequency difference is PID regulated to obtain the PID regulation result. Based on the PID regulation, the current error, past error and future error of the frequency difference are corrected to avoid overshoot and avoid amplifying the noise of the output signal of the frequency sampling module to obtain a more accurate frequency difference. Figure 4 The K in represents the PID adjustment of the frequency difference. The PID adjustment result includes the proportional control result, the integral control result and the differential control result.
[0086] The PID adjustment result is delayed by a unit to determine the accumulated frequency difference.
[0087] The PID adjustment result is delayed by one cycle to achieve the accumulation of frequency difference.
[0088] Based on the summation operation logic, the results of the PID adjustment results after the unit delay are summed and output to determine the accumulated frequency difference.
[0089] Among them, signal D is the frequency data output by the frequency sampling module, and signal E is the frequency difference output by the PID controller.
[0090] In one embodiment, Figure 5 As shown, the above phase-locked loop further includes: a noise shaping module 160 .
[0091] The input end of the noise shaping module is connected to the output end of the frequency difference accumulation module, and the output end of the noise shaping module is connected to the second input end of the numerical control delay chain; the noise shaping module is used to receive and perform noise shaping on the frequency difference.
[0092] The noise module can perform noise shaping on the frequency difference, thereby optimizing the spectrum of the output start-up clock.
[0093] In one embodiment, the noise shaping module includes: a noise generating module 162 and an adder 164 .
[0094] The noise generation module is used to generate white noise.
[0095] The first input end of the adder is connected to the output end of the frequency difference accumulation module, the second input end of the adder is connected to the output end of the noise generation module, and the output end of the adder is connected to the second input end of the digital control delay chain. The adder adds white noise to the frequency difference, thereby increasing the main lobe width of the start-up clock output spectrum to transform the power spectrum of the low-frequency part to the high-frequency part.
[0096] The introduced white noise destroys the periodicity of the final output starting clock and disperses the interference signal to the vicinity of the adjusted expected value. From the spectrum, the amplitude of the starting clock is reduced and its spectrum range is correspondingly widened. In this way, at a certain frequency point, the interference to other signals is reduced.
[0097] In one embodiment, Figure 5 As shown, the above phase-locked loop further includes: a digital low-pass filter 170 .
[0098] The input end of the digital low-pass filter is connected to the output end of the noise shaping module, and the output end of the digital low-pass filter is connected to the second input end of the digital control delay chain.
[0099] The digital low-pass filter performs low-pass filtering on the frequency difference with white noise added thereto to filter out the high-frequency part thereof, thereby improving the purity of the oscillation clock finally outputted.
[0100] In one embodiment, the output signal of the XOR gate is a square wave signal.
[0101] After the phase-locked loop is in working state, the parameters in the phase-locked loop can be adjusted so that the XOR gate can continuously trigger the generation and correction of the oscillation clock at equal intervals. In this case, the output signal of the XOR gate is a square wave signal. By analyzing the square wave signal, the generation timing of the phase-locked loop output signal can be determined.
[0102] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.
[0103] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0104] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.
Claims
1. A phase-locked loop, characterized in that: include: A digital signal selector, wherein the first input terminal of the digital signal selector is used to receive a start pulse signal; A digitally controlled delay chain, wherein a first input end of the digitally controlled delay chain is connected to an output end of the digital signal selector; A frequency sampling module, wherein a first input end of the frequency sampling module is connected to an output end of the digital control delay chain, and a second input end of the frequency sampling module is used to access a reference clock; The frequency sampling module is used to convert the output signal of the digital control delay chain into corresponding frequency data according to the reference clock; A frequency difference accumulation module, wherein the first input end of the frequency difference accumulation module is connected to the output end of the frequency difference sampling module, the second input end of the frequency difference accumulation module is used to access the target frequency, and the output end of the frequency difference accumulation module is connected to the second input end of the digital control delay chain; the frequency difference accumulation module is used to determine and output the frequency difference between the target frequency and the frequency data, so that the digital control delay chain delays the output signal of the digital signal selector based on the frequency difference; An XOR gate, wherein the first input end of the XOR gate is connected to the output end of the digital signal selector, the second input end of the XOR gate is connected to the output end of the digital control delay chain, and the output end of the XOR gate is connected to the second input end of the digital signal selector, so that the digital signal selector continues to output a signal after the start pulse signal is triggered once.
2. The phase-locked loop according to claim 1, characterized in that: The numerically controlled delay chain comprises: A plurality of delay chains connected in series in sequence; wherein the input end of the first delay chain is connected to the output end of the digital signal selector, and the output end of the last delay chain is connected to the first input end of the frequency sampling module; A control logic circuit, wherein the input end of the control logic circuit is connected to the output end of the frequency difference accumulation module, and the multiple output ends of the control logic circuit are respectively connected to the controlled ends of each level of delay chain; the control logic circuit is used to determine the control signal according to the frequency difference, and the control signal is used to determine the delay time of each delay chain.
3. The phase-locked loop according to claim 2, characterized in that: Each of the delay chains comprises: A plurality of delay modules connected in series; wherein the types of the delay modules are all the same; A multiplexer, wherein the multiple input terminals of the multiplexer are respectively connected to the output terminals of the delay modules and the input terminals of the first delay module in a one-to-one correspondence, the output terminal of the multiplexer is connected to the input terminal of the first delay module in the next-level delay chain, and the controlled terminal of the multiplexer is connected to the output terminal of the control logic circuit to select and turn on one of the input terminals and the output terminal of the multiplexer under the drive of the control signal.
4. The phase-locked loop according to claim 3, characterized in that: Each of the delay chains satisfies the following conditions: N i ≥D i+1 Among them, N i is the number of delay modules in the i-th delay chain, D i+1 is a multiple of the delay time of the delay module in the (i+1)th delay chain and the delay time of the delay module in the i-th delay chain, where i is an integer greater than or equal to 1.
5. The phase-locked loop according to claim 1, characterized in that: The frequency sampling module comprises: A clock divider, wherein an input end of the clock divider is connected to an output end of the digitally controlled delay chain; A reference clock counter, the reference clock counter is used to access the reference clock; the reference clock counter is used to determine the time length corresponding to the reference clock; an oscillator clock counter, wherein a first input terminal of the oscillator clock counter is connected to an output terminal of the clock divider, and a second input terminal of the oscillator clock counter is connected to an output terminal of the reference clock counter; the oscillator clock counter is used to determine an actual count value of an output signal of the digital control delay chain within the time length; A frequency calculation logic circuit, wherein the first input end of the frequency calculation logic circuit is connected to the output end of the start-up clock counter, the second input end of the frequency calculation logic circuit is connected to the output end of the reference clock counter, and the output end of the frequency calculation logic circuit is connected to the first input end of the frequency difference accumulation module; the frequency calculation logic circuit is used to output the frequency data according to the actual count value and the time length.
6. The phase-locked loop according to claim 1, characterized in that: The frequency difference accumulation module is a PID controller, and the PID controller is used to: Determining a corresponding frequency difference according to the frequency data and the target frequency; Performing PID adjustment on the frequency difference to obtain a PID adjustment result; A unit delay is performed on the PID adjustment result to determine the accumulated frequency difference.
7. The phase-locked loop according to claim 1, characterized in that: Also includes: A noise shaping module, wherein an input end of the noise shaping module is connected to an output end of the frequency difference accumulation module, and an output end of the noise shaping module is connected to a second input end of the digital control delay chain; The noise shaping module is used to receive and perform noise shaping on the frequency difference.
8. The phase-locked loop according to claim 7, characterized in that: The noise shaping module comprises: A noise generating module, wherein the noise generating module is used to generate white noise; An adder, wherein a first input end of the adder is connected to an output end of the frequency difference accumulation module, a second input end of the adder is connected to an output end of the noise generation module, and an output end of the adder is connected to a second input end of the digital control delay chain.
9. The phase-locked loop according to claim 7, characterized in that: The phase-locked loop also includes: A digital low-pass filter, wherein the input end of the digital low-pass filter is connected to the output end of the noise shaping module, and the output end of the digital low-pass filter is connected to the second input end of the digitally controlled delay chain.
10. The phase-locked loop according to claim 7, characterized in that: The output signal of the XOR gate is a square wave signal.