Time division multiplexed media independent interface and method supporting multi-rate multi-lane communication

Abstract

The application discloses a time division multiplexing medium independent interface and method supporting multi-rate multi-channel communication. The interface comprises a medium access control layer module and a physical coding sublayer module supporting multi-rate multi-channel communication. The medium access control layer module and the physical coding sublayer module share the same path clock signal and channel mode configuration signal. The signal output from the medium access control layer module to the physical coding sublayer module comprises a sending channel time slot signal, a sending data signal, a sending control signal and a sending data and control effective signal. The signal output from the physical coding sublayer module to the medium access control layer module comprises a sending enable signal, a receiving channel time slot signal, a receiving data signal, a receiving control signal and a receiving data and control effective signal. The application aims to solve the problem of various interface types and interface signals in the existing medium independent interface technology and realize the compatibility of multi-rate multi-channel Ethernet with a large rate range.

Description

Technical Field

[0001] This invention relates to the field of network communication chips, and specifically to a Time Division Multiplexing Medium Independent Interface (TDMII) and method that supports multi-rate multi-channel communication. Background Technology

[0002] In network communication chips, the protocol stack typically includes the Media Access Control (MAC) layer, the Physical Coding System (PCS) sublayer, and the Serial-to-Parallel Converter Set (SERDES), etc. Figure 1 As shown. The interface between the MAC and PCS is called the Media Independent Interface (MII), a logical interface used to connect the physical layer with different media types to the control layer with the same rate type media. The interface between the PCS and SERDES is called the Physical Media Attachment (PMA) interface, a physical media adapter interface in high-speed serial-to-parallel converters. Currently, to enable network communication chips to be applied to more communication scenarios, there are usually two design requirements: first, support for multiple rates, that is, the ability to configure SERDES channels to different rates according to application scenario requirements. For example, the SERDES channel rates defined in the IEEE 802.3 Ethernet standard series include 10.3125Gbps, 25.78125Gbps, and 53.125Gbps; second, support for multiple channels, that is, the ability to flexibly bind different numbers of SERDES channels and split network ports according to application scenario requirements. For example, a single 200G network port defined by the IEEE 802.3 Ethernet standard series can be implemented by binding eight SERDES channels at a rate of 25.78125Gbps. This 200G network port can be reconfigured and split into two 100G network ports, each implemented by binding four SERDES channels at a rate of 25.78125Gbps. The aforementioned network port refers to a unit containing MAC, PCS, and SERDES functions, capable of both data transmission and reception.

[0003] To enable network communication chips to support multi-rate, multi-channel characteristics, not only must the underlying SERDES channels support configuration for multiple rate modes, but the PCS and MAC must also have the capability to support multi-rate, multi-channel operation. Therefore, existing technologies typically encapsulate multi-rate PCS and MACs together and connect them to the underlying multi-rate SERDES channels via multiplexers (MUX) and demultiplexers (DEMUX). For example... Figure 2As shown, assuming the SERDES contains 8 channels, and its single-channel rate can be configured to 10.3125Gbps and 25.78125Gbps. To support multi-rate, multi-channel network port modes such as 1×200G, 2×100G, 4×50G, 2×40G, 8×25G, and 8×10G, the following IP logical modules are typically integrated: 1 200G MAC, 1 200G-R8 PCS, 2 100G MACs, 2 100G-R4 PCS, 4 50G MACs, 4 50G-R2 PCS, 2 40G MACs, 2 40G-R4 PCS, 8 25G MACs, 8 25G-R1 PCS, 8 10G MACs, and 8 10G-R1 PCS. In this implementation structure, MACs of different rates and their corresponding PCS are connected using different MII interfaces. Specifically, the 200G MAC and 200G-R8 PCS use the CDMII interface, the 100G MAC and 100G-R4 PCS use the CGMII interface, the 50G MAC and 50G-R2 PCS use the LGMII interface, the 40G MAC and 40G-R4 PCS use the XLGMII interface, and the 10G MAC and 10G-R1 PCS use the XGMII interface.

[0004] Figure 3 and Figure 4 Examples of signal definitions for the existing CDMII and CGMII interfaces are given respectively. *MII_TXD and *MII_TXC are the data transmission and control transmission signals from *MAC to *PCS, respectively; *MII_TXCLK_ENA is the reverse voltage control signal from *PCS to *MAC; *MII_RXD and *MII_RXC are the data reception and control reception signals from *PCS to *MAC, respectively; and *MII_RXCLK_ENA is the valid signal for receiving data and control from *PCS to *MAC (the symbol * represents CD or CG).

[0005] Therefore, it can be seen that in order to support multi-rate, multi-channel communication of network communication chips, the existing MII interface technology has two disadvantages: (1) There are many types of interfaces. For example, in Figure 2 The implementation structure shown includes various MII interface types such as CDMII, CGMII, LGMII, XLGMII, and XGMII. (2) The interface signals are numerous. For example, in Figure 2In the implementation structure shown, the number of signals for the CDMII and CGMII interfaces alone reaches 1158 (578 + 290 × 2 = 1158). As the underlying SERDES technology continues to develop towards higher speeds, network communication chip designs will need to integrate more types of MII interfaces, and the number of signal lines will further increase. This will not only hinder the integration of multi-rate, multi-channel MAC and PCS in the front-end design of network communication chips, but will also cause difficulties in the placement and routing of multi-rate, multi-channel MAC and PCS in the back-end design of network communication chips. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a time-division multiplexing medium-independent interface and method that supports multi-rate multi-channel communication, in response to the above-mentioned problems of the existing medium-independent interface technology. The present invention aims to solve the problem of the large number of interface types and interface signals in the existing medium-independent interface technology, and to achieve compatibility with multi-rate multi-channel Ethernet with a wide range of speeds.

[0007] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0008] A time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication includes a media access control layer module (UMAC) and a physical coding sublayer module (UPCS) supporting multi-rate multi-channel communication. The UMAC and UPCS share the same clock signal TDMII_CLK and channel mode configuration signal CFG_TDMII[23:0]. The signals output from the UMAC to the UPCS include a transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and a transmit data signal TDMII. The signals output from the Physical Coding Sublayer Module UPCS to the Media Access Control Layer Module UMAC include the transmit enable signal TDMII_TXENABLE, the receive channel time slot signal TDMII_RXCHANSLOT[2:0], the receive data signal TDMII_RXDATA, the receive control signal TDMII_RXCTRL, and the receive data and control valid signal TDMII_RXVALID[2:0].

[0009] Optionally, the channel mode configuration signal CFG_TDMII[23:0] can be divided into a maximum of 8 channels, with channel numbers 0, 1, 2, 3, 4, 5, 6, and 7 respectively. The mode of the i-th channel is controlled by the bit field CFG_TDMII[i*3+2 : i*3] of the channel mode configuration signal CFG_TDMII, including: when the bit field CFG_TDMII[i*3+2 : i*3] = 3'b001, it indicates that the i-th channel mode is 10G-R1, and the value of i ranges from {0, 1, 2, 3, 4, 5, 6, 7}; when the bit field CFG_TDMII[i*3+2 : i*3] = 3'b010, it indicates that the i-th channel mode is 25 ... When the bit field CFG_TDMII[i*3+2 : i*3]=3'b011, it indicates that the i-th channel mode is 40G-R4, and the value of i is {0, 4}; when the bit field CFG_TDMII[i*3+2 : i*3]=3'b100, it indicates that the i-th channel mode is 50G-R2, and the value of i is {0, 2, 4, 6}; when the bit field CFG_TDMII[i*3+2 : i*3]=3'b101, it indicates that the i-th channel mode is 100G-R4, and the value of i is {0, 4}; when the bit field CFG_TDMII[i*3+2 : i*3]=3'b01 ...40G-R4, and the value of i is {0, 4}; when the bit field CFG_TDMII[i*3+2 : i*3]=3'b011, it indicates that the i-th channel mode is 40G-R4, and the value of i is {0, 4}; when the bit field CFG_TDMII[i*3+2 : i*3]=3'b011, it indicates that the i-th channel mode is 50G-R2, and the value of i is {0, 2, 4, 6}. [i*3]=3'b110 indicates that the i-th channel mode is 200G-R8, and the value of i is in the range of {0}. Here, 10G-R1 indicates that the network port has a single SERDES channel at the underlying layer, and its SERDES channel rate is configured to 10.3125Gbps; 25G-R1 indicates that the network port has a single SERDES channel at the underlying layer, and its SERDES channel rate is configured to 25.78125Gbps; 40G-R4 indicates that the network port is bound to 4 SERDES channels at the underlying layer, and the rate of each SERDES channel is... The configuration is 10.3125Gbps; 50G-R2 indicates that the network port is bound to 2 SERDES channels at the underlying level, and the rate of each SERDES channel is configured to 25.78125Gbps; 100G-R4 indicates that the network port is bound to 4 SERDES channels at the underlying level, and the rate of each SERDES channel is configured to 25.78125Gbps; 200G-R8 indicates that the network port is bound to 8 SERDES channels at the underlying level, and the rate of each SERDES channel is configured to 25.78125Gbps.

[0010] Optionally, the valid signal TDMII_TXVALID[2:0] for transmitting data and control is used to control the effective bit width of the transmitting data signal TDMII_TXDATA and the transmitting control signal TDMII_TXCTRL. The effective bit width of the receiving direction of the time-division multiplexed medium-independent interface is controlled in a time-division multiplexing manner. The value of the valid signal TDMII_TXVALID[2:0] for transmitting data and control in each clock cycle determines the corresponding transmitting channel number in this clock cycle. The transmitting channel number and the channel mode configuration signal CFG_TDMII[23:0] in this clock cycle determine the transmitting channel mode of the network port in this clock cycle. The transmitting channel mode in this clock cycle determines the specific value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control in this clock cycle.

[0011] Optionally, the transmit channel mode of the current clock cycle determines the specific value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control in the current clock cycle, including: (1) If the channel mode is 10G-R1, the value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}; (2) If the channel mode is 25G-R1, the value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}; (3) If the channel mode is 40G-R4, the value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}; (4) If the channel mode is 50G-R2, the value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}. (5) If the channel mode is 100G-R4, the range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}; (6) If the channel mode is 200G-R8, the range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}. In each transmission channel mode, whether the valid signal TDMII_TXVALID[2:0] for transmitting data and control is 3'b000 depends on the value of the transmit enable signal TDMII_TXENABLE k clock cycles ago. If the transmit enable signal TDMII_TXENABLE = 1 k clock cycles ago, then the valid signal TDMII_TXVALID[2:0] for transmitting data and control takes a value other than 3'b000 in this clock cycle; otherwise, if the transmit enable signal TDMII_TXENABLE = 0 k clock cycles ago, then the valid signal TDMII_TXVALID[2:0] for transmitting data and control takes a value of 3'b000 in this clock cycle.

[0012] Optionally, the effective signal TDMII_RXVALID[2:0] for receiving data and control is used to control the effective bit width of the receiving data signal TDMII_RXDATA and the receiving control signal TDMII_RXCTRL. The effective bit width of the receiving direction of the time-division multiplexed medium-independent interface is controlled in a time-division multiplexing manner. The value of the effective signal TDMII_RXVALID[2:0] for receiving data and control in each clock cycle determines the corresponding receiving channel number in this clock cycle. The receiving channel mode of the network port in this clock cycle is determined according to the receiving channel number and the channel mode configuration signal CFG_TDMII[23:0] in this clock cycle. The receiving channel mode in this clock cycle determines the specific value range of the effective signal TDMII_RXVALID[2:0] for receiving data and control in this clock cycle.

[0013] Optionally, the specific value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control in this clock cycle is determined by the receiving channel mode of this clock cycle, including: (1) if the channel mode is 10G-R1, the value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control is {3'b001}; (2) if the channel mode is 25G-R1, the value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control is {3'b001}; The value range of LID[2:0] is {3'b001}; (3) If the channel mode is 40G-R4, the value range of TDMII_TXVALID[2:0] and TDMII_RXVALID[2:0] is {3'b001}; (4) If the channel mode is 50G-R2, the value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control is {3'b001}; (5) If the channel mode is 100G -R4, then the range of the valid signal TDMII_RXVALID[2:0] for receiving data and control is {3'b010}; (6) If the channel mode is 200G-R8, then the range of the valid signal TDMII_RXVALID[2:0] for receiving data and control is {3'b100}; In each receiving channel mode, whether the specific value of the valid signal TDMII_RXVALID[2:0] for receiving data and control is 3'b000 depends on whether the receiving channel corresponding to the physical coding sub-layer module UPCS has data to be transmitted to the medium access control layer module UMAC in this clock cycle; if there is data to be transmitted, then the valid signal TDMII_RXVALID[2:0] for receiving data and control takes a value other than 3'b000 in this clock cycle; otherwise, if there is no data to be transmitted, then the valid signal TDMII_RXVALID[2:0] for receiving data and control takes a value of 3'b000 in this clock cycle.

[0014] Furthermore, the present invention also provides an application method for the aforementioned time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication, comprising constructing multiple time-division multiplexing medium-independent interfaces supporting multi-rate multi-channel communication into one of the following six homogeneous network port channel modes: (1) 8×10G-R1, indicating that the time-division multiplexing medium-independent interface is sequentially split into 8 network ports with a channel mode of 10G-R1, and the assigned channel numbers are {0, 1, 2, 3, 4, 5, 6, 7}, and the value of its channel mode configuration signal CFG_TDMII is {8{3'b001}}; (2) 8×25G-R1, indicating that the time-division multiplexing medium-independent interface is sequentially split into 8 network ports with a channel mode of 25G-R1, and the assigned channel numbers are {0, 1, 2, 3, 4, 5, 6, 7}, and the value of its channel mode configuration signal CFG_TDMII is {8{3'b001}}; 1, 2, 3, 4, 5, 6, 7}, the channel mode configuration signal CFG_TDMII value is {8{3'b010}}; (3) 2×40G-R4, indicating that the time-division multiplexing medium-independent interface is sequentially split into two network ports with channel mode of 40G-R4, the allocated channels are numbered {0, 4}, and the channel mode configuration signal CFG_TDMII value is {2{{3'b011}, 3{3'bzzz}}}; (4) 4×50G-R2, indicating that the time-division multiplexing medium-independent interface is sequentially split into four network ports with channel mode of 50G-R2, the allocated channel numbers are {0, 2, 4, 6}, and the channel mode configuration signal CFG_TDMII value is {4{{3'b100}, {3'bzzz}}};(5)2×100G-R4, indicating that the time-division multiplexing medium-independent interface is sequentially split into two network ports with channel mode of 100G-R4, and the assigned channel numbers are {0, 4}, and the channel mode configuration signal CFG_TDMII value is {2{{3'b101},3{3'bzzz}}};(6)1×200G-R8, indicating that the time-division multiplexing medium-independent interface is used as a network port with channel mode of 200G-R8, and the assigned channel number is {0}, and the channel mode configuration signal CFG_TDMII value is {{3'b101},7{3'bzzz}}}, where {3'bzzz} represents a 3-bit signal with each bit taking any value.

[0015] Optionally, in the six homogeneous network port channel modes: (1) In the 8×10G-R1 homogeneous network port channel mode, the values ​​of the transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and the receive channel time slot signal TDMII_RXCHANSLOT[2:0] in the first to the eighth scheduling cycles are {0, 4, 2, 6, 1, 5, 3, 7}, and each channel mode allocates 1 / 8 of the clock cycle to the 25G-R1 network port; (2) In the 8×25G-R1 homogeneous network port channel mode, the transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and the receive channel time slot signal TDMII_RXCHANSLOT[2:0] are assigned to the 25G-R1 network port in the first to the eighth scheduling cycles respectively. The values ​​of TDMII_RXCHANSLOT[2:0] in the first to eighth scheduling cycles are {0, 4, 2, 6, 1, 5, 3, 7}, which means that each network port with a channel mode of 25G-R1 is allocated 1 / 8 of the clock cycle; (3) In the 2×40G-R4 homogeneous network port channel mode, the values ​​of the transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and the receive channel time slot signal TDMII_RXCHANSLOT[2:0] in the first to eighth scheduling cycles are {0, 4, 0, 4, 0, 4, 0, 4}, and each network port with a channel mode of 40G-R4 is allocated 4 / (4) In the 4×50G-R2 homogeneous network port channel mode, the values ​​of the transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and the receive channel time slot signal TDMII_RXCHANSLOT[2:0] in the 1st to 8th scheduling cycles are {0, 4, 2, 6, 0, 4, 2, 6}, and 2 / 8 of the clock cycles are allocated to each network port with channel mode 50G-R2; (5) In the 2×100G-R4 homogeneous network port channel mode, the transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and the receive channel time slot signal TDMII_RXCHANSLOT[2:0] are assigned to the network port with channel mode 50G-R2. The values ​​of NSLOT[2:0] in the first to the eighth scheduling cycles are {0, 4, 0, 4, 0, 4, 0, 4}, which allocate 4 / 8 of the clock cycles for each network port with a channel mode of 100G-R4; (6) In the channel mode of 1×200G-R8 homogeneous network port, the values ​​of the transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and the receive channel time slot signal TDMII_RXCHANSLOT[2:0] in the first to the eighth scheduling cycles are {0, 0, 0, 0, 0, 0, 0}, which allocate all 8 / 8 of the clock cycles for a single network port with a channel mode of 200G-R8.

[0016] In addition, the present invention also provides an application method for the aforementioned time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication, including constructing multiple time-division multiplexing medium-independent interfaces supporting multi-rate multi-channel communication into one of the following four heterogeneous network port channel modes: (1) 1×100G-R4+2×50G-R2, the time-division multiplexing medium-independent interface is sequentially split into 1 network port with channel mode 100G-R4 and 2 network ports with channel mode 50G-R2, the assigned channel numbers are {0, 4, 6}, and the channel mode configuration signal value is CFG_TDMII[23:0]={{3'b101},3{3'bzzz},2{{3'b100},{3'bzzz}}}; (2) 4×25G-R1+1×40G-R4, the time-division multiplexing medium-independent interface is sequentially split into 4 One network port with channel mode 25G-R1 and one network port with channel mode 40G-R4 are assigned channel numbers {0, 1, 2, 3, 4} respectively, and their channel mode configuration signal value is CFG_TDMII[23:0]={4{3'b010},{3'b011},3{3'bzzz}}; (3) 1×50G-R2+2×25G-R1+1×100G-R4, the time division multiplexing medium-independent interface is sequentially split into one network port with channel mode 50G-R2, two network ports with channel mode 25G-R1 and one network port with channel mode 100G-R4, assigned channel numbers {0, 2, 3, 4} respectively, and their channel mode configuration signal value is CFG_TDMII[23:0]={{3'b100},{3'bzzz}, 2{3'b010},{3'b101},3{3'bzzz}};(4)2×10G-R1+1×50G-R2+2×25G-R1+1×50G-R2, the time-division multiplexing medium-independent interface is sequentially divided into 2 network ports with channel mode 10G-R1, 1 network port with channel mode 50G-R2, 2 network ports with channel mode 25G-R1 and 1 network port with channel mode 50G-R2, and their assigned channel numbers are {0, 1, 2, 4, 5, 6}, and their channel mode configuration signal value is CFG_TDMII[23:0] ={2{3'b001},{3'b001},{3'bzzz},2{3'b010},{3'b100},{3'bzzz}}, where {3'bzzz} represents a 3-bit signal where each bit can take any value.

[0017] Optionally, in the four heterogeneous network port channel modes: (1) In the 1×100G-R4+2×50G-R2 heterogeneous network port channel mode, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned the values ​​{0, 4, 0, 6, 0, 4, 0, 6} respectively from the 1st to the 8th scheduling period, allocating 4 / 8 of the clock cycle for a single network port with channel mode 100G-R4 and 2 / 8 of the clock cycle for each network port with channel mode 50G-R2; (2) In the 4×25G-R1+1 In the ×40G-R4 heterogeneous network port channel mode, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned the values ​​{0, 4, 2, 4, 1, 4, 3, 4} respectively from the 1st to the 8th scheduling period. This allocates 1 / 8 of the clock cycle to each network port with a channel mode of 25G-R1 and 4 / 8 of the clock cycle to a single network port with a channel mode of 40G-R4; (3) In the 1×50G-R2+2×25G-R1+1×100G-R4 heterogeneous network port channel mode, the channel time slot signals... The values ​​of TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] in the first to the eighth scheduling cycles are {0, 4, 2, 4, 0, 4, 3, 4}, respectively. 2 / 8 of the clock cycle is allocated to a single network port with a 50G-R2 channel mode, 1 / 8 of the clock cycle is allocated to each network port with a 25G-R1 channel mode, and 4 / 8 of the clock cycle is allocated to a single network port with a 100G-R4 channel mode; (4) 2×10G-R1+1×50G-R2+2×25G-R1+1×50G-R2 heterogeneous network In port channel mode, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned the values ​​{0, 4, 2, 6, 1, 4, 3, 6} in the 1st to 8th scheduling cycles, respectively. 1 / 8 of the clock cycle is allocated to each network port with channel mode 10G-R1, 2 / 8 of the clock cycle is allocated to a single network port with channel mode 50G-R2, 1 / 8 of the clock cycle is allocated to each network port with channel mode 25G-R1, and 2 / 8 of the clock cycle is allocated to a single network port with channel mode 50G-R2.

[0018] Compared with the prior art, the present invention has the following main advantages: The time-division multiplexing medium-independent interface of the present invention includes a medium access control layer module and a physical coding sublayer module supporting multi-rate multi-channel communication. The medium access control layer module and the physical coding sublayer module share the same clock signal and channel mode configuration signal. The signals output by the medium access control layer module to the physical coding sublayer module include a transmit channel time slot signal, a transmit data signal, a transmit control signal, and a transmit data and control valid signal. The signals output by the physical coding sublayer module to the medium access control layer module include a transmit enable signal, a receive channel time slot signal, a receive data signal, a receive control signal, and a receive data and control valid signal. The time-division multiplexing media-independent interface of this invention, by providing effective control signals, solves the problem of numerous interface types and signals in existing media-independent interface technologies. Considering that 200G, 100G, 50G, 40G, and 10G are the mainstream applications in the current Ethernet market, and that single-channel speeds of 25.78125Gbps and 10.3125Gbps are commonly used configurations, this invention primarily targets Ethernet within this single-channel speed range. The time-division multiplexing media-independent interface of this invention can achieve compatibility with multi-rate, multi-channel Ethernet across a wide speed range, including 200G, 100G, 50G, 40G, 10G, 25.78125Gbps, and 10.3125Gbps. This invention is applicable to time-division multiplexing media-independent interface (TDMII) connections between the Physical Coding Sublayer (PCS) and the Media Access Control (MAC) layer in multi-rate, multi-channel communication. Compared to existing Media Independent Interface (MII) technology, this invention enables communication between multi-rate, multi-channel PCS and multi-rate, multi-channel MAC using channelized time-division multiplexing. This simplifies the connection signals between the multi-rate, multi-channel PCS and multi-rate, multi-channel MAC, resolving the issues of numerous interface types and signals present in existing MII technology. This invention facilitates both the integration of multi-rate, multi-channel MAC and multi-rate, multi-channel PCS in the front-end design of network communication chips and the placement and routing of multi-rate, multi-channel MAC and multi-rate, multi-channel PCS in the back-end design of network communication chips. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the underlying protocol stack structure of a multi-rate, multi-channel network communication chip in the prior art.

[0020] Figure 2 This is a schematic diagram illustrating the communication principle of existing multi-rate, multi-channel network communication chips.

[0021] Figure 3 This is a schematic diagram of the signal definition for the existing CDMII interface.

[0022] Figure 4This is a schematic diagram of the signal definition for the existing CGMII interface.

[0023] Figure 5 This is a schematic diagram of the signal definition of TDMII in an embodiment of the present invention.

[0024] Figure 6 This is a schematic diagram of the TDMII mode configuration in an embodiment of the present invention.

[0025] Figure 7 This is a schematic diagram of channel scheduling in the isomorphic channel mode of TDMII in an embodiment of the present invention.

[0026] Figure 8 This is a schematic diagram of channel scheduling in the heterogeneous channel mode of TDMII in an embodiment of the present invention.

[0027] Figure 9 This is a schematic diagram of the effective bit width of TDMII in an embodiment of the present invention.

[0028] Figure 10 This is a typical timing diagram of TDMII in an embodiment of the present invention, where (a) is the data transmission direction and (b) is the data reception direction.

[0029] Figure 11 The following are application examples of TDMII in the embodiments of the present invention, wherein (a) is an example of the first application scenario and (b) is an example of the second application scenario. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] like Figure 5As shown, this embodiment provides a Time Division Multiplexing Medium Independent Interface (TDMII) supporting multi-rate multi-channel communication, including a Media Access Control (UMAC) module and a Physical Coding Sub-layer (UPCS) module supporting multi-rate multi-channel communication. The UMAC and UPCS modules share the same clock signal TDMII_CLK and channel mode configuration signal CFG_TDMII[23:0]. The signals output from the UMAC to the UPCS include a transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and a transmit data signal TDMII_TXDAT. A. Send control signal TDMII_TXCTRL and valid signal for sending data and control TDMII_TXVALID[2:0]; The signals output from the physical coding sublayer module UPCS to the media access control layer module UMAC include the send enable signal TDMII_TXENABLE, the receive channel time slot signal TDMII_RXCHANSLOT[2:0], the receive data signal TDMII_RXDATA, the receive control signal TDMII_RXCTRL and valid signal for receiving data and control TDMII_RXVALID[2:0], where [23:0] represents a 24-bit width and [2:0] represents a 3-bit width. The specific description of the interface signals is as follows: (1) TDMII interface clock signal (TDMII_CLK), 1 bit wide, is input from outside the TDMII interface and drives the UMAC and UPCS to work. To ensure that each SERDES channel supports a maximum data transmission of 25.78125Gbps, the minimum operating frequency of TDMII_CLK is (25.78125*64 / 66) / (256 / 8)=0.78125GHz. (2) TDMII interface channel mode configuration signal (CFG_TDMII), 24 bits wide, is input from outside the TDMII interface and determines the working mode of UMAC and UPCS. The channel mode configuration signal CFG_TDMII[23:0] is used to control the channel mode when UMAC and UPCS are working. The TDMII interface supports a maximum of 8 channels, with channel numbers 0, 1, 2, 3, 4, 5, 6, and 7 respectively. The mode of the i-th channel of the TDMII interface is controlled by the CFG_TDMII[i*3+2 : i*3] bit field. (3) TDMII interface transmit channel time slot signal (TDMII_TXCHANSLOT), 3 bits wide, is output from UMAC to UPCS. This signal is used to indicate the transmit channel corresponding to the TDMII_TXDATA[255:0], TDMII_TXCTRL[31:0], TDMII_TXVALID[2:0], and TDMII_TXENABLE signals in each clock cycle.The valid value range of TDMII_TXCHANSLOT[2:0] is {3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110, 3'b111}, which respectively indicate that the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, and 7th channels of the UMAC are sending data characters and control characters. (4) The TDMII interface sends a data signal (TDMII_TXDATA), which is 256 bits wide and is output from the UMAC to the UPCS. (5) The TDMII interface sends a control signal (TDMII_TXCTRL), which is 32 bits wide and is output from the UMAC to the UPCS. Each bit of the control signal TDMII_TXCTRL[31:0] is used to indicate whether the 1 byte of information corresponding to TDMII_TXDATA[255:0] is a data character or a control character. When TDMII_TXCTRL[m]=0, it means that data characters are transmitted on TDMII_TXDATA[m*8+7:m*8]; when TDMII_TXCTRL[m]=1, it means that control characters are transmitted on TDMII_TXDATA[m*8+7:m*8]. (6) The valid signal for sending data and control on the TDMII interface (TDMII_TXVALID), 3 bits wide, is output from UMAC to UPCS. The valid value range of TDMII_TXVALID[2:0] is {3'b100, 3'b010, 3'b001, 3'b000}. When TDMII_TXVALID[2:0]=3'b100, it indicates that TDMII_TXDATA[255:0] and TDMII_TXCTRL[31:0] are valid in the current clock cycle; when TDMII_TXVALID[2:0]=3'b010, it indicates that TDMII_TXDATA[127:0] and TDMII_TXCTRL[15:0] are valid in the current clock cycle, and the remaining bit fields are invalid. When TDMII_TXVALID[2:0]=3'b001, it indicates that TDMII_TXDATA[63:0] and TDMII_TXCTRL[7:0] are valid in the current clock cycle, and the remaining bit fields are invalid. When TDMII_TXVALID[2:0]=3'b000, it indicates that TDMII_TXDATA[255:0] and TDMII_TXCTRL[31:0] are invalid in the current clock cycle. (7) TDMII interface transmit enable signal (TDMII_TXENABLE), 1 bit wide, output from UPCS to UMAC.When TDMII_TXENABLE=0, it means that UPCS cannot receive data and control signals sent by UMAC in the k-th clock cycle starting from the current clock cycle; when TDMII_TXENABLE=1, it means that UPCS can receive data and control signals sent by UMAC in the k-th clock cycle starting from the current clock cycle. If k=0, the TDMII_TXENABLE signal value indicates whether UPCS can receive data and control signals sent by UMAC in the current clock cycle. (8) TDMII interface receive channel time slot signal (TDMII_RXCHANSLOT), 3 bits wide, is output by UPCS to UMAC. This signal is used to indicate the receive channel corresponding to the TDMII_RXDATA[255:0], TDMII_RXCTRL[31:0] and TDMII_RXVALID[2:0] signals in each clock cycle. The valid value range of TDMII_RXCHANSLOT[2:0] is {3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110, 3'b111}, which respectively indicate that channels 0, 1, 2, 3, 4, 5, 6, and 7 of the UMAC are receiving data characters and control characters. (9) The TDMII interface receives data signals (TDMII_RXDATA), which are 256 bits wide and are output from UPCS to UMAC. (10) The TDMII interface receives control signals (TDMII_RXCTRL), which are 32 bits wide and are output from UPCS to UMAC. Each bit of the receive control signal RDMII_TXCTRL[31:0] is used to indicate whether the 1 byte of information corresponding to TDMII_RXDATA[255:0] is a data character or a control character. When RDMII_TXCTRL[n]=0, it means that data characters are transmitted on RDMII_TXDATA[n*8+7:n*8]; when RDMII_TXCTRL[n]=1, it means that control characters are transmitted on RDMII_TXDATA[n*8+7:n*8]. (11) The valid signal for receiving data and control on the TDMII interface (TDMII_RXVALID), which is 3 bits wide, is output from UPCS to UMAC. The valid value range of TDMII_RXVALID[2:0] is 3'b100, 3'b010, 3'b001, 3'b000.When TDMII_RXVALID[2:0]=3'b100, it indicates that TDMII_RXDATA[255:0] and TDMII_RXCTRL[31:0] are valid in the current clock cycle; when TDMII_RXVALID[2:0]=3'b010, it indicates that TDMII_RXDATA[127:0] and TDMII_RXCTRL[15:0] are valid in the current clock cycle, and the remaining bit fields are invalid. When TDMII_RXVALID[2:0]=3'b001, it indicates that TDMII_RXDATA[63:0] and TDMII_RXCTRL[7:0] are valid in the current clock cycle, and the remaining bit fields are invalid. When TDMII_RXVALID[2:0]=3'b000, it indicates that TDMII_RXDATA[255:0] and TDMII_RXCTRL[31:0] are invalid in the current clock cycle.

[0032] The definitions between the Media Access Control (UMAC) module and the Physical Coding Sublayer (UPCS) module include TDMII interface signals, TDMII interface modes, TDMII interface channel scheduling, and TDMII interface effective bit width.

[0033] 1) TDMII interface signals

[0034] The TDMII interface is used to connect UMAC and UPCS, where UMAC and UPCS refer to MAC and PCS that support multi-rate multi-channel communication, respectively. The specific implementation is determined by the user using the TDMII interface, but the signal interaction between them must comply with the TDMII interface specification. The TDMII interface signals specifically include: (1) TDMII interface clock signal (TDMII_CLK), 1 bit wide, input from outside the TDMII interface and drives the UMAC and UPCS to work; (2) TDMII interface channel mode configuration signal (CFG_TDMII), 24 bits wide, input from outside the TDMII interface and determines the working mode of the UMAC and UPCS; (3) TDMII interface transmit channel time slot signal (TDMII_TXCHANSLOT), 3 bits wide, output from UMAC to UPCS; (4) TDMII interface transmit data signal (TDMII_TXDATA), 256 bits wide, output from UMAC to UPCS; (5) TDMII interface transmit control signal (TDMII_TXCTRL), 32 bits wide, output from UMAC to UPCS; (6) TDMII interface transmit data (7) The TDMII interface sends an enable signal (TDMII_TXVALID), 3 bits wide, from the UMAC to the UPCS; (8) The TDMII interface receives a channel time slot signal (TDMII_RXCHANSLOT), 3 bits wide, from the UPCS to the UMAC; (9) The TDMII interface receives a data signal (TDMII_RXDATA), 256 bits wide, from the UPCS to the UMAC; (10) The TDMII interface receives a control signal (TDMII_RXCTRL), 32 bits wide, from the UPCS to the UMAC; (11) The TDMII interface receives a valid signal for both data and control (TDMII_RXVALID), 3 bits wide, from the UPCS to the UMAC.

[0035] In the data transmission direction from UMAC to UPCS, each bit of the transmission control signal TDMII_TXCTRL[31:0] indicates whether the byte of information corresponding to the transmission data signal TDMII_TXDATA[255:0] is a data character or a control character. When TDMII_TXCTRL[m]=0, it indicates that a data character is transmitted on TDMII_TXDATA[m*8+7:m*8]; when TDMII_TXCTRL[m]=1, it indicates that a control character is transmitted on TDMII_TXDATA[m*8+7:m*8].

[0036] The TDMII_TXENABLE enable signal is used to control the UMAC's data transmission behavior based on the UPCS's real-time data reception capability. When TDMII_TXENABLE = 0, it indicates that the UPCS cannot receive data and control signals transmitted by the UMAC in the k-th clock cycle starting from the current clock cycle; when TDMII_TXENABLE = 1, it indicates that the UPCS can receive data and control signals transmitted by the UMAC in the k-th clock cycle starting from the current clock cycle. If parameter k = 0, the TDMII_TXENABLE signal value indicates whether the UPCS can receive data and control signals transmitted by the UMAC within the current clock cycle.

[0037] The valid data and control signal TDMII_TXVALID[2:0] is used to indicate the validity of the TDMII_TXDATA[255:0] and TDMII_TXCTRL[31:0] bit fields in each clock cycle. The valid value range of TDMII_TXVALID[2:0] is {3'b100, 3'b010, 3'b001, 3'b000}. When TDMII_TXVALID[2:0]=3'b100, it means that TDMII_TXDATA[255:0] and TDMII_TXCTRL[31:0] are valid in the current clock cycle; when TDMII_TXVALID[2:0]=3'b010, it means that TDMII_TXDATA[127:0] and TDMII_TXCTRL[15:0] are valid in the current clock cycle, and the other bit fields are invalid. When TDMII_TXVALID[2:0]=3'b001, it means that TDMII_TXDATA[63:0] and TDMII_TXCTRL[7:0] are valid during the current clock cycle, and the other bit fields are invalid. When TDMII_TXVALID[2:0]=3'b000, it means that TDMII_TXDATA[255:0] and TDMII_TXCTRL[31:0] are invalid during the current clock cycle.

[0038] The transmit channel time slot signal TDMII_TXCHANSLOT[2:0] is used to indicate the transmit channel corresponding to the TDMII_TXDATA[255:0], TDMII_TXCTRL[31:0], TDMII_TXVALID[2:0], and TDMII_TXENABLE signals in each clock cycle. The TDMII interface supports a maximum of 8 transmit channels. The valid value range of TDMII_TXCHANSLOT[2:0] is {3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110, 3'b111}, which respectively represent that the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, and 7th channels of the UMAC are transmitting data characters and control characters.

[0039] In the data reception direction from UPCS to UMAC, each bit of the receive control signal RDMII_RXCTRL[31:0] is used to indicate whether the byte of information corresponding to the receive data signal TDMII_RXDATA[255:0] is a data character or a control character. When RDMII_TXCTRL[n]=0, it means that data characters are transmitted on RDMII_TXDATA[n*8+7:n*8]; when RDMII_TXCTRL[n]=1, it means that control characters are transmitted on RDMII_TXDATA[n*8+7:n*8].

[0040] The valid signal TDMII_RXVALID[2:0] for receiving data and control is used to indicate the validity of the TDMII_RXDATA[255:0] and TDMII_RXCTRL[31:0] bit fields in each clock cycle. The valid value range of TDMII_RXVALID[2:0] is 3'b100, 3'b010, 3'b001, and 3'b000. When TDMII_RXVALID[2:0] = 3'b100, it means that TDMII_RXDATA[255:0] and TDMII_RXCTRL[31:0] are valid in the current clock cycle; when TDMII_RXVALID[2:0] = 3'b010, it means that TDMII_RXDATA[127:0] and TDMII_RXCTRL[15:0] are valid in the current clock cycle, and the other bit fields are invalid. When TDMII_RXVALID[2:0]=3'b001, it means that TDMII_RXDATA[63:0] and TDMII_RXCTRL[7:0] are valid in the current clock cycle, and the other bit fields are invalid. When TDMII_RXVALID[2:0]=3'b000, it means that TDMII_RXDATA[255:0] and TDMII_RXCTRL[31:0] are invalid in the current clock cycle.

[0041] The receive channel time slot signal TDMII_RXCHANSLOT[2:0] is used to indicate the receive channel corresponding to the TDMII_RXDATA[255:0], TDMII_RXCTRL[31:0], and TDMII_RXVALID[2:0] signals in each clock cycle. The TDMII interface supports a maximum of 8 receive channels. The valid value range of TDMII_RXCHANSLOT[2:0] is {3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110, 3'b111}, which respectively represent that the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, and 7th channels of the UMAC are receiving data characters and control characters.

[0042] 2) TDMII interface mode

[0043] The channel mode configuration signals CFG_TDMII[23:0] are used to control the channel mode when UMAC and UPCS are working, specifically including network port splitting method, channel binding method, channel rate, etc. Since the TDMII interface supports a maximum of 8 channels, their channel numbers are 0, 1, 2, 3, 4, 5, 6, and 7. The mode of the i-th channel of the TDMII interface is controlled by the CFG_TDMII[i*3+2 : i*3] bit field.

[0044] like Figure 6 As shown, in this embodiment, the specific correspondence between the configuration value of the channel mode configuration signal CFG_TDMII[i*3+2 : i*3] (bits i*3 to i*3+2) and the mode of the i-th channel is as follows: When CFG_TDMII[i*3+2 : i*3] = 3'b001, it indicates that the mode of the i-th channel is 10G-R1, and the value of i is in the range of {0, 1, 2, 3, 4, 5, 6, 7}; when CFG_TDMII[i*3+2 : i*3] = 3'b010, it indicates that the mode of the i-th channel is 25 ... When CFG_TDMII[i*3+2 : i*3]=3'b011, it means the i-th channel mode is 40G-R4, and the value of i is in the range of {0, 4}; when CFG_TDMII[i*3+2 : i*3]=3'b100, it means the i-th channel mode is 50G-R2, and the value of i is in the range of {0, 2, 4, 6}; when CFG_TDMII[i*3+2 : i*3]=3'b101, it means the i-th channel mode is 100G-R4, and the value of i is in the range of {0, 4}; when CFG_TDMII[i*3+2 : i*3]=3'b110, it means the i-th channel mode is 200G-R8, and the value of i is in the range of {0}. Figure 6 In this context, CFG_XXX_TDMI represents the 3 XXX bits of the channel mode configuration signal CFG_TDMII[23:0], including [2:0], [5:3], [8:6], etc., which correspond to the i*3 to i*3+2 bits mentioned earlier, as shown in the example below. Figure 6 As shown above, in the descriptions related to channel mode configuration, the specific meanings of various channel modes are as follows: 10G-R1 indicates that the network port has a single SERDES channel at its underlying layer, and its SERDES channel rate is configured to 10.3125Gbps; 25G-R1 indicates that the network port has a single SERDES channel at its underlying layer, and its SERDES channel rate is configured to 25.78125Gbps; 40G-R4 indicates that the network port is bound to 4 SERDES channels at its underlying layer, and the rate of each SERDES channel is configured to 10.3125Gbps. 3125Gbps; 50G-R2 indicates that the network port is bound to 2 SERDES channels at the underlying level, and the rate of each SERDES channel is configured to 25.78125Gbps; 100G-R4 indicates that the network port is bound to 4 SERDES channels at the underlying level, and the rate of each SERDES channel is configured to 25.78125Gbps; 200G-R8 indicates that the network port is bound to 8 SERDES channels at the underlying level, and the rate of each SERDES channel is configured to 25.78125Gbps.

[0045] The TDMII interface supports both homogeneous and heterogeneous network port channel modes. Homogeneous network port channel mode means that the network port generated by the channel mode configuration signal CFG_TDMII[23:0] has only one channel mode. For example... Figure 7 As shown, the TDMII interface supports a total of 6 homogeneous network port channel modes (homogeneous channel modes), specifically including: (1) 8×10G-R1, which means that the TDMII interface is sequentially split into 8 network ports with channel mode of 10G-R1, and the assigned channel numbers are {0, 1, 2, 3, 4, 5, 6, 7}, and its channel mode configuration signal value is CFG_TDMII[23:0]={8{3'b001}}. (2) 8×25G-R1, which means that the TDMII interface is sequentially split into 8 network ports with channel mode of 25G-R1, and the assigned channel numbers are {0, 1, 2, 3, 4, 5, 6, 7}, and its channel mode configuration signal value is CFG_TDMII[23:0] ={8{3'b010}}. (3) 2×40G-R4, that is, the TDMII interface is sequentially split into two network ports with channel mode of 40G-R4, and the assigned channels are numbered {0, 4} respectively. The channel mode configuration signal value is CFG_TDMII[23:0]={2{{3'b011},3{3'bzzz}}}. (4) 4×50G-R2, that is, the TDMII interface is sequentially split into four network ports with channel mode of 50G-R2, and the assigned channels are numbered {0, 2, 4, 6} respectively. The channel mode configuration signal value is CFG_TDMII[23:0]={4{{3'b100}, {3'bzzz}}}. (5) 2×100G-R4, that is, the TDMII interface is sequentially split into two network ports with channel mode of 100G-R4, and the assigned channel numbers are {0, 4}, and the channel mode configuration signal value is CFG_TDMII[23:0]={2{{3'b101},3{3'bzzz}}}. (6) 1×200G-R8, that is, the TDMII interface is used as one network port with channel mode of 200G-R8, and the assigned channel number is {0}, and the channel mode configuration signal value is CFG_TDMII[23:0]={{3'b101},7{3'bzzz}}}. The above {3'bzzz} represents a 3-bit signal with each bit taking any value.

[0046] Heterogeneous network port channel mode refers to a network port that has at least two channel modes generated according to the channel mode configuration signal CFG_TDMII[23:0]. For example... Figure 8As shown, the TDMII interface can flexibly support a variety of heterogeneous network port channel modes (heterogeneous channel modes), for example (but not limited to): (1) 1×100G-R4+2×50G-R2, that is, the TDMII interface is sequentially split into 1 network port with channel mode 100G-R4 and 2 network ports with channel mode 50G-R2, and the assigned channel numbers are {0, 4, 6} respectively. The channel mode configuration signal value is CFG_TDMII[23:0]={{3'b101},3{3'bzzz}, 2{{3'b100},{3'bzzz}}}. (2) 4×25G-R1+1×40G-R4, that is, the TDMII interface is sequentially split into 4 network ports with channel mode 25G-R1 and 1 network port with channel mode 40G-R4, and the assigned channel numbers are {0, 1, 2, 3, 4}, and the channel mode configuration signal value is CFG_TDMII[23:0]={4{3'b010},{3'b011},3{3'bzzz}}. (3) 1×50G-R2+2×25G-R1+1×100G-R4, that is, the TDMII interface is sequentially split into 1 network port with channel mode 50G-R2, 2 network ports with channel mode 25G-R1 and 1 network port with channel mode 100G-R4, and the assigned channel numbers are {0, 2, 3, 4} respectively. The channel mode configuration signal value is CFG_TDMII[23:0]={{3'b100},{3'bzzz},2{3'b010},{3'b101},3{3'bzzz}}. (4) 2×10G-R1+1×50G-R2+2×25G-R1+1×50G-R2, that is, the TDMII interface is sequentially split into 2 network ports with channel mode 10G-R1, 1 network port with channel mode 50G-R2, 2 network ports with channel mode 25G-R1 and 1 network port with channel mode 50G-R2, and their assigned channel numbers are {0, 1, 2, 4, 5, 6}, respectively. The channel mode configuration signal value is CFG_TDMII[23:0] ={2{3'b001},{3'b001},{3'bzzz},2{3'b010}, {3'b100},{3'bzzz}}. The above {3'bzzz} represents a 3-bit signal where each bit is any value.

[0047] 3) TDMII interface channel scheduling

[0048] The transmit channel time slot signal TDMII_TXCHANSLOT[2:0] is used to schedule the various transmit channels that transmit data and control characters from UMAC to UPCS. The receive channel time slot signal TDMII_RXCHANSLOT[2:0] is used to schedule the various receive channels that receive data and control characters from UPCS to UMAC. Scheduling of both transmit and receive channels is based on a single clock cycle and uses time-division multiplexing. Each transmit channel shares the signals MII_TXDATA[255:0], TDMII_TXCTRL[31:0], TDMII_TXVALID[2:0], and TDMII_TXENABLE. Each receive channel shares the signals TDMII_RXDATA[255:0], TDMII_RXCTRL[31:0], and TDMII_RXVALID[2:0]. The scheduling of transmit channels is handled by UMAC and typically begins after UMAC is reset. The scheduling of the receive channels is handled by the UPCS, and scheduling is typically initiated after the UPCS is reset. Once channel scheduling is initiated, consecutive clock cycles are cyclically numbered as: scheduling cycle 1, scheduling cycle 2, scheduling cycle 3, scheduling cycle 4, scheduling cycle 5, scheduling cycle 6, scheduling cycle 7, scheduling cycle 8, scheduling cycle 1, scheduling cycle 2. Channel scheduling involves assigning channel numbers to the TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] signals from scheduling cycle 1 to scheduling cycle 8.

[0049] like Figure 9As shown, the TDMII interface supports a total of 6 homogeneous network port channel modes. The specific channel scheduling methods under various homogeneous network port channel modes are explained as follows: (1) For 8×10G-R1, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned the values ​​{0, 4, 2, 6, 1, 5, 3, 7} respectively from the 1st to the 8th scheduling cycle, which means that 1 / 8 of the clock cycle is allocated to each network port with channel mode 25G-R1. (2) For 8×25G-R1, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned the values ​​{0, 4, 2, 6, 1, 5, 3, 7} respectively from the 1st to the 8th scheduling cycle, which means that 1 / 8 of the clock cycle is allocated to each network port with channel mode 25G-R1. (3) 2×40G-R4, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned the values ​​{0, 4, 0, 4, 0, 4, 0, 4} respectively from the 1st to the 8th scheduling period, that is, each network port with channel mode 40G-R4 is allocated 4 / 8 of the clock cycle. (4) 4×50G-R2, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned the values ​​{0, 4, 2, 6, 0, 4, 2, 6} respectively from the 1st to the 8th scheduling period, that is, each network port with channel mode 50G-R2 is allocated 2 / 8 of the clock cycle. (5) 2×100G-R4, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned the values ​​{0, 4, 0, 4, 0, 4, 0, 4} respectively from the 1st to the 8th scheduling period, that is, each network port with channel mode 100G-R4 is allocated 4 / 8 of the clock cycle. (6) 1×200G-R8, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned the values ​​{0, 0, 0, 0, 0, 0, 0, 0} respectively from the 1st to the 8th scheduling period, that is, each network port with channel mode 200G-R8 is allocated all 8 / 8 of the clock cycle.

[0050] The TDMII interface can flexibly support a variety of heterogeneous network port channel modes. In the above examples of heterogeneous channel modes, the specific channel scheduling method is explained as follows: (1) 1×100G-R4+2×50G-R2, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned the values ​​{0, 4, 0, 6, 0, 4, 0, 6} in the first to the eighth scheduling cycles, respectively. That is, 4 / 8 of the clock cycle is allocated to a single network port with channel mode 100G-R4, and 2 / 8 of the clock cycle is allocated to each network port with channel mode 50G-R2. (2) 4×25G-R1+1×40G-R4, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned the values ​​{0, 4, 2, 4, 1, 4, 3, 4} in the first to eighth scheduling cycles, respectively. That is, 1 / 8 of the clock cycle is allocated to each network port with channel mode 25G-R1, and 4 / 8 of the clock cycle is allocated to a single network port with channel mode 40G-R4. (3) 1×50G-R2+2×25G-R1+1×100G-R4, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned the values ​​{0, 4, 2, 4, 0, 4, 3, 4} in the first to eighth scheduling cycles, respectively. That is, 2 / 8 of the clock cycle is allocated to a single network port with a channel mode of 50G-R2, 1 / 8 of the clock cycle is allocated to a single network port with a channel mode of 25G-R1, and 4 / 8 of the clock cycle is allocated to a single network port with a channel mode of 100G-R4. (4) 2×10G-R1+1×50G-R2+2×25G-R1+1×50G-R2, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned the values ​​{0, 4, 2, 6, 1, 4, 3, 6} in the first to eighth scheduling cycles, respectively. That is, 1 / 8 of the clock cycle is allocated to each network port with channel mode 10G-R1, 2 / 8 of the clock cycle is allocated to a single network port with channel mode 50G-R2, 1 / 8 of the clock cycle is allocated to each network port with channel mode 25G-R1, and 2 / 8 of the clock cycle is allocated to a single network port with channel mode 50G-R2.

[0051] 4) Effective bit width of TDMII interface

[0052] The valid signals TDMII_TXVALID[2:0] for transmitting data and control control control the effective bit width of the data signals (TDMII_TXDATA[255:0]) and control signals (TDMII_TXCTRL[31:0]) in the transmit direction. The valid signals TDMII_RXVALID[2:0] for receiving data and control control control control the effective bit width of the data signals (TDMII_RXDATA[255:0]) and control signals (TDMII_RXCTRL[31:0]) in the receive direction. The effective bit width of the transmit and receive directions of the TDMII interface is controlled using time-division multiplexing. In the data and control transmission direction, the value of TDMII_TXCHANSLOT[2:0] in each clock cycle determines the corresponding transmit channel number for that clock cycle. Based on the transmit channel number and the channel mode configuration signal CFG_TDMII[23:0] in that clock cycle, the transmit channel mode of the network port in that clock cycle is determined. In the data and control receiving direction, the assignment of TDMII_RXCHANSLOT[2:0] in each clock cycle determines the corresponding receiving channel number in this clock cycle. Based on the receiving channel number and channel mode configuration signal CFG_TDMII[23:0] in this clock cycle, the receiving channel mode of the network port in this clock cycle is determined.

[0053] The transmit channel mode of this clock cycle determines the specific value range of TDMII_TXVALID[2:0] for this clock cycle. The specific value ranges for various channel modes are explained as follows: (1) If the transmit channel mode is 10G-R1, the value range of TDMII_TXVALID[2:0] is {3'b000, 3'b001}. (2) If the transmit channel mode is 25G-R1, the value range of TDMII_TXVALID[2:0] is {3'b000, 3'b001}. (3) If the transmit channel mode is 40G-R4, the value range of TDMII_TXVALID[2:0] is {3'b000, 3'b001}. (4) If the transmit channel mode is 50G-R2, the value range of TDMII_TXVALID[2:0] is {3'b000, 3'b001}. (5) If the transmit channel mode is 100G-R4, the value range of TDMII_TXVALID[2:0] is {3'b000, 3'b010}. (6) If the transmit channel mode is 200G-R8, the value range of TDMII_TXVALID[2:0] is {3'b000, 3'b100}. In each transmit channel mode, whether the specific value of TDMII_TXVALID[2:0] is 3'b000 depends on the value of the transmit enable signal TDMII_TXENABLE k clock cycles ago. If TDMII_TXENABLE=1 k clock cycles ago, then TDMII_TXVALID[2:0] takes a value other than 3'b000 in this clock cycle. Otherwise, if TDMII_TXENABLE=0 k clock cycles ago, then TDMII_TXVALID[2:0] takes a value of 3'b000 in this clock cycle.

[0054] The receive channel mode of this clock cycle determines the specific value range of TDMII_RXVALID[2:0] for this clock cycle. The specific value ranges for various channel modes are explained as follows: (1) If the receive channel mode is 10G-R1, the value range of TDMII_RXVALID[2:0] is {3'b000, 3'b001}. (2) If the receive channel mode is 25G-R1, the value range of TDMII_RXVALID[2:0] is {3'b000, 3'b001}. (3) If the receive channel mode is 40G-R4, the value range of TDMII_RXVALID[2:0] is {3'b000, 3'b001}. (4) If the receive channel mode is 50G-R2, the value range of TDMII_RXVALID[2:0] is {3'b000, 3'b001}. (5) If the receive channel mode is 100G-R4, the value range of TDMII_RXVALID[2:0] is {3'b000, 3'b010}. (6) If the receive channel mode is 200G-R8, the value range of TDMII_RXVALID[2:0] is {3'b000, 3'b100}. In each receive channel mode, whether TDMII_RXVALID[2:0] is 3'b000 or not depends on whether the corresponding receive channel of UPCS transmits data to UMAC in this clock cycle. If there is data to be transmitted, TDMII_RXVALID[2:0] takes a value other than 3'b000 in this clock cycle. Otherwise, if there is no data to be transmitted, TDMII_RXVALID[2:0] takes the value 3'b000 within the current clock cycle.

[0055] As a further extension of the Time Division Multiplexing Medium Independent Interface (TDMII) supporting multi-rate multi-channel communication in this embodiment: In order to be suitable for multi-rate multi-channel Ethernet with a wider rate range and more channel modes, it can be extended by appropriately increasing the data width of each signal of the TDMII interface of the present invention. For example, in order to support 400G, 200G, 100G, 50G, 40G, 10G multi-channel, with a single SERDES channel configurable to 53.125Gbps, 25.78125Gbps and 10.3125Gbps multi-rate, and a maximum support of 8 channels Ethernet interface, the above TDMII interface signals can be extended as follows: (1) The transmit data signal TDMII_TXDATA is extended from 256 bits to 512 bits. (2) The transmit control signal TDMII_TXCTRL is extended from 32 bits to 64 bits. (3) The valid signal TDMII_TXVALID for transmit data and control is extended from 3 bits to 4 bits. The valid value range of TDMII_TXVALID is extended to {4'b1000, 4'b0100, 4'b0010, 4'b0001, 4'b0000}. When TDMII_TXVALID[3:0]=4'b1000, it means that TDMII_TXDATA[511:0] and TDMII_TXCTRL[63:0] are valid in the current clock cycle; when TDMII_TXVALID[3:0]=4'b0100, it means that TDMII_TXDATA[255:0] and TDMII_TXCTRL[31:0] are valid in the current clock cycle, and the other bit fields are invalid; when TDMII_TXVALID[3:0]=4'b0010, it means that TDMII_TXDATA[127:0] and TDMII_TXCTRL[15:0] are valid in the current clock cycle, and the other bit fields are invalid. When TDMII_TXVALID[3:0]=4'b0001, it means that TDMII_TXDATA[63:0] and TDMII_TXCTRL[7:0] are valid in the current clock cycle, and the other bit fields are invalid. When TDMII_TXVALID[2:0]=4'b0000, it means that TDMII_TXDATA[511:0] and TDMII_TXCTRL[63:0] are invalid in the current clock cycle. (4) Extend the received data signal TDMII_RXDATA from 256 bits to 512 bits. (5) Extend the received control signal TDMII_RXCTRL from 32 bits to 64 bits. (6) Extend the valid signal TDMII_RXVALID for received data and control from 3 bits to 4 bits. The valid value range of TDMII_RXVALID is extended to {4'b1000, 4'b0100, 4'b0010, 4'b0001, 4'b0000}.When TDMII_RXVALID[3:0]=4'b1000, it means that TDMII_RXDATA[511:0] and TDMII_RXCTRL[63:0] are valid in the current clock cycle; when TDMII_RXVALID[3:0]=4'b0100, it means that TDMII_RXDATA[255:0] and TDMII_RXCTRL[31:0] are valid in the current clock cycle, and the other bit fields are invalid; when TDMII_RXVALID[3:0]=4'b0010, it means that TDMII_RXDATA[127:0] and TDMII_RXCTRL[15:0] are valid in the current clock cycle, and the other bit fields are invalid. When TDMII_RXVALID[3:0]=4'b0001, it means that TDMII_RXDATA[63:0] and TDMII_RXCTRL[7:0] are valid in the current clock cycle, and the other bit fields are invalid. When TDMII_RXVALID[3:0]=4'b0000, it means that TDMII_RXDATA[511:0] and TDMII_RXCTRL[63:0] are invalid in the current clock cycle. (7) The TDMII interface channel mode configuration signal CFG_TDMII is extended from 24 bits to 32 bits.The correspondence between the channel mode configuration signal CFG_TDMII[i*4+3 : i*4] and the mode of the i-th channel is extended as follows: When CFG_TDMII[i*4+3 : i*4] = 4'b0001, it indicates that the mode of the i-th channel is 10G-R1, and the value of i is in the range of {0, 1, 2, 3, 4, 5, 6, 7}; when CFG_TDMII[i*4+3 : i*4] = 4'b0010, it indicates that the mode of the i-th channel is 25G-R1, and the value of i is in the range of {0, 1, 2, 3, 4, 5, 6, 7}; when CFG_TDMII[i*4+3 : i*4] = 4'b0011, it indicates that the mode of the i-th channel is 40G-R4, and the value of i is in the range of {0, 4 ... When CFG_TDMII[i*4+3 : i*4]=4'b0100, it indicates that the i-th channel mode is 50G-R2, and the value of i is {0, 2, 4, 6}; when CFG_TDMII[i*4+3 : i*4]=4'b0101, it indicates that the i-th channel mode is 50G-R1, and the value of i is {0, 1, 2, 3, 4, 5, 6, 7}; when CFG_TDMII[i*4+3 : i*4]=4'b0110, it indicates that the i-th channel mode is 100G-R4, and the value of i is {0, 4}; when CFG_TDMII[i*4+3 : i*4]=4'b0111, it indicates that the i-th channel mode is 100G-R2, and the value of i is {0, 2, 4, 6 ... When CFG_TDMII[i*4+3 : i*4]=4'b1000, it means that the i-th channel mode is 200G-R8, and the value of i is {0}; when CFG_TDMII[i*4+3 : i*4]=4'b1001, it means that the i-th channel mode is 200G-R4, and the value of i is {0, 4}; when CFG_TDMII[i*4+3 : i*4]=4'b1010, it means that the i-th channel mode is 400G-R8, and the value of i is {0}. In the above description of channel mode configuration, the specific meanings of the four extended channel modes are as follows: 50G-R1 indicates that the network port has a single SERDES channel at the bottom layer, and its SERDES channel rate is configured to 53.125Gbps; 100G-R2 indicates that the network port is bound to two SERDES channels at the bottom layer, and the rate of each SERDES channel is configured to 53.125Gbps; 200G-R4 indicates that the network port is bound to four SERDES channels at the bottom layer, and the rate of each SERDES channel is configured to 53.125Gbps; 400G-R8 indicates that the network port is bound to four SERDES channels at the bottom layer, and the rate of each SERDES channel is configured to 53.125Gbps.

[0056] 5) TDMII interface timing

[0057] In this embodiment, the TDMII interface is a channelized interface using time-division multiplexing technology, and the interface logic operates on the TDMII_CLK clock. To ensure that each SERDES channel supports a maximum data transmission speed of 25.78125Gbps, the minimum operating frequency of TDMII_CLK is (25.78125*64 / 66) / (256 / 8)=0.78125GHz.

[0058] In the data transmission direction from UMAC to UPCS, the timing of the TDMII interface is mainly controlled by UMAC, but it must comply with the TDMII interface channel scheduling rules, as described in the previous "TDMII Interface Channel Scheduling". Figure 10(a) in the figure gives an example of the timing of the TDMII interface in the data transmission direction. The digital signal driven by the TDMII interface clock TDMII_CLK lasts for 13 complete clock cycles. The TDMII interface transmit channel time slot signal TDMII_TXCHANSLOT[2:0] indicates the scheduling of the TDMII interface channels by the UMAC, and the channel scheduling period shown is {0, 4, 2, 6, 1, 5, 3, 7}. The TDMII interface transmit enable signal TDMII_TXENABLE indicates the ability of each UPCS channel to receive data characters and control characters transmitted by the UMAC. Its value is 1 in the 1st, 3rd, 6th, 8th, and 12th clock cycles, indicating that data characters and control characters transmitted by the UMCA can be received in the 2nd, 4th, 7th, 9th, and 13th clock cycles (i.e., parameter k=1). The TDMII interface transmits direction data control signals (TDMII_TXDATA [255:0] and TDMII_TXCTRL [31:0]) and its valid signal TDMII_TXVALID [2:0], which are sent by the UMAC to the UPCS in the 2nd, 4th, 7th, 9th, and 13th clock cycles. The data of TDMII_TXDATA [255:0] in the above 5 clock cycles are TD[0], TD[1], TD[2], TD[3], and TD[4], respectively. The data of TDMII_TXCTRL [31:0] in the above 5 clock cycles are TC[0], TC[1], TC[2], TC[3], and TC[4], respectively. The value of TDMII_TXVALD [2:0] is 1 in the above 5 clock cycles and 0 in the remaining clock cycles. Therefore, the data characters sent by UMAC to UPCS through the TDMII interface are TD[0][63:0], TD[1][63:0], TD[2][63:0], TD[3][63:0], and TD[4][63:0], and the control characters sent are TC[0][7:0], TC[1][7:0], TC[2][7:0], TC[3][7:0], and TC[4][7:0], and the channel numbers are 4, 6, 3, 0, and 1, respectively.

[0059] In the data reception direction from UPCS to UMAC, the timing of the TDMII interface is mainly controlled by UPCS, but it must comply with the TDMII interface channel scheduling rules, as described in the previous "TDMII Interface Channel Scheduling". Figure 10Example (b) of the TDMII interface timing in the data reception direction is given. The digital signal driven by the TDMII interface clock TDMII_CLK lasts for 13 complete clock cycles. The TDMII interface receive channel time slot signal TDMII_RXCHANSLOT[2:0] indicates the UPCS scheduling of the TDMII interface channels, with the channel scheduling cycle shown as {0, 4, 2, 4, 1, 4, 3, 4}. The 1st and 9th clock cycles belong to receive channel 0, the 2nd, 4th, 6th, 8th, 10th, and 12th clock cycles belong to receive channel 4, the 3rd and 11th clock cycles belong to receive channel 2, the 5th and 13th clock cycles belong to receive channel 1, and the 7th and 9th clock cycles belong to receive channel 3. The TDMII interface receive direction data control signals (TDMII_RXDATA[255:0] and TDMII_RXCTRL[31:0]) and its valid signal TDMII_RXVALID[2:0] are sent by UPCS to UMAC in the 11 clock cycles other than the 7th and 10th clock cycles. The data for TDMII_RXDATA [255:0] in the above 11 clock cycles are RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7], RD[8], RD[9], and RD

[10] . The data for TDMII_RXCTRL [31:0] in the above 11 clock cycles are RC[0], RC[1], RC[2], RC[3], RC[4], RC[5], RC[6], RC[7], RC[8], RC[9], and RC

[10] . The values ​​for TDMII_RXVALD [2:0] are all 1 or 2 in the above 11 clock cycles and are all 0 in the remaining clock cycles.Therefore, the data characters received by UMAC from each channel of UPCS through the TDMII interface are as follows: Channel 0 receives {RD[0][63:0], RD[7][63:0]}, Channel 4 receives {RD[1][127:0], RD[3][127:0], RD[5][127:0], RD[6][127:0], RD[9][127:0]}, Channel 2 receives {RD[2][63:0], RD[8][63:0]}, and Channel 1 receives {RD[4][63:0], RD

[10] [63:0]}.}, Channel 3 did not receive any valid data characters; the control characters received by each channel are as follows: Channel 0 received {RC[0][7:0], RC[7][7:0]}, Channel 4 received {RC[1][15:0], RC[3][15:0], RC[5][15:0], RC[6][15:0], RC[9][15:0]}, Channel 2 received {RC[2][7:0], RC[8][7:0]}, Channel 1 received {RC[4][7:0], RC

[10] [7:0]}, and Channel 3 did not receive any valid control characters.

[0060] 6) TDMII Interface Application

[0061] There are two typical application scenarios for the TDMII interface. The first is to build an interface adapter that conforms to the TDMII interface timing rules to connect PCS and MAC of various rates in existing technologies. Figure 11 (a) in the diagram provides an example of the first application scenario. In this scenario, interface adapter 0 converts one 200G MAC CDMII interface, two 100G MAC CGMII interfaces, four 50G MAC LGMII interfaces, two 40G MAC XLGMII interfaces, eight 25G MAC MII interfaces XXVGMII, and eight 10G MAC XGMII interfaces into TDMII interfaces. Interface adapter 1 converts one 200G PCS CDMII interface, two 100G PCS CGMII interfaces, four 50G PCS LGMII interfaces, two 40G PCS XLGMII interfaces, eight 25G PCS MII interfaces XXVGMII, and eight 10G PCS XGMII interfaces into TDMII interfaces. The TDMII interfaces of interface adapter 0 and interface adapter 1 are then connected together. The second scenario involves constructing multi-rate, multi-channel UMAC and UPCS interfaces so that their connection interfaces follow the TDMII interface timing. Figure 11(b) provides an example of the second application scenario. The multi-rate, multi-channel UMAC and UPCS employ a channelized design, supporting a maximum of 8 channels. Supported network port rates include 200G, 100G, 50G, 40G, 25G, and 10G. The number of SERDES channels that can be bound to a single channel supports ×8, ×4, ×2, and ×1. The channelized multi-rate, multi-channel UMAC and UPCS design using TDMII interface technology is beneficial for improving logical resource utilization and reducing logical resource requirements.

[0062] As a further improvement to the method of using the time-division multiplexing medium-independent interface that supports multi-rate multi-channel communication according to the present invention: as mentioned above, in order to be applicable to multi-rate multi-channel Ethernet with a wider rate range and more channel modes, it can be extended by appropriately increasing the data width of each signal of the TDMII interface of the present invention. For example, for an extended TDMII interface that supports 400G, 200G, 100G, 50G, 40G, and 10G multi-channels, with a single SERDES channel configurable to multiple rates of 53.125Gbps, 25.78125Gbps, and 10.3125Gbps, and can be divided into a maximum of 8 channels for Ethernet interface connections, in the first application scenario, interface adapter 0 and interface adapter 1 need to support converting more MII interfaces (requiring the addition of MII interfaces corresponding to 50G-R1, 100G-R2, 200G-R4, and 400G-R8 modes) into extended TDMII interfaces; in the second application scenario, UMAC and UPCS need to support 400G network port channel mode with 8 SERDES channels, 200G network port channel mode with 4 SERDES channels, 100G network port channel mode with 2 SERDES channels, and 50G network port channel mode with a single SERDES channel.

[0063] In summary, the time-division multiplexing media-independent interface of this embodiment includes a media access control layer module and a physical coding sublayer module supporting multi-rate, multi-channel communication. The media access control layer module and the physical coding sublayer module share the same clock signal and channel mode configuration signal. The signals output from the media access control layer module to the physical coding sublayer module include a transmit channel time slot signal, a transmit data signal, a transmit control signal, and a valid signal for transmitting data and control. The signals output from the physical coding sublayer module to the media access control layer module include a transmit enable signal, a receive channel time slot signal, a receive data signal, a receive control signal, and a valid signal for receiving data and control. This time-division multiplexing media-independent interface solves the problem of numerous interface types and signals in existing media-independent interface technologies, achieving compatibility with multi-rate, multi-channel Ethernet over a wide range of rates. Compared to existing media-independent interface (MII) technologies, this embodiment can achieve communication between multi-rate, multi-channel PCS and multi-rate, multi-channel MAC in a channelized time-division multiplexing manner, thereby simplifying the connection signals between the multi-rate, multi-channel PCS and multi-rate, multi-channel MAC and solving the problem of numerous interface types and signals in existing media-independent interface (MII) technologies. The method described in this embodiment is beneficial for the integration of multi-rate multi-channel MAC and multi-rate multi-channel PCS in the front-end design of network communication chips, and also beneficial for the layout and routing of multi-rate multi-channel MAC and multi-rate multi-channel PCS in the back-end design of network communication chips.

[0064] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication, characterized in that, The system includes a Media Access Control (UMAC) module supporting multi-rate, multi-channel communication and a Physical Coding Sublayer (UPCS) module. The UMAC and UPCS share the same clock signal TDMII_CLK and channel mode configuration signal CFG_TDMII[23:0]. The signals output from the UMAC to the UPCS include a transmit channel time slot signal TDMII_TXCHANSLOT[2:0], a transmit data signal TDMII_TXDATA, a transmit control signal TDMII_TXCTRL, and a transmit data and control validity signal TDMII_TXVALID[2:0]. The signals output from the UPCS to the UMAC include a transmit enable signal TDMII_TXENABLE, a receive channel time slot signal TDMII_RXCHANSLOT[2:0], a receive data signal TDMII_RXDATA, a receive control signal TDMII_RXCTRL, and a receive data and control validity signal TDMII_RXVALID[2:0]. The channel mode configuration signal CFG_TDMII[23:0] supports a maximum of 8 channels, numbered 0, 1, 2, 3, 4, 5, 6, and 7. The mode of the i-th channel is controlled by the bit field CFG_TDMII[i*3+2 : i*3] of the channel mode configuration signal CFG_TDMII, including: when the bit field CFG_TDMII[i*3+2 : i*3] = 3'b001, it indicates that the i-th channel mode is 10G-R1, and the value of i ranges from {0, 1, 2, 3, 4, 5, 6, 7}; when the bit field CFG_TDMII[i*3+2 : i*3] = 3'b010, it indicates that the i-th channel mode is 25 ... When the bit field CFG_TDMII[i*3+2 : i*3]=3'b011, it indicates that the i-th channel mode is 40G-R4, and the value of i is {0, 4}; when the bit field CFG_TDMII[i*3+2 : i*3]=3'b100, it indicates that the i-th channel mode is 50G-R2, and the value of i is {0, 2, 4, 6}; when the bit field CFG_TDMII[i*3+2 : i*3]=3'b101, it indicates that the i-th channel mode is 100G-R4, and the value of i is {0, 4}; when the bit field CFG_TDMII[i*3+2 : i*3]=3'b01 ...40G-R4, and the value of i is {0, 4}; when the bit field CFG_TDMII[i*3+2 : i*3]=3'b011, it indicates that the i-th channel mode is 40G-R4, and the value of i is {0, 4}; when the bit field CFG_TDMII[i*3+2 : i*3]=3'b011, it indicates that the i-th channel mode is 50G-R2, and the value of i is {0, 2, 4, 6}. [i*3]=3'b110 indicates that the i-th channel mode is 200G-R8, and the value of i is in the range of {0}. Here, 10G-R1 indicates that the network port has a single SERDES channel at the underlying layer, and its SERDES channel rate is configured to 10.3125Gbps; 25G-R1 indicates that the network port has a single SERDES channel at the underlying layer, and its SERDES channel rate is configured to 25.78125Gbps; 40G-R4 indicates that the network port is bound to 4 SERDES channels at the underlying layer, and the rate of each SERDES channel is... The configuration is 10.3125Gbps; 50G-R2 indicates that the network port is bound to 2 SERDES channels at the underlying level, and the rate of each SERDES channel is configured to 25.78125Gbps; 100G-R4 indicates that the network port is bound to 4 SERDES channels at the underlying level, and the rate of each SERDES channel is configured to 25.78125Gbps; 200G-R8 indicates that the network port is bound to 8 SERDES channels at the underlying level, and the rate of each SERDES channel is configured to 25.78125Gbps. The effective signal TDMII_TXVALID[2:0] for transmitting data and control is used to control the effective bit width of the transmitting data signal TDMII_TXDATA and the transmitting control signal TDMII_TXCTRL. The effective bit width of the receiving direction of the time-division multiplexed medium-independent interface is controlled in a time-division multiplexing manner. The value of the effective signal TDMII_TXVALID[2:0] for transmitting data and control in each clock cycle determines the corresponding transmitting channel number in this clock cycle. The transmitting channel number and the channel mode configuration signal CFG_TDMII[23:0] in this clock cycle determine the transmitting channel mode of the network port in this clock cycle. The transmitting channel mode in this clock cycle determines the specific value range of the effective signal TDMII_TXVALID[2:0] for transmitting data and control in this clock cycle. The effective signal TDMII_RXVALID[2:0] for receiving data and control is used to control the effective bit width of the receiving data signal TDMII_RXDATA and the receiving control signal TDMII_RXCTRL. The effective bit width of the receiving direction of the time-division multiplexed medium-independent interface is controlled in a time-division multiplexing manner. The value of the effective signal TDMII_RXVALID[2:0] for receiving data and control in each clock cycle determines the corresponding receiving channel number in this clock cycle. The receiving channel mode of the network port in this clock cycle is determined according to the receiving channel number and the channel mode configuration signal CFG_TDMII[23:0] in this clock cycle. The receiving channel mode in this clock cycle determines the specific value range of the effective signal TDMII_RXVALID[2:0] for receiving data and control in this clock cycle.

2. The time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication according to claim 1, characterized in that, The transmit channel mode of this clock cycle determines the specific value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control in this clock cycle, including: (1) If the channel mode is 10G-R1, the value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}; (2) If the channel mode is 25G-R1, the value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}; (3) If the channel mode is 40G-R4, the value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}; (4) If the channel mode is 50G-R2, the value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}. (5) If the channel mode is 100G-R4, the range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}; (6) If the channel mode is 200G-R8, the range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}. In each transmission channel mode, whether the valid signal TDMII_TXVALID[2:0] for transmitting data and control is 3'b000 depends on the value of the transmit enable signal TDMII_TXENABLE k clock cycles ago. If the transmit enable signal TDMII_TXENABLE = 1 k clock cycles ago, then the valid signal TDMII_TXVALID[2:0] for transmitting data and control takes a value other than 3'b000 in this clock cycle; otherwise, if the transmit enable signal TDMII_TXENABLE = 0 k clock cycles ago, then the valid signal TDMII_TXVALID[2:0] for transmitting data and control takes a value of 3'b000 in this clock cycle.

3. The time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication according to claim 2, characterized in that, The specific value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control in this clock cycle is determined by the receiving channel mode of this clock cycle, including: (1) If the channel mode is 10G-R1, the value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control is {3'b001}; (2) If the channel mode is 25G-R1, the value range of the valid signal TDMII_RXVALID for receiving data and control is {3'b001}; The value range of [2:0] is {3'b001}; (3) If the channel mode is 40G-R4, the value range of TDMII_TXVALID[2:0] and TDMII_RXVALID[2:0] is {3'b001}; (4) If the channel mode is 50G-R2, the value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control is {3'b001}; (5) If the channel mode is 100G-R 4. The range of the effective signal TDMII_RXVALID[2:0] for receiving data and control is {3'b010}; (6) If the channel mode is 200G-R8, the range of the effective signal TDMII_RXVALID[2:0] for receiving data and control is {3'b100}; In each receiving channel mode, whether the specific value of the effective signal TDMII_RXVALID[2:0] for receiving data and control is 3'b000 depends on whether the receiving channel corresponding to the physical coding sub-layer module UPCS transmits data to the medium access control layer module UMAC in this clock cycle; if there is data to be transmitted, the effective signal TDMII_RXVALID[2:0] for receiving data and control takes a value other than 3'b000 in this clock cycle; otherwise, if there is no data to be transmitted, the effective signal TDMII_RXVALID[2:0] for receiving data and control takes a value of 3'b000 in this clock cycle.

4. An application method for a time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication as described in any one of claims 1 to 3, characterized in that, This includes using multiple time-division multiplexing media-independent interfaces supporting multi-rate multi-channel communication to form one of the following six homogeneous network port channel modes: (1) 8×10G-R1, which means that the time-division multiplexing media-independent interface is sequentially split into 8 network ports with a channel mode of 10G-R1, and the assigned channel numbers are {0, 1, 2, 3, 4, 5, 6, 7}, and the value of its channel mode configuration signal CFG_TDMII is {8{3'b001}}; (2) 8×25G-R1, which means that the time-division multiplexing media-independent interface is sequentially split into 8 network ports with a channel mode of 25G-R1, and the assigned channel numbers are {0, 1, 2, 3, 4, 5, 6, 7}, and the channel mode is {8{3'b001}}. The configuration signal CFG_TDMII has a value of {8{3'b010}}; (3) 2×40G-R4, which means that the time-division multiplexing medium-independent interface is sequentially split into two network ports with channel mode 40G-R4, and the allocated channels are numbered {0, 4} respectively. The channel mode configuration signal CFG_TDMII has a value of {2{{3'b011}, 3{3'bzzz}}}; (4) 4×50G-R2, which means that the time-division multiplexing medium-independent interface is sequentially split into four network ports with channel mode 50G-R2, and the allocated channels are numbered {0, 2, 4, 6} respectively. The channel mode configuration signal CFG_TDMII has a value of {4{{3'b100}, {3'bzzz}}};(5)2×100G-R4, indicating that the time-division multiplexing medium-independent interface is sequentially split into two network ports with channel mode of 100G-R4, and the assigned channel numbers are {0, 4}, and the channel mode configuration signal CFG_TDMII value is {2{{3'b101},3{3'bzzz}}};(6)1×200G-R8, indicating that the time-division multiplexing medium-independent interface is used as a network port with channel mode of 200G-R8, and the assigned channel number is {0}, and the channel mode configuration signal CFG_TDMII value is {{3'b101},7{3'bzzz}}}, where {3'bzzz} represents a 3-bit signal with each bit taking any value.

5. The application method of the time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication according to claim 4, characterized in that, In the six homogeneous network port channel modes: (1) In the 8×10G-R1 homogeneous network port channel mode, the values ​​of the transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and the receive channel time slot signal TDMII_RXCHANSLOT[2:0] in the first to the eighth scheduling cycles are {0, 4, 2, 6, 1, 5, 3, 7}, and each channel mode allocates 1 / 8 of the clock cycle to the 25G-R1 network port; (2) In the 8×25G-R1 homogeneous network port channel mode, the transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and the receive channel time slot signal TDMII_RXCHANSLOT[2:0] are assigned to the network port of 25G-R1 respectively. The values ​​of II_RXCHANSLOT[2:0] in the first to eighth scheduling cycles are {0, 4, 2, 6, 1, 5, 3, 7}, which means that 1 / 8 of the clock cycle is allocated to each network port with channel mode 25G-R1; (3) In the 2×40G-R4 homogeneous network port channel mode, the values ​​of the transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and the receive channel time slot signal TDMII_RXCHANSLOT[2:0] in the first to eighth scheduling cycles are {0, 4, 0, 4, 0, 4, 0, 4}, which means that 4 / 8 of the clock cycle is allocated to each network port with channel mode 40G-R4. Clock cycle; (4) In the 4×50G-R2 homogeneous network port channel mode, the values ​​of the transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and the receive channel time slot signal TDMII_RXCHANSLOT[2:0] in the 1st to 8th scheduling cycles are {0, 4, 2, 6, 0, 4, 2, 6}, and 2 / 8 of the clock cycle is allocated to each network port with channel mode 50G-R2; (5) In the 2×100G-R4 homogeneous network port channel mode, the transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and the receive channel time slot signal TDMII_RXCHANSLOT[2:0] are assigned to the following values: {0, 4, 2, 6, 0, 4, 2, 6}, respectively, and 2 / 8 of the clock cycle is allocated to each network port with channel mode 50G-R2; The values ​​of SLOT[2:0] in the first to the eighth scheduling cycles are {0, 4, 0, 4, 0, 4, 0, 4}, which allocate 4 / 8 of the clock cycles for each network port with a channel mode of 100G-R4; (6) In the channel mode of 1×200G-R8 homogeneous network port, the values ​​of the transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and the receive channel time slot signal TDMII_RXCHANSLOT[2:0] in the first to the eighth scheduling cycles are {0, 0, 0, 0, 0, 0, 0}, which allocate all 8 / 8 of the clock cycles for a single network port with a channel mode of 200G-R8.

6. An application method for a time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication as described in any one of claims 1 to 3, characterized in that, This includes using multiple time-division multiplexing media-independent interfaces supporting multi-rate multi-channel communication to form one of the following four heterogeneous network port channel modes: (1) 1×100G-R4+2×50G-R2, where the time-division multiplexing media-independent interface is sequentially split into one network port with channel mode 100G-R4 and two network ports with channel mode 50G-R2, with assigned channel numbers {0, 4, 6}, and the channel mode configuration signal value is CFG_TDMII[23:0]={{3'b101},3{3'bzzz},2{{3'b100},{3'bzzz}}}; (2) 4×25G-R1+1×40G-R4, where the time-division multiplexing media-independent interface is sequentially split into four network ports with channel mode 25G- The network port of R1 and one network port with channel mode 40G-R4 are assigned channel numbers {0, 1, 2, 3, 4} respectively, and their channel mode configuration signal value is CFG_TDMII[23:0]={4{3'b010},{3'b011},3{3'bzzz}}; (3) 1×50G-R2+2×25G-R1+1×100G-R4, the time division multiplexing medium-independent interface is sequentially split into one network port with channel mode 50G-R2, two network ports with channel mode 25G-R1 and one network port with channel mode 100G-R4, assigned channel numbers {0, 2, 3, 4} respectively, and their channel mode configuration signal value is CFG_TDMII[23:0] ={{3'b100},{3'bzzz}, 2{3'b010},{3'b101},3{3'bzzz}};(4)2×10G-R1+1×50G-R2+2×25G-R1+1×50G-R2, the time-division multiplexing medium-independent interface is sequentially divided into 2 network ports with channel mode 10G-R1, 1 network port with channel mode 50G-R2, 2 network ports with channel mode 25G-R1 and 1 network port with channel mode 50G-R2, and their assigned channel numbers are {0, 1, 2, 4, 5, 6}, and their channel mode configuration signal value is CFG_TDMII[23:0] ={2{3'b001},{3'b001},{3'bzzz},2{3'b010},{3'b100},{3'bzzz}}, where {3'bzzz} represents a 3-bit signal where each bit can take any value.

7. The application method of the time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication according to claim 6, characterized in that, In the four heterogeneous network port channel modes: (1) In the 1×100G-R4+2×50G-R2 heterogeneous network port channel mode, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned the values ​​{0, 4, 0, 6, 0, 4, 0, 6} respectively from the 1st to the 8th scheduling period, allocating 4 / 8 of the clock cycle for a single network port with channel mode 100G-R4 and 2 / 8 of the clock cycle for each network port with channel mode 50G-R2; (2) In the 4×25G-R1+1×40 In the G-R4 heterogeneous network port channel mode, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned the values ​​{0, 4, 2, 4, 1, 4, 3, 4} respectively from the 1st to the 8th scheduling cycle. 1 / 8 of the clock cycle is allocated to each network port with channel mode 25G-R1, and 4 / 8 of the clock cycle is allocated to a single network port with channel mode 40G-R4; (3) In the 1×50G-R2+2×25G-R1+1×100G-R4 heterogeneous network port channel mode, the channel time slot signal T The values ​​of DMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] in the first to the eighth scheduling cycles are {0, 4, 2, 4, 0, 4, 3, 4}, respectively. 2 / 8 of the clock cycle is allocated to a single network port with a channel mode of 50G-R2, 1 / 8 of the clock cycle is allocated to each network port with a channel mode of 25G-R1, and 4 / 8 of the clock cycle is allocated to a single network port with a channel mode of 100G-R4; (4) 2×10G-R1+1×50G-R2+2×25G-R1+1×50G-R2 heterogeneous network terminals In the channel mode, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned the values ​​{0, 4, 2, 6, 1, 4, 3, 6} in the 1st to 8th scheduling cycles, respectively. 1 / 8 of the clock cycle is allocated to each network port with channel mode 10G-R1, 2 / 8 of the clock cycle is allocated to a single network port with channel mode 50G-R2, 1 / 8 of the clock cycle is allocated to each network port with channel mode 25G-R1, and 2 / 8 of the clock cycle is allocated to a single network port with channel mode 50G-R2.

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