Semiconductor epitaxial wafer and preparation method thereof

Abstract

The invention discloses a semiconductor epitaxial wafer and a preparation method thereof. The semiconductor epitaxial wafer comprises a substrate, a first mask structure layer, a first nitride layer, a second mask structure layer and a second nitride layer. The first mask structure layer is arranged on the substrate and exposes part of the surface of the substrate; the first nitride layer is arranged on the exposed surface of the substrate, and the top surface of the first nitride layer is higher than the top surface of the first mask structure layer; the second mask structure layer is arranged on the first nitride layer; the second nitride layer covers the second mask structure layer, the second mask structure layer covers dislocation of the second nitride layer, and the second nitride layer covers at least part of the top surface of the first mask structure layer and the outer surface of the first nitride layer. By arranging the first mask structure layer and the second mask structure layer, the growth quality of the second nitride layer is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor epitaxial technology, and in particular to a semiconductor epitaxial wafer and a method for preparing the same. Background Art

[0002] III-V nitride semiconductor materials and their related alloys and heterojunctions occupy an important position in the application of optoelectronics and microelectronic devices due to their superior performance. Since III-V nitrides are generally heteroepitaxially grown on heterogeneous substrates such as sapphire or SiC, the lattice constants and thermal mismatch between different materials will produce dislocations or defects, which will extend upward with the growth of the epitaxial layer. These dislocations will appear as non-radiative recombination centers when the device is working, affecting the efficiency of the device. At the same time, they will act as leakage channels, causing the leakage current to increase and causing the device to age rapidly, affecting the working efficiency and life of the device, and restricting its application in the field of semiconductor electronics. Summary of the invention

[0003] The present application provides a semiconductor epitaxial wafer and a method for preparing the same, the purpose of which is to solve the problem of high dislocation defects in the existing semiconductor epitaxial layer epitaxial growth process.

[0004] This application is implemented using the following technical solutions:

[0005] A semiconductor epitaxial wafer, comprising:

[0006] substrate;

[0007] A first mask structure layer, wherein the first mask structure layer is disposed on the substrate and exposes a portion of a surface of the substrate;

[0008] a first nitride layer, wherein the first nitride layer is disposed on the exposed surface of the substrate, and a top surface of the first nitride layer is higher than a top surface of the first mask structure layer;

[0009] a second mask structure layer, wherein the second mask structure layer is located on the first nitride layer;

[0010] A second nitride layer, wherein the second nitride layer covers the second mask structure layer, the second mask structure layer masks dislocations for the second nitride layer, and the second nitride layer covers at least a portion of the top surface of the first mask structure layer and an outer surface of the first nitride layer.

[0011] In some specific embodiments, the semiconductor epitaxial wafer further includes: a nitride seed layer, wherein the nitride seed layer is disposed on the first nitride layer and is used to provide nucleation centers for the second mask structure layer.

[0012] In some specific embodiments, the dislocation density of the nitride seed layer is greater than that of the first nitride layer, and the dislocation density of the nitride seed layer is 1×10 8 ~1×10 12 cm -2 ;

[0013] Preferably, the thickness of the nitride seed layer is 2-20 nm, and the nitride seed layer is an n-type doped nitride layer with a doping concentration of 2×10 19 cm -3 ~2×10 20 cm -3 .

[0014] In some specific embodiments, a gap is formed between the second nitride layer and a portion of the top surface of the first mask structure layer; and a lateral size of the gap is 5 to 15 nm.

[0015] In some specific embodiments, the first mask structure layer is a first SiN layer with a thickness of 2 to 200 nm; and / or,

[0016] The first nitride layer is a first GaN layer with a thickness of 10 to 500 nm; and / or,

[0017] The second mask structure layer is a second SiN layer with a thickness of 2 to 200 nm; and / or,

[0018] The second nitride layer is a second GaN layer with a thickness of 1000-5000 nm; and / or

[0019] It also includes: an n-type nitride layer, the n-type nitride layer is disposed on the second nitride layer and has a thickness of 1000 to 8000 nm;

[0020] A nitride light-emitting layer, which is disposed on the n-type nitride layer and has a thickness of 5 to 300 nm;

[0021] A p-type nitride layer is disposed on the nitride light-emitting layer and has a thickness of 50 to 200 nm.

[0022] A method for preparing a semiconductor epitaxial wafer comprises the following steps:

[0023] providing a substrate;

[0024] Growing a first mask structure layer on the substrate and exposing a portion of the surface of the substrate;

[0025] Under the conditions of a first temperature, a first pressure, and a first V / III ratio, growing a first nitride layer on the exposed surface of the substrate, wherein a top surface of the first nitride layer is higher than a top surface of the first mask structure layer;

[0026] growing a second mask structure layer on the top surface of the first nitride layer;

[0027] Under the conditions of a second temperature, a second pressure, and a second V / III ratio, a second nitride layer is grown on the second mask structure layer, wherein the second nitride layer covers at least a portion of the top surface of the first mask structure layer, an outer surface of the first nitride layer, and an outer surface of the second mask structure layer.

[0028] In some embodiments, the first pressure is greater than the second pressure, and the first V / III ratio is lower than the second V / III ratio;

[0029] Preferably, the first pressure is 400-600 torr, the second pressure is 100-400 torr, the first V / III ratio is less than 1000, and the second V / III ratio is 2000-8000;

[0030] Wherein, under the process of high pressure and low V / III ratio, a portion of the first nitride layer protruding from the first mask structure layer forms a sidewall;

[0031] Forming the first nitride layer further comprises: under the condition of reducing gas, partially decomposing the sidewall to form a flat top surface of the first nitride layer; more preferably, the molar flow ratio of group V / reducing carrier gas is 1:5 to 1:100.

[0032] In some specific embodiments, the preparation method further comprises:

[0033] Under the third temperature and high doping process, a nitride seed layer is grown on the top surface of the first nitride layer, and the nitride seed layer is used to provide a nucleation center for the second mask structure layer; the dislocation density of the nitride seed layer is 1×10 8 ~1×10 12 cm -2 ;

[0034] The thickness of the nitride seed layer is 2-20 nm, and the nitride seed layer is an n-type doped nitride layer with a doping concentration of 2×10 19 cm -3 ~2×10 20 cm -3 .

[0035] In some specific embodiments, under the conditions of a second temperature, a second pressure, and a second V / III ratio, the 0001 plane growth rate of the second nitride layer is higher than that of the side surface of the second nitride layer, and under the limiting effect of the second mask structure layer, pores are formed between the second nitride layer and a portion of the top surface of the first mask structure layer; wherein the lateral size of the pores is 5 to 15 nm.

[0036] In some specific embodiments, the first mask structure layer is a SiN layer grown in situ by MOCVD, and the growth conditions are a temperature of 900-1200° C. and a pressure of 50-650 torr; and / or,

[0037] The growth condition of the first nitride layer is that the first temperature is 900-1200° C.; and / or,

[0038] The growth conditions of the nitride seed layer are a temperature of 700-1000° C. and a pressure of 50-650 torr; and / or,

[0039] The growth conditions of the second mask structure layer are a temperature of 900-1200° C. and a pressure of 50-650 torr; and / or,

[0040] The growth condition of the second nitride layer is that the second temperature is 900-1200° C.; and / or,

[0041] The method further includes sequentially growing an n-type nitride layer, a nitride light emitting layer and a p-type nitride layer on the second nitride layer;

[0042] The growth conditions of the n-type nitride layer are a temperature of 950-1250° C. and a pressure of 50-650 torr;

[0043] The growth conditions of the nitride light-emitting layer are a temperature of 700-1000° C. and a pressure of 100-500 torr;

[0044] The growth conditions of the p-type nitride layer are a temperature of 950-1150° C. and a pressure of 100-600 torr. Compared with the prior art, the beneficial effects of the present application include at least:

[0045] On the one hand, the epitaxial wafer of the present application controls the process of the first nitride layer on the first mask structure layer, so that the dislocations in the growth process of the first nitride layer are turned, and a growth template is provided for the second nitride layer; on the other hand, the second mask structure layer shields the extension of dislocations in the first nitride layer outside the first mask structure layer, and provides a lateral growth basis for the growth of the second nitride layer. The dislocations are turned during the growth process of the second nitride layer, and finally a high-quality second nitride layer is obtained.

[0046] Further beneficial effects of the present application include: lateral growth during the growth of the second nitride layer causes a pore structure to be formed between the first mask structure layer and the first nitride layer, thereby releasing the subsequent growth stress of the second nitride layer, increasing the thick film growth of the second nitride layer, and being suitable for epitaxial growth of large-size substrates, thereby expanding the process application. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1-Figure 3 It is a schematic diagram of the cross-sectional structure of a semiconductor epitaxial wafer prepared in steps according to an embodiment of the present application.

[0048] Figure 4 It is a schematic diagram of the cross-sectional structure of a semiconductor epitaxial wafer according to an embodiment of the present application.

[0049] Figure 5 This is a TEM test image of the semiconductor epitaxial wafer of Example 1 of the present application.

[0050] Figure 6 This is a TEM test image of the semiconductor epitaxial wafer of Example 4 of the present application.

[0051] Figure 7 This is a TEM test image of the semiconductor epitaxial wafer of comparative example 1 of the present application.

[0052] In the figure: 10, first mask structure layer; 20, first nitride layer; 21, side wall; 30, nitride seed layer; 40, second mask structure layer; 50, second nitride layer; 60, pores; 70, n-type nitride layer; 80, nitride light-emitting layer; 81, nitride quantum well layer; 82, nitride quantum barrier layer; 90, p-type nitride layer; 100, substrate. DETAILED DESCRIPTION

[0053] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the drawings represent the same or similar structures, and thus their repeated description will be omitted. In addition, the present application Figures 1 to 4 It is just a schematic diagram, the height and width are not the actual size.

[0054] The words expressing position and direction described in this application are all explained with reference to the accompanying drawings as examples, but they can be changed as needed, and all changes are included in the scope of protection of this application.

[0055] Lateral epitaxial growth technology can cause dislocations to turn during the lateral epitaxial growth process, thereby effectively reducing the dislocation density in the epitaxial layer and realizing the preparation of high-quality epitaxial materials. How to achieve simple and efficient lateral epitaxial growth technology is still the key to the current growth of high-quality epitaxial layers, and is of great significance for promoting the application of semiconductor materials in the field of high-end semiconductors. This application is based on the lateral epitaxial growth technology to develop a new high-quality epitaxial structure.

[0056] Reference Figures 1 to 3An embodiment of the present application provides a semiconductor epitaxial wafer, including: a substrate 100, a first mask structure layer 10, a first nitride layer 20, a second mask structure layer 40, a second nitride layer 50, and may also include a nitride seed layer 30, an n-type nitride layer 70, a nitride light-emitting layer 80 and a p-type nitride layer 90.

[0057] The substrate 100 may be a sapphire substrate, a SiC substrate or a Si substrate, etc. The substrate 100 of the present application is preferably a sapphire substrate. A first mask structure layer 10 is provided on the substrate 100 of the present application, and the first mask structure layer 10 exposes a portion of the surface of the substrate 100. The first mask structure layer 10 includes but is not limited to a first SiN layer, such as, it may also be a nitride layer such as MgN, BN or TiN, the thickness of the first mask structure layer 10 is 2 to 200 nm, for example, it may be 10 nm, 30 nm, 50 nm, 80 nm, 100 nm, 150 nm, 180 nm, the first mask structure layer 10 may be a patterned structure, so that a portion of the surface of the substrate 100 is exposed from the gap in the first mask structure layer 10.

[0058] A first nitride layer 20 is disposed on the exposed surface of the substrate 100 , wherein the first nitride layer 20 includes but is not limited to a first GaN layer, such as, may be: AlN, AlGAN, InGaN, InN and other group III and IV nitride layers, the thickness of the first nitride layer 20 is 10 to 500 nm, for example, may be: 20 nm, 50 nm, 80 nm, 120 nm, 200 nm, 400 nm, the first nitride layer 20 may fill the exposed surface of the substrate 100 , and the top surface of the first nitride layer 20 is higher than the top surface of the first mask structure layer 10 .

[0059] A second mask structure layer 40 is disposed on the first nitride layer 20. As a preferred embodiment of the present application, the second mask structure layer 40 is a patterned structure. The second mask structure layer 40 can only grow upward on the top surface of the first nitride layer 20, so that the first mask structure layer 10 is exposed from the gap of the second mask structure layer 40 of the patterned structure. The second mask structure layer 40 can include but is not limited to a second SiN layer, such as, it can also be: AlN, AlGAN, InGaN, InN and other III and IV nitride layers, the thickness is 2nm ~ 200nm, can be: 10nm, 30nm, 50nm, 80nm, 100nm, 150nm, 180nm. For example, the first mask structure layer 10 and the second mask structure layer 40 can use the same nitride material.

[0060] As a preferred solution, a nitride seed layer 30 is provided on the top surface of the first nitride layer 20. The nitride seed layer 30 is used to provide a nucleation center for the second mask structure layer 40, thereby improving the uniformity of the second mask structure layer 40, thereby improving the growth quality of the semiconductor epitaxial wafer. The nitride seed layer 30 includes but is not limited to an n-type doped nitride layer, such as an n-type doped GaN layer, and the dopant includes but is not limited to AlN, AlGAN, InGaN, InN and other III and IV group nitrides, and the doping concentration is 2×10 19 ~2×10 20 cm -3 , for example, it can be: 3×10 19 cm -3 , 5×10 19 cm -3 , 1×10 20 cm -3 , 1.5×10 20 cm -3 , 1.8×10 20 cm -3 The thickness of the nitride seed layer 30 is 2 to 20 nm, for example, 3 nm, 6 nm, 9 nm, 12 nm, 15 nm, or 18 nm.

[0061] The second nitride layer 50 covers the second mask structure layer 40. The second mask structure layer 40 is the second nitride layer 50 that covers the dislocations. The second nitride layer 50 also covers at least a portion of the top surface of the first mask structure layer 10 and the outer surface of the first nitride layer 20. The first nitride layer 20 and the second nitride layer 50 are made of the same material. The second nitride layer 50 may include but is not limited to a second GaN layer with a thickness of 1000 to 5000 nm, for example, 1500 nm, 2000 nm, 3500 nm, or 4000 nm. When the nitride seed layer 30 is provided, the second nitride layer 50 covers the nitride seed layer 30 in addition to covering the second mask structure layer 40.

[0062] Therefore, when the semiconductor epitaxial wafer of the present application adopts the above structure, since the growth window area of ​​the first nitride layer 20 is not blocked during the lateral epitaxy of the first mask structure layer 10, the dislocation density is relatively high. By setting the second mask structure layer 40 on the first nitride layer 20, the second mask structure layer 40 shields the dislocation extension of the first nitride layer 20. Under the action of the first mask structure layer 10 and the second mask structure layer 40, a lateral growth basis is provided for the growth of the second nitride layer 50. During the growth process, the dislocations of the second nitride layer 50 are fully redirected to achieve self-annihilation, thereby obtaining a high-quality second nitride layer 50 and providing a growth template for subsequent epitaxial structures.

[0063] In some embodiments, the present invention forms a high-density distributed dislocation center on the surface of the nitride seed layer 30, and the dislocation center point provides a nucleation center for the second mask structure layer 40. The dislocation density is preferably: 1×10 8 ~1×10 12 cm -2 , for example, it can be: 5×10 8 , 1×10 9 cm -2 , 1×10 10 , 1×10 11 cm -2 , 1×10 12 cm -2 , the nitride seed layer 30 can improve the uniformity of the second mask structure layer 40. The density distribution of dislocation centers on the top surface of the nitride seed layer 30 of the present application is greater than the density distribution of dislocation centers on the top surface of the first nitride layer 20. Since the density distribution of dislocation centers on the top surface of the nitride seed layer 30 is greater than the density distribution of dislocation centers on the top surface of the first nitride layer 20, the dislocation centers on the top surface of the first nitride layer 20 can be shielded by the nitride seed layer 30, and the dislocations of the first nitride layer 20 will not extend upward. Similarly, since the second mask structure layer 40 is disposed on the nitride seed layer 30, the high-density dislocation centers on the surface of the nitride seed layer 30 are shielded by the second mask structure layer 40, and the dislocations of the nitride seed layer 30 will not extend upward, and the uniformity of the second mask structure layer 40 can be improved.

[0064] In some embodiments, a pore 60 is formed between the second nitride layer 50 of the present application and a portion of the top surface of the first mask structure layer 10. The pore 60 releases the subsequent growth stress of the second nitride layer 50, which can increase the quality of the thick film growth of the second nitride layer 50, and can be applied to the growth of large-size substrate epitaxial process, thereby expanding the process application. Specifically, due to the high V / III ratio of the second nitride layer 50 during growth, the growth rate of the second nitride layer 50 on the top surface of the first nitride layer 20 is higher than the growth rate of the sidewall 21, so the second nitride layer 50 tends to grow on the top surface of the first nitride layer 20 during growth, and the lateral merging rate of the crystal plane growth of the sidewall 21 is slower, resulting in the formation of the pore 60 during the growth of the second nitride layer 50. Because of the growth rate difference caused by the difference in crystal plane growth rate, there is no need for a special growth process to adjust the longitudinal and lateral growth ratios of the second nitride layer 50, thereby simplifying the growth process and expanding the process window. At the same time, due to the limitation of the second mask structure layer 40, it is not easy for the second nitride layer 50 to nucleate on the second mask structure layer 40 during its growth. Therefore, during its growth, the second nitride layer 50 must first form a top crystal plane of the first nitride layer 20, and then continue to grow along the top crystal plane of the first nitride layer 20. In this process, it is equivalent to increasing the lateral growth ratio of the side wall 21, resulting in the formation of a maximum lateral size of the pore 60 of 5 to 15 nm, for example, 6 nm, 8 nm, 10 nm, or 12 nm. The nanoscale pore 60 releases the growth stress of the nitride epitaxial layer without affecting the mechanical properties of the epitaxial layer.

[0065] In some embodiments, the side of the portion of the first nitride layer 20 of the present application protruding from the first mask structure layer 10 is a sidewall 21, and the top surface of the first nitride layer 20 is a flat surface, that is, the first nitride layer 20 of the present application protrudes from the top of the first mask structure layer 10. The flat top surface of the first nitride layer 20 is conducive to growing a nitride seed layer 30 with uniform thickness and flatness, and is conducive to improving the thickness uniformity of the second mask structure layer 40, and obtaining a second mask structure layer 40 of a desired shape. The sidewalls 21 formed on both sides of the first nitride layer 20 protruding from the first mask structure layer 10 can provide a growth template for the second nitride layer 50, and the sidewalls 21 are conducive to dislocation steering during the growth of the second nitride layer 50. The flat top surface of the first nitride layer 20 can be achieved by controlling the epitaxial process of the MOCVD equipment. Specifically, a relatively high pressure or a low V / III ratio process can increase the diffusion distance of atoms on the top crystal plane of the first nitride layer 20, improve the growth rate of the crystal plane of the side wall 21, and under relatively high pressure process conditions, the stability of the top crystal plane is much lower than that of the side wall 21. Under reducing atmosphere conditions, the decomposition of the crystal plane of the side wall 21 is accelerated, thereby forming a first nitride layer 20 with a locally flat surface.

[0066] like Figure 4As shown, the semiconductor epitaxial wafer of the present application may further include: an n-type nitride layer 70 , a nitride light emitting layer 80 , and a p-type nitride layer 90 .

[0067] As a preferred embodiment of the present application, the n-type nitride layer 70 of the present application is disposed on the second nitride layer 50, and has a thickness of 1000 to 8000 nm, for example, 1500 nm, 2000 nm, 3500 nm, 5000 nm, 7000 nm. The nitride light-emitting layer 80 is disposed on the n-type nitride layer 70, and has a thickness of 5 to 300 nm, for example, 10 nm, 50 nm, 100 nm, 150 nm, 250 nm. The p-type nitride layer 90 is disposed on the nitride light-emitting layer 80, and has a thickness of 50 to 200 nm, for example, 60 nm, 80 nm, 100 nm, 150 nm, 180 nm. As a preferred embodiment of the present application, the nitride light-emitting layer 80 of the present application includes a nitride quantum well layer 81 and a nitride quantum barrier layer 82 that are grown in a periodic cyclic overlapping manner, and the cycle period is 2 to 10, for example, it can be 3, 5, or 8. The single layer thickness of the nitride quantum well layer 81 is 1 to 6 nm, for example, it can be 1.5 nm, 2 nm, 3 nm, 4.5 nm, or 5 nm. The single layer thickness of the nitride quantum barrier layer 82 is 6 to 18 nm, for example, it can be 7 nm, 8 nm, 12 nm, 15 nm, or 17 nm.

[0068] Under the action of the first mask structure layer 10 and the second mask structure layer 40, the present application obtains a high-quality second nitride layer 50. The second nitride layer 50 provides a growth template for the subsequent epitaxial structure, that is, the second nitride layer 50 provides a growth template for the n-type nitride layer 70, the nitride light-emitting layer 80, and the p-type nitride layer 90. The second nitride layer 50 reduces the extension of dislocations to the n-type nitride layer 70 and the nitride light-emitting layer 80, greatly reduces the leakage channel and the non-radiative recombination center, and improves the leakage and luminescence performance of the epitaxial wafer.

[0069] In some embodiments, a method for preparing a semiconductor epitaxial wafer of the present application includes steps S1-S5, and each layer structure of the semiconductor epitaxial wafer can be prepared by MOCVD equipment.

[0070] Step S1: providing a substrate 100 .

[0071] Step S2 : growing a first mask structure layer 10 on the substrate 100 and exposing a portion of the surface of the substrate 100 .

[0072] As an example, the first mask structure layer 10 is a SiN layer grown in situ by MOCVD (the specific thickness has been described above), and the growth conditions are a temperature of 900-1200°C, for example, 920°C, 950°C, 1000°C, 1100°C, and a pressure of 50-650 torr, for example, 80 torr, 100 torr, 200 torr, 350 torr, 500 torr, 600 torr.

[0073] Step S3: Under the conditions of a first temperature, a first pressure, and a first V / III ratio, a first nitride layer 20 (the specific thickness has been described above) is grown on the exposed surface of the substrate 100 , and the top surface of the first nitride layer 20 is higher than the top surface of the first mask structure layer 10 .

[0074] As an example, the growth conditions of the first nitride layer 20 are as follows: a first temperature of 900-1200°C, for example, 920°C, 950°C, 1000°C, or 1100°C; a first pressure of 400-600 torr, for example, 450 torr, 500 torr, or 550 torr; a first V / III ratio (group V / group III gas molar flow ratio) of not more than 1000, for example, 1, 10, 50, 100, 300, 500, 600, 750, or 900, wherein the group V gas is an N source gas and the group III gas is a Ga source gas; the group V / reducing carrier gas molar flow ratio is 1:5-1:100, for example, 1:8, 1:10, 1:20, 1:40, 1:70, or 1:90, and the reducing gas of the present application may be hydrogen.

[0075] The top crystal plane and shape of the first nitride layer 20 are controlled by controlling the MOCVD epitaxial process. In a relatively high pressure or low V / III ratio process (compared with the second pressure and the second V / III during the growth of the second nitride layer 50, the pressure of the first nitride layer 20 is higher and the V / III is lower, specifically refer to the second pressure and the second V / III ratio of the second nitride layer 50 below), the diffusion distance of the crystal plane atoms will be increased, and the growth rate of the side wall 21 crystal plane will be increased. In addition, under relatively high pressure process conditions, the stability of the top crystal plane is much lower than that of the side wall 21 crystal plane. Under reducing atmosphere conditions, the decomposition of the top crystal plane is accelerated, and the width ratio of the local plane on the top surface of the first nitride layer 20 can be increased, thereby forming a first nitride layer 20 with a locally flat surface.

[0076] The sidewall 21 is inclined, which is caused by the growth process of the first nitride layer 20 after masking. The dislocation is naturally interrupted at the interface of the sidewall 21 of the first nitride layer 20. The sidewall 21 can delay the growth merging process of the nitride epitaxial layer, greatly reducing the probability of dislocations extending upward due to continuous growth.

[0077] Step S4 : growing a second mask structure layer 40 (the specific thickness has been described above) on the top surface of the first nitride layer 20 .

[0078] As a preferred solution, the method for preparing a semiconductor epitaxial wafer further includes: before step S4, growing a nitride seed layer 30 on the top surface of the first nitride layer 20 at the third temperature and in a highly doped process. In step S4, growing a second mask structure layer 40 on the nitride seed layer 30.

[0079] As an example, the growth conditions of the second mask structure layer 40 are a temperature of 900-1200°C, for example, 920°C, 950°C, 1000°C, 1100°C, and a pressure of 50 torr-650 torr, for example, 80 torr, 100 torr, 200 torr, 350 torr, 500 torr, 600 torr.

[0080] As an example, the thickness of the nitride seed layer 30 is 2-20 nm, and the doping concentration of the nitride seed layer 30 is 2×10 19 ~2×10 20 cm -3 , for example, it can be 3×10 19 cm -3 , 5×10 19 cm -3 , 1×10 20 cm -3 , 1.5×10 20 cm -3 , 1.8×10 20 cm -3 The growth conditions of the nitride seed layer 30 are a temperature of 700 to 1000° C., for example, 750° C., 800° C., 900° C., 950° C., and a pressure of 50 torr to 650 torr, for example, 80 torr, 100 torr, 200 torr, 350 torr, 500 torr, and 600 torr. The nitride seed layer 30 is preferably an n-type doped nitride layer, and a highly doped nitride layer is formed by controlling the temperature and doping concentration. A highly densely distributed dislocation center is formed on the surface of the highly doped nitride layer. The dislocation center point provides a nucleation center for the second mask structure layer, which is used to improve the uniformity of the second mask structure layer 40. The dislocation density is 1×10 8 ~1×10 12 cm -2 , for example, it can be 1×10 8 cm -2 , 1×10 9 cm -2 , 1×10 10 cm -2, 1×10 11 cm -2 , 1×10 12 cm -2 .

[0081] Since the crystal growth rate of the nitride seed layer 30 on the top surface of the first nitride layer 20 is much higher than that of the side wall 21, the nitride seed layer 30 will preferentially grow on the top surface of the first nitride layer 20; and since the second mask structure layer 40 is disposed on the nitride seed layer 30, the high-density dislocation centers on the surface of the nitride seed layer 30 are shielded by the second mask structure layer 40 and will not extend to the upper epitaxial layer, and the uniformity of the second mask structure layer 40 can be improved.

[0082] Step S5: Under the conditions of a second temperature, a second pressure, and a second V / III ratio, a second nitride layer 50 (the specific thickness has been described above) is grown on the second mask structure layer 40, and the second nitride layer 50 covers at least a portion of the top surface of the first mask structure layer 10, the outer surface of the first nitride layer 20, and the outer surface of the second mask structure layer 40.

[0083] When the nitride seed layer 30 is provided, the second nitride layer 50 also covers the nitride seed layer 30 .

[0084] As an example, the growth conditions of the second nitride layer 50 are as follows: the second temperature is 900°C to 1200°C, for example, it can be 920°C, 950°C, 1000°C, or 1100°C; the second pressure is 100 to 400 torr, for example, it can be 120 torr, 150 torr, 200 torr, 300 torr, or 350 torr; the second V / III ratio (molar flow ratio of group V / group III gas) is 2000 to 8000, for example, it can be 2400, 3000, 3500, 4200, 5000, 6000, or 7500.

[0085] The second V / III ratio during the growth of the second nitride layer 50 is greater than the first V / III ratio. In an environment with a high V / III ratio, the growth rate of the second nitride layer 50 on the top surface of the first nitride layer 20 is higher than the growth rate of the side wall 21. Therefore, during the growth of the second nitride layer 50, it will first tend to grow on the top surface of the first nitride layer 20, and the lateral merging rate of the crystal plane growth of the side wall 21 is slower, resulting in the formation of pores 60 during the growth of the second nitride layer 50.

[0086] Because the width of the local plane at the top of the first nitride layer 20 accounts for a large proportion, it affects the merging process of the second nitride layer 50. The large proportion can delay the merging process of the second nitride layer 50. During the growth of the second nitride layer 50, dislocations have a greater probability of turning, which is beneficial to improving the crystal quality of the second nitride layer 50. At the same time, the large proportion will increase the longitudinal height of the pores 60. At this time, a thicker second nitride layer 50 is required to match it to form a second nitride layer 50 with a smooth surface. The longitudinal increase of the pores 60 has a stronger stress release effect when growing a thicker epitaxial layer, ensuring that when the epitaxial layer is thick, there will be no cracks due to excessive stress.

[0087] As a preferred method for preparing the semiconductor epitaxial wafer of the present application, the following steps S6-S8 are also included.

[0088] Step S6 : growing an n-type nitride layer 70 (the specific thickness has been described above) on the second nitride layer 50 .

[0089] As an example, the growth conditions are a temperature of 950-1250°C, for example, 1000°C, 1050°C, 1150°C, 1200°C, and a pressure of 50-650 torr, for example, 80 torr, 100 torr, 200 torr, 350 torr, 500 torr, 600 torr.

[0090] Step S7 : growing a nitride light emitting layer 80 (the specific thickness has been described above) on the n-type nitride layer 70 .

[0091] As an example, the growth conditions are a temperature of 700-1000° C., for example, 750° C., 800° C., 900° C., 950° C., and a pressure of 100-500 torr, for example, 150 torr, 200 torr, 350 torr, 400 torr.

[0092] Step S8 : growing a p-type nitride layer 90 (the specific thickness has been described above) on the nitride light emitting layer 80 .

[0093] As an example, the growth conditions are a temperature of 950-1150° C., for example, 1000° C., 1050° C., 1100° C., and a pressure of 100-600 torr, for example, 150 torr, 200 torr, 300 torr, 400 torr, 500 torr, 550 torr.

[0094] Embodiment 1:

[0095] like Figures 1 to 4 As shown, the semiconductor epitaxial wafer includes the following steps.

[0096] 1) Provide a sapphire substrate 100 and place it in an epitaxial growth reaction chamber of a MOCVD device.

[0097] 2) Under the conditions of temperature 1150° C. and pressure 200 torr, a first mask structure layer 10 of SiN material with a thickness of 20 nm is grown on the substrate 100, the Si source used is SiH4, the N source used is NH3, and the growth atmosphere is H2.

[0098] 3) A first nitride layer 20 of GaN material with a thickness of 80 nm is grown on the substrate 100 not covered by the first mask structure layer 10 at a temperature of 1085°C, a pressure of 500 torr, a molar flow ratio of group V to group III gas of 200, and a molar flow ratio of group V to reducing carrier gas of 1:20. The Ga source used is TMG, the N source used is NH3, and the growth atmosphere is H2.

[0099] 4) Under the conditions of temperature 780°C and pressure 100 torr, a nitride seed layer 30 is grown on the first nitride layer 20, i.e., an n-type GaN seed layer, and the Si doping concentration is 8×10 19 cm -3 The Ga source used is TMG, the Si source used is SiH4, the N source used is NH3, and the growth atmosphere is H2.

[0100] 5) Under the conditions of temperature 1150° C. and pressure 150 torr, a second mask structure layer 40 of SiN material with a thickness of 20 nm is grown on the nitride seed layer 30 , the Si source used is SiH 4 , the N source used is NH 3 , and the growth atmosphere is H 2 .

[0101] 6) Under the conditions of temperature 1095°C, pressure 200 torr, and molar flow ratio of group V / group III gas of 4000, a second nitride layer 50 with a thickness of 1500 nm, i.e., a GaN layer, is grown on part of the first mask structure layer 10 and the second mask structure layer 40. The Ga source used is TMG, the N source used is NH3, and the growth atmosphere is H2.

[0102] 7) At a temperature of 1085°C and a pressure of 200 torr, an n-type nitride layer 70 with a thickness of 2500 nm is grown on the second nitride layer 50, i.e., an n-type GaN layer. The Ga source used is TMG, the Si source used is SiH4, the N source used is NH3, and the growth atmosphere is H2.

[0103] 8) A nitride light-emitting layer 80 is grown on the n-type nitride layer 70 at a pressure of 400 torr, including a single-layer InGaN quantum well layer with a thickness of 2 nm and a single-layer GaN quantum barrier layer with a thickness of 15 nm that are periodically and overlappingly grown. The cycle period is 5, the growth temperature of the InGaN quantum well layer is 750°C, the growth atmosphere is N2, the growth temperature of the GaN quantum barrier layer is 920°C, the growth atmosphere is H2, the Ga source used is TEG, and the N source used is NH3.

[0104] 9) Under the conditions of temperature 1020° C. and pressure 400 torr, a p-type nitride layer 90 with a thickness of 120 nm is grown on the nitride light emitting layer 80 . The p-type nitride layer 90 is a p-type GaN layer, and the p-type dopant is Mg.

[0105] Embodiment 2:

[0106] like Figures 1 to 4 As shown, the semiconductor epitaxial wafer includes the following steps.

[0107] 1) Provide a sapphire substrate 100 and place it in an epitaxial growth reaction chamber of a MOCVD device.

[0108] 2) Under the conditions of temperature 900° C. and pressure 50 torr, a first mask structure layer 10 of SiN material with a thickness of 2 nm is grown on the substrate 100, the Si source used is SiH 4 , the N source used is NH 3 , and the growth atmosphere is H 2 .

[0109] 3) A first nitride layer 20 of GaN material with a thickness of 10 nm is grown on the substrate 100 not covered by the first mask structure layer 10 at a temperature of 900°C, a pressure of 400 torr, a molar flow ratio of group V to group III gas of 10, and a molar flow ratio of group V to reducing carrier gas of 1:5. The Ga source used is TMG, the N source used is NH3, and the growth atmosphere is H2.

[0110] 4) Under the conditions of temperature 700°C and pressure 50 torr, a nitride seed layer 30, i.e., an n-type GaN seed layer, is grown on the first nitride layer 20, and the Si doping concentration is 2×10 19 cm -3 The Ga source used is TMG, the Si source used is SiH4, the N source used is NH3, and the growth atmosphere is H2.

[0111] 5) Under the conditions of temperature 900° C. and pressure 50 torr, a second mask structure layer 40 of SiN material with a thickness of 2 nm is grown on the nitride seed layer 30 , the Si source used is SiH 4 , the N source used is NH 3 , and the growth atmosphere is H 2 .

[0112] 6) Under the conditions of temperature 900°C, pressure 100 torr, and molar flow ratio of group V / group III gas of 2000, a second nitride layer 50 with a thickness of 1000 nm, i.e., a GaN layer, is grown on part of the first mask structure layer 10 and the second mask structure layer 40. The Ga source used is TMG, the N source used is NH3, and the growth atmosphere is H2.

[0113] 7) At a temperature of 950°C and a pressure of 50 torr, an n-type nitride layer 70 with a thickness of 1000 nm is grown on the second nitride layer 50, i.e., an n-type GaN layer. The Ga source used is TMG, the Si source used is SiH4, the N source used is NH3, and the growth atmosphere is H2.

[0114] 8) A nitride light-emitting layer 80 is grown on the n-type nitride layer 70 under a pressure of 100 torr, including a single-layer InGaN quantum well layer with a thickness of 1 nm and a single-layer GaN quantum barrier layer with a thickness of 6 nm that are periodically and overlappingly grown. The cycle period is 2, the growth temperature of the InGaN quantum well layer is 700°C, and the growth atmosphere is N2. The growth temperature of the GaN quantum barrier layer is 900°C, and the growth atmosphere is H2. The Ga sources used are all TEG, and the N sources used are all NH3.

[0115] 9) Under the conditions of temperature 950° C. and pressure 100 torr, a p-type nitride layer 90 with a thickness of 50 nm is grown on the nitride light emitting layer 80 . The p-type nitride layer 90 is a p-type GaN layer, and the p-type dopant is Mg.

[0116] Embodiment 3:

[0117] like Figures 1 to 4 As shown, the semiconductor epitaxial wafer includes the following steps.

[0118] 1) Provide a sapphire substrate 100 and place it in an epitaxial growth reaction chamber of a MOCVD device.

[0119] 2) Under the conditions of temperature 1200° C. and pressure 650 torr, a first mask structure layer 10 of SiN material with a thickness of 200 nm is grown on the substrate 100, the Si source used is SiH4, the N source used is NH3, and the growth atmosphere is H2.

[0120] 3) A first nitride layer 20 of GaN material with a thickness of 500 nm is grown on the substrate 100 not covered by the first mask structure layer 10 at a temperature of 1200°C, a pressure of 600 torr, a molar flow ratio of group V to group III gas of 900, and a molar flow ratio of group V to reducing carrier gas of 1:100. The Ga source used is TMG, the N source used is NH3, and the growth atmosphere is H2.

[0121] 4) Under the conditions of temperature 1000°C and pressure 650 torr, a nitride seed layer 30 is grown on the first nitride layer 20, i.e., an n-type GaN seed layer, and the Si doping concentration is 2×10 20 cm -3 The Ga source used is TMG, the Si source used is SiH4, the N source used is NH3, and the growth atmosphere is H2.

[0122] 5) Under the conditions of temperature 1200° C. and pressure 650 torr, a second mask structure layer 40 of SiN material with a thickness of 100 nm is grown on the nitride seed layer 30 , the Si source used is SiH 4 , the N source used is NH 3 , and the growth atmosphere is H 2 .

[0123] 6) Under the conditions of temperature 1200°C, pressure 400 torr, and molar flow ratio of group V / group III gas of 8000, a second nitride layer 50 with a thickness of 5000 nm, i.e., a GaN layer, is grown on part of the first mask structure layer 10 and the second mask structure layer 40. The Ga source used is TMG, the N source used is NH3, and the growth atmosphere is H2.

[0124] 7) Under the conditions of temperature 1250°C and pressure 650 torr, an n-type nitride layer 70 with a thickness of 8000nm is grown on the second nitride layer 50, i.e., an n-type GaN layer. The Ga source used is TMG, the Si source used is SiH4, the N source used is NH3, and the growth atmosphere is H2.

[0125] 8) A nitride light-emitting layer 80 is grown on the n-type nitride layer 70 under a pressure of 500 torr, including a single-layer InGaN quantum well layer with a thickness of 6 nm and a single-layer GaN quantum barrier layer with a thickness of 18 nm that are periodically and overlappingly grown. The cycle period is 10, the growth temperature of the InGaN quantum well layer is 800°C, and the growth atmosphere is N2. The growth temperature of the GaN quantum barrier layer is 1000°C, and the growth atmosphere is H2. The Ga sources used are all TEG, and the N sources used are all NH3.

[0126] 9) Under the conditions of temperature 1150° C. and pressure 600 torr, a p-type nitride layer 90 with a thickness of 200 nm is grown on the nitride light emitting layer 80 . The p-type nitride layer 90 is a p-type GaN layer, and the p-type dopant is Mg.

[0127] Embodiment 4:

[0128] like Figures 1 to 4 As shown, the semiconductor epitaxial wafer includes the following steps.

[0129] 1) Provide a sapphire substrate 100 and place it in an epitaxial growth reaction chamber of a MOCVD device.

[0130] 2) Same as step 2) of Example 1.

[0131] 3) Same as step 3) of Example 1.

[0132] 4) Under the conditions of temperature 1150° C. and pressure 150 torr, a second mask structure layer 40 of SiN material with a thickness of 20 nm is grown on the first nitride layer 20 , the Si source used is SiH 4 , the N source used is NH 3 , and the growth atmosphere is H 2 .

[0133] 5) Same as step 6) of Example 1.

[0134] 6) Same as step 7) of Example 1.

[0135] 7) Same as step 8) of Example 1.

[0136] 8) Same as step 9) of Example 1.

[0137] Comparative Example 1:

[0138] like Figures 1 to 4 As shown, the semiconductor epitaxial wafer includes the following steps.

[0139] 1) Provide a sapphire substrate 100 and place it in an epitaxial growth reaction chamber of a MOCVD device.

[0140] 2) Under the conditions of temperature 1150°C and pressure 200 torr, a first mask structure layer 10 of SiN material with a thickness of 20 nm is grown on the substrate 100, the first mask structure layer 10 covers the substrate 100, the Si source used is SiH4, the N source used is NH3, and the growth atmosphere is H2.

[0141] 3) Under the conditions of temperature 780°C and pressure 100 torr, a nitride seed layer 30, i.e., an n-type GaN seed layer, is grown on the first mask structure layer 10, and the Si doping concentration is 8×10 19 cm -3 The Ga source used is TMG, the Si source used is SiH4, the N source used is NH3, and the growth atmosphere is H2.

[0142] 4) Under the conditions of temperature 1095°C, pressure 200 torr, and molar flow ratio of group V / group III gas of 4000, a second nitride layer 50 with a thickness of 1500 nm, i.e., a GaN layer, is grown on part of the first mask structure layer 10. The Ga source used is TMG, the N source used is NH3, and the growth atmosphere is H2.

[0143] 5) Same as step 7) of Example 1.

[0144] 6) Same as step 8) of Example 1.

[0145] 7) Same as step 9) of Example 1.

[0146] Test results:

[0147] The embodiments and comparative examples were respectively subjected to high-resolution X-ray diffraction (XRD) test to measure the (002) / (102) half-peak width, cathode luminescence (CL) etching pit method to measure the dislocation density, and the LED chip photoelectric performance test to measure the brightness and leakage performance.

[0148] The test data is as follows:

[0149]

[0150] in conclusion:

[0151] It can be seen from the data that the (002) crystal plane and (102) crystal plane of Example 1, Example 2 and Example 3 have lower diffraction peak half-width, and the dislocation density is one order of magnitude lower than that of the control example, indicating that by setting the first mask structure layer 10 and the second mask structure layer 40, the growth quality of the second nitride layer 50 is improved, and the epitaxial wafer has higher brightness and excellent leakage performance. The present invention greatly reduces the leakage channel and non-radiative recombination center, and improves the leakage and luminescence performance of the epitaxial wafer.

[0152] Referring to the TEM test images of Example 1, Example 4 and Comparative Example 1, it can be seen that almost no dislocation extension is observed in the second nitride layer 50 in Example 1, and the dislocation is turned and self-annihilated during the growth of the first nitride layer 20 .

[0153] Example 4

[0154] Without the nitride seed layer 30 , the second mask structure layer 40 has relatively poor distribution uniformity, and dislocations may still partially extend into the second nitride layer 50 in the unevenly distributed regions.

[0155] Comparative Example 1

[0156] During the growth process, a large number of dislocations extend into the second nitride layer 50 .

[0157] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the application without departing from the principles and purpose of the present application. All of these changes should fall within the scope of protection of the claims of the present application.

Claims

1. A semiconductor epitaxial wafer, characterized in that: include: Base (100); A first mask structure layer (10), the first mask structure layer (10) being arranged on the substrate (100) and exposing a portion of the surface of the substrate (100); A first nitride layer (20), the first nitride layer (20) being arranged on the exposed surface of the substrate (100), the top surface of the first nitride layer (20) being higher than the top surface of the first mask structure layer (10); A second mask structure layer (40), wherein the second mask structure layer (40) is located on the first nitride layer (20); A second nitride layer (50), wherein the second nitride layer (50) covers the second mask structure layer (40), the second mask structure layer (40) masks dislocations for the second nitride layer (50), and the second nitride layer (50) covers at least a portion of the top surface of the first mask structure layer (10) and an outer surface of the first nitride layer (20).

2. The semiconductor epitaxial wafer according to claim 1, characterized in that: The semiconductor epitaxial wafer further comprises: a nitride seed layer (30), wherein the nitride seed layer (30) is arranged on the first nitride layer (20) and is used to provide a nucleation center for the second mask structure layer (40).

3. The semiconductor epitaxial wafer according to claim 1, characterized in that: The dislocation density of the nitride seed layer (30) is greater than that of the first nitride layer (20), and the dislocation density of the nitride seed layer (30) is 1×10 8 ~1×10 12 cm -2 ; Preferably, the thickness of the nitride seed layer (30) is 2-20 nm, and the nitride seed layer (30) is an n-type doped nitride layer with a doping concentration of 2×10 19 cm -3 ~2×10 20 cm -3 .

4. The semiconductor epitaxial wafer according to claim 1, characterized in that: A pore (60) is formed between the second nitride layer (50) and a portion of the top surface of the first mask structure layer (10); the lateral size of the pore (60) is 5 to 15 nm.

5. The semiconductor epitaxial wafer according to claim 2, characterized in that: The first mask structure layer (10) is a first SiN layer with a thickness of 2 to 200 nm; and / or, The first nitride layer (20) is a first GaN layer with a thickness of 10 to 500 nm; and / or, The second mask structure layer (40) is a second SiN layer with a thickness of 2 to 200 nm; and / or, The second nitride layer (50) is a second GaN layer with a thickness of 1000 to 5000 nm; and / or It also includes: an n-type nitride layer (70), the n-type nitride layer (70) being arranged on the second nitride layer (50) and having a thickness of 1000 to 8000 nm; A nitride light-emitting layer (80), the nitride light-emitting layer (80) being disposed on the n-type nitride layer (70) and having a thickness of 5 to 300 nm; A p-type nitride layer (90) is provided on the nitride light-emitting layer (80) and has a thickness of 50 to 200 nm.

6. A method for preparing a semiconductor epitaxial wafer, characterized in that: The steps include: Providing a substrate (100); Growing a first mask structure layer (10) on the substrate (100) and exposing a portion of the surface of the substrate (100); Under the conditions of a first temperature, a first pressure and a first V / III ratio, growing a first nitride layer (20) on the exposed surface of the substrate (100), wherein the top surface of the first nitride layer (20) is higher than the top surface of the first mask structure layer (10); Growing a second mask structure layer (40) on the top surface of the first nitride layer (20); Under the conditions of a second temperature, a second pressure and a second V / III ratio, a second nitride layer (50) is grown on the second mask structure layer (40), wherein the second mask structure layer (40) covers dislocations of the second nitride layer (50), and the second nitride layer (50) covers at least a portion of the top surface of the first mask structure layer (10), the outer surface of the first nitride layer (20), and the outer surface of the second mask structure layer (40).

7. The method for preparing a semiconductor epitaxial wafer according to claim 6, characterized in that: The first pressure is greater than the second pressure, and the first V / III ratio is lower than the second V / III ratio; Preferably, the first pressure is 400-600 torr, the second pressure is 100-400 torr, the first V / III ratio is less than 1000, and the second V / III ratio is 2000-8000; Wherein, under a high-voltage and low-V / III ratio process, a portion of the first nitride layer (20) protruding from the first mask structure layer (10) forms a sidewall (21); Forming the first nitride layer (20) further comprises: under the condition of reducing gas, the local side wall (21) decomposes to form a flat top surface of the first nitride layer (20); more preferably, the molar flow ratio of group V / reducing carrier gas is 1:5 to 1:

100.

8. The method for preparing a semiconductor epitaxial wafer according to claim 7, characterized in that: Also includes: Under a third temperature and high doping process, a nitride seed layer (30) is grown on the top surface of the first nitride layer (20), the nitride seed layer (30) being used to provide a nucleation center for the second mask structure layer (40); the dislocation density of the nitride seed layer (30) is 1×10 8 ~1×10 12 cm -2 ; The nitride seed layer (30) has a thickness of 2 to 20 nm and is an n-type doped nitride layer with a doping concentration of 2×10 19 cm -3 ~2×10 20 cm -3 .

9. The method for preparing a semiconductor epitaxial wafer according to claim 6, characterized in that: Under the conditions of a second temperature, a second pressure, and a second V / III ratio, the 0001 plane growth rate of the second nitride layer (50) is higher than the side surface of the second nitride layer (50), and under the limiting effect of the second mask structure layer (40), a pore (60) is formed between the second nitride layer (50) and a portion of the top surface of the first mask structure layer (10); wherein the lateral size of the pore (60) is 5 to 15 nm.

10. The method for preparing a semiconductor epitaxial wafer according to claim 8, characterized in that: The first mask structure layer (10) is a SiN layer grown in situ by MOCVD, and the growth conditions are a temperature of 900-1200° C. and a pressure of 50-650 torr; and / or, The growth condition of the first nitride layer (20) is that the first temperature is 900-1200° C.; and / or, The growth conditions of the nitride seed layer (30) are a temperature of 700-1000° C. and a pressure of 50-650 torr; and / or, The growth conditions of the second mask structure layer (40) are a temperature of 900-1200° C. and a pressure of 50-650 torr; and / or, The growth condition of the second nitride layer (50) is that the second temperature is 900-1200° C.; and / or, The method further comprises sequentially growing an n-type nitride layer (70), a nitride light-emitting layer (80), and a p-type nitride layer (90) on the second nitride layer (50); The growth conditions of the n-type nitride layer (70) are a temperature of 950-1250° C. and a pressure of 50-650 torr; The growth conditions of the nitride light-emitting layer (80) are a temperature of 700-1000° C. and a pressure of 100-500 torr; The growth conditions of the p-type nitride layer (90) are a temperature of 950-1150° C. and a pressure of 100-600 torr.

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