Low jitter delay cell
By combining resistive digital-to-analog converter and insufficient current delay unit, a hybrid delay unit that provides low jitter performance at low power is achieved, solving the problem of delay unit jitter limitation in the DLL-based serial link, and optimizing the performance and power consumption of the delay line.
Patent Information
- Application Number
- CN202380071091.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-10-13
- Filing Date
- 2023-08-23
- Publication Date
- 2025-05-16
AI Technical Summary
In a serial link design based on a delay locking ring (DLL), jitter of the delay unit is an important limiting factor in achieving high data rates. Existing solutions such as insufficient current delay units, power supply tuning delay units, or analog replication units are limited by thermal noise of MOS devices, making it difficult to provide improved low jitter performance at low power.
Using a hybrid delay unit, combined with a resistive digital-to-analog converter (R-DAC) and a low current delay unit, provides inherent low jitter delay delay through the first stage and fine-tune it with a programmable low current delay unit of the second stage to achieve low jitter configurable delay generation at low power.
Provides lower jitter performance than conventional low-current delay units at low power, optimizes the performance of the delay line, reduces power consumption, and improves the configurability of the delay.
Smart Images
Figure CN120019574A_ABST
Abstract
Description
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS
[0002] This application claims the benefit of U.S. Patent Application No. 18 / 046,283, filed on October 13, 2022, entitled “LOW JITTER DELAY CELL,” which is expressly incorporated herein by reference in its entirety. Technical Field
[0003] An apparatus is provided herein for a programmable low jitter delay cell suitable for use in, for example, a delay locked loop (DLL) based serial link. Background Art
[0004] Delay cell jitter can be a significant limiting factor in achieving high data rates in DLL (delay locked loop) based serial link designs. The thermal noise of the delay cell in the CMOS transistor channel is the main source of jitter. The typical solution to this problem is to provide a power noise tradeoff. This is usually achieved by burning more current in the device to reduce jitter. However, this comes at the expense of increased power consumption. Current solutions involve using current starved delay cells, power supply tuned delay cells or analog replica cells, however these solutions are limited by the thermal noise of MOS devices.
[0005] It would therefore be desirable to provide a topology that can provide improved low jitter performance at low power. Summary of the invention
[0006] A delay cell for a delay locked loop (DLL) based serial link is provided, the delay cell comprising a first stage and a second stage, wherein the output of the first stage is the input to the second stage, the first stage comprising a resistive digital-to-analog converter (R-DAC), and the second stage comprising a current starvation delay cell.
[0007] This hybrid delay cell combines the inherently lower jitter delay generation using the RDAC with the area efficient delay configuration in the current starved delay cell. Combining these two provides low jitter configurable delay generation at low power.
[0008] The first stage may include a first field effect transistor FET and a second field effect transistor FET, wherein the drain of the first transistor may be coupled to the drain of the second FET, and wherein the gate of the first FET is coupled to the gate and input of the second FET. Such a first stage provides a lower level of jitter than a device-based delay cell.
[0009] The delay unit may further include a first resistor coupled in series between the first voltage level and a source of the first FET, and a second resistor coupled in series between the source of the second FET and the second voltage level.
[0010] The first FET may be a pFET and the second FET may be an nFET.
[0011] The first stage provides fixed delay, coarse tuning, low jitter and low noise. The first stage provides low noise performance.
[0012] The second stage may include n sections coupled in series, each section including a third field effect transistor FET and a fourth field effect transistor FET, wherein the drain of the third FET is coupled to the drain of the fourth FET and the output of the section, and wherein the gate of the third FET is coupled to the gate of the fourth FET and the input of the section.
[0013] The second stage may further include a fifth FET, wherein a drain of the fifth FET is coupled to a source of the third FET, wherein a source of the fifth FET is coupled to the first voltage level, and wherein a gate of the fifth FET is coupled to the third voltage level.
[0014] The second stage may also include a sixth FET, wherein a drain of the sixth FET is coupled to a source of the fourth FET, wherein a source of the sixth FET is coupled to the second voltage level, and wherein a gate of the sixth FET is coupled to the fourth voltage level.
[0015] The third FET and the fifth FET may be pFETs, and the fourth FET and the sixth FET may be nFETs.
[0016] The number of parts n may be greater than or equal to 3. It will be appreciated that this allows varying the delay provided.
[0017] The output of the second stage may be coupled to the output of the nth section of the n sections, and the input of the second stage may be coupled to the input of the first section of the n sections.
[0018] The second stage provides fine control using a programmable undercurrent delay cell for fine tuning. The combination of the first stage providing coarse tuning and the second stage providing fine tuning optimizes the performance of the delay line. The hybrid combination provides lower jitter than conventional undercurrent delay cells at comparable power in comparable processes (e.g., 7nm processes).
[0019] The delay unit may further include an inverter coupled to the output of the second stage.
[0020] The delay cell may be fabricated according to a 7 nanometer lithography process. However, it should be understood that the topology is not so limited.
[0021] A method of providing a delay cell for use in a delay locked loop (DLL) based serial link is claimed herein, the method comprising providing a first stage and a second stage, wherein the output of the first stage is an input to the second stage, the first stage comprising a resistive digital to analog converter, and the second stage comprising a current starved delay cell.
[0022] The first stage may include a first field effect transistor FET and a second field effect transistor FET, wherein the drain of the first FET is coupled to the drain of the second FET, and wherein the gate of the first FET is coupled to the gate of the second FET and to the input.
[0023] The method may also include coupling a first resistor in series between the first voltage level and a source of the first FET, and coupling a second resistor in series between a source of the second FET and a second voltage level (204).
[0024] The first FET may be a pFET and the second FET may be an nFET.
[0025] The second stage may include n sections coupled in series, each section including a third field effect transistor FET and a fourth field effect transistor FET, wherein the drain of the third FET is coupled to the drain of the fourth FET and the output of the section, and wherein the gate of the third FET is coupled to the gate of the fourth FET and the input of the section.
[0026] The second stage may further include a fifth FET, wherein a drain of the fifth FET is coupled to a source of the third FET, wherein a source of the fifth FET is coupled to the first voltage level, and wherein a gate of the fifth FET is coupled to the third voltage level.
[0027] The second stage may also include a sixth FET, wherein a source of the sixth FET is coupled to a drain of the fourth FET, wherein a drain of the sixth FET is coupled to a source of the fourth FET, wherein a source of the sixth FET is coupled to the second voltage level, and wherein a gate of the sixth FET is coupled to the fourth voltage level.
[0028] The third FET and the fifth FET may be pFETs, and the fourth FET and the sixth FET may be nFETs.
[0029] The number n of parts may be greater than or equal to three.
[0030] Each of the plurality of sections may be coupled in series such that an input to the second stage is an input to a first of the plurality of sections and an output of the second stage is an output to a last of the plurality of sections.
[0031] The method may further include coupling an inverter to the output of the second stage.
[0032] In another configuration, a delay locked loop (DLL) is provided, which includes a plurality of delay cells having the above-mentioned features.
[0033] In a further configuration, a serial link including a delay locked loop according to the present invention is provided. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 is a block diagram of an example of a hybrid delay unit according to the present invention;
[0035] Figure 2 is a circuit diagram showing an example first stage of a hybrid delay cell according to the present invention;
[0036] Figure 3 A number of alternative configurations for the first stage of a hybrid delay cell according to the present invention are provided;
[0037] Figure 4 is a circuit diagram of an exemplary second stage of a hybrid delay cell according to the present invention;
[0038] Figure 5 is a circuit diagram of an example of a hybrid delay unit according to the present invention;
[0039] Figure 6 is a representation of a delay locked loop including N stages of delay lines in one implementation of the present invention; and
[0040] Figure 7 is a flow chart of an example of a method according to the present application. DETAILED DESCRIPTION
[0041] The present invention will now be described with reference to the accompanying drawings. Figure 1 1 is a representation of an example of a hybrid delay cell 100. The hybrid delay cell 100 includes a first stage 101, and a second stage 102 is coupled in series to the first stage. The output of the first stage 104 is the input of the second stage 102. In a preferred configuration, the first stage 101 includes a resistive digital-to-analog converter R-DAC 201. The second stage includes a current-deficient delay cell 301. Both the first stage and the second stage will be described in more detail below. The input of the first stage 101 can be a clock signal. The output of the second stage is the clock signal to the delay.
[0042] An exemplary configuration of the first stage 101 is as follows Figure 21. The first stage 101 includes a first field effect transistor FET 201. A second FET 202 is also provided. The drain of the first FET 201 is coupled to the drain of the second FET 202. The output 104 of the first stage 101 is coupled to the drain of the first FET and the drain of the second FET. The gate of the first FET 201 and the gate of the second FET 202 are coupled together and coupled to the input 103. The first FET and the second FET form an inverter. A first resistor 203 is coupled to the source of the first FET 201. The first resistor 203 is coupled in series between a first voltage level Vddfx provided by a first voltage input (not shown) and the source of the first FET 201. The first resistor 203 is a variable resistor. A second resistor 204 is coupled to the source of the second FET 202. The second resistor 204 is coupled in series between the source of the second FET 202 and a second voltage level Vssfx. The second voltage level is provided at the second voltage input. The first FET is a pFET, and the second FET is an nFET.
[0043] In one configuration, Vssfx may be ground or 0 V. Vddfx is a power supply voltage and is variable depending on the relevant process technology used in the fabrication of the delay cell. For example, for 6nm to 14nm processes, Vddfx may be in the range of 0.7V to 0.9V.
[0044] Although a single inverter section is shown in the first stage 101 , it will be appreciated that the inverter configuration may be replicated to provide n sections, where n>1.
[0045] The equivalent circuit of the first stage 101 is as follows Figure 3 As shown. Figure 3 A four-bit resistive digital-to-analog converter cell is shown in FIG. 1 , but it will be appreciated that the circuit elements can be easily repeated to extend the resistive DAC cell.
[0046] In a first configuration, a first stage 101 is provided. The first stage 101 includes a first field effect transistor FET 201. A second FET 202 is also provided. The drain of the first FET is coupled to the drain of the second FET. An output 104 of the first stage 101 is coupled to the drain of the first FET and the drain of the second FET. The gate of the first FET and the gate of the second FET are coupled together and coupled to an input 103. The first FET and the second FET form an inverter. A first resistor 203 is coupled to the source of the first FET 201. The first resistor 203 is coupled in series between a first voltage level Vddfx provided by a first voltage input (not shown) and the source of the first FET 201. The first resistor 203 may be a variable resistor. A second resistor 204 is coupled to the source of the second FET. The second resistor 204 is coupled in series between the source of the second FET 202 and a second voltage level Vssfx. The second voltage level is provided at the second voltage input. The first FET is a pFET, and the second FET is an nFET.
[0047] In a second equivalent configuration, as shown in 3(b), the first resistor 203 is depicted as a 4-level binary weighted resistor ladder or resistor bank. The inverter comprising the first FET 201 and the second FET 202 is the same as described with respect to 3(a). The values of the weighted resistors are multiples of 2. The resistor in the most significant bit position has a value of R, the next resistor has a value of 2R, and so on. It should be understood that this can be extended to 2 N , where N is the number of bits (4 in this case). Each resistor is coupled to a switching FET that is used to switch in response to a corresponding digital input. In the configuration shown in 3(b), the source of each switching FET is coupled to Vdd (Vddfx). The drain of the switching FET is coupled to the corresponding resistor in the ladder. Rdac[3:0] is provided to the gate. It can be understood that Figure 3 The rdac_b shown is the inverse of rdac[3:0].
[0048] Similarly, the second resistor 204 is depicted as having a 4-level binary weighted resistor ladder or resistor group. The values of the weighted resistors are multiples of 2. The resistor in the most significant bit position has a value of R, the next resistor has a value of 2R, and so on. It should be understood that this can be extended to 2 N . Each resistor is coupled to a switching FET that is used to switch between binary 1 and 0. In the configuration shown in 3(b), the source of each switching FET is coupled to ground. The drain of the switching FET is coupled to the corresponding resistor in the ladder. Rdac[3:0] is provided to the gate. It can be understood that Figure 3 The rdac_b shown is the inverse of rdac[3:0].
[0049] The configuration shown in 3(c) provides an alternative equivalent arrangement in which the positions of the resistors and switch transistors are switched. The first resistor 203 is depicted by a resistor ladder in which the resistors are coupled between Vdd and the source of their corresponding switch transistors. Similarly, the second resistor is depicted by a resistor ladder in which the resistor elements are located between the source of the corresponding switch transistor and ground. As with the configuration of 3b, the values of the weighted resistors are multiples of 2. The resistor in the most significant bit position has a value of R, the next resistor has a value of 2R, and so on. It will be appreciated that this can be extended to 2 N , where N is the number of bits (4 in this case).
[0050] Figure 3 The equivalent circuit of (d) positions the resistor ladder at the output of the inverter circuit formed by the first FET 201 and the second FET 202. Figure 3 (b) and Figure 3 As with the equivalent circuit of (c), the resistors are weighted resistors with values that are multiples of 2. The resistor in the most significant bit position has a value of R, the next resistor has a value of 2R, and so on. It will be appreciated that this can be extended to 2 N , where N is the number of bits (4 in this case).
[0051] An exemplary configuration of the second stage 102 is as follows Figure 4 As shown. The second stage includes n sections. The n sections are coupled in series. In one configuration, n is equal to 3, however, it should be understood that n is not limited thereto and may be greater or less than 3. The value of n is selected to optimize the performance of the second stage.
[0052] Each of the n sections includes a third FET 301 and a fourth FET 302. The drain of the third FET 301 is coupled to the drain of the fourth FET 302 and the output 303 of the section. The gate of the third FET 301 is coupled to the gate of the fourth FET 302 and the input of the section. Each of the n sections also includes a fifth FET 304. The drain of the fifth FET 304 is coupled to the source of the third FET 301. The source of the fifth FET 304 is coupled to the first voltage level Vddfx. The gate of the fifth FET is coupled to the third voltage level Vgp. The third voltage level is provided at the third voltage input. In one configuration, the third voltage level Vgp can be in the range of 0.25V to 0.35V lower than Vddfx (the power supply voltage level).
[0053] A fourth voltage input is also provided. The fourth voltage input provides a fourth voltage at a fourth voltage level. In one configuration, the fourth voltage level is between 0.25V and 0.35V and is above ground. Figure 4 Shown as Vgn.
[0054] Each of the n sections further includes a sixth FET 305. The drain of the sixth FET 305 is coupled to the source of the fourth FET 302, and the source of the sixth FET 305 is coupled to the second voltage level Vssfx. The gate of the sixth FET 305 is coupled to the fourth voltage level.
[0055] In one configuration, the third FET 301 and the fifth FET 304 are pFETs, and the fourth FET 302 and the sixth FET 305 are nFETs.
[0056] The output of the second stage 105 is coupled to the output of the nth of the n sections. The input of the second stage is the input to the first of the n sections. The n sections of the second stage are coupled in series so that the output of one stage is the input to the next stage.
[0057] Figure 5 An example of a delay cell including a first stage 101 and a second stage is provided, wherein the first stage and the second stage are coupled in series.
[0058] The first stage 101 includes a first FET 201. A second FET 202 is also provided. The drain of the first FET is coupled to the drain of the second FET. The output 104 of the first stage 101 is coupled to the drain of the first FET 201 and the drain of the second FET 202. The gate of the first FET 201 and the gate of the second FET 202 are coupled together and coupled to the input 103. The first FET and the second FET form an inverter. The first resistor 203 is coupled to the source of the first FET 201. The first resistor 203 is coupled in series between a first voltage level Vddfx provided by a first voltage input (not shown) and the source of the first FET 201. The first resistor 203 is a variable resistor. The second resistor 204 is coupled to the source of the second FET. The second resistor 204 is coupled in series between the source of the second FET 202 and a second voltage level Vssfx. The second voltage level is provided at the second voltage input. The first FET is a pFET and the second FET is an nFET. The second stage includes n sections. The n sections are coupled in series. However, in one configuration, n is equal to 3, it should be understood that n is not limited thereto and may be greater or less than 3. The value of n is selected to optimize the performance of the second stage.
[0059] In one configuration, Vssfx may be ground or 0 V. Vddfx is a power supply voltage and is variable depending on the relevant process technology used in the fabrication of the delay cell. For example, for 6nm to 14nm processes, Vddfx may be in the range of 0.7V to 0.9V.
[0060] The second stage includes n sections. Each of the n sections includes a third FET 301 and a fourth FET 302. The drain of the third FET 301 is coupled to the drain of the fourth FET 302 and the output 303 of the section. The gate of the third FET 301 is coupled to the gate of the fourth FET 302 and the input of the section. Each of the n sections also includes a fifth FET 304. The drain of the fifth FET 304 is coupled to the source of the third FET 301. The source of the fifth FET 304 is coupled to the first voltage level Vddfx. The gate of the fifth FET is coupled to the third voltage level Vgp. The third voltage level is provided at the third voltage input. In one configuration, the third voltage level Vgp can be in the range of 0.25V to 0.35V lower than Vddfx (power supply voltage level).
[0061] A fourth voltage input is also provided. The fourth voltage input provides a fourth voltage at a fourth voltage level. In one configuration, the fourth voltage level is between 0.25V and 0.35V and is above ground. Figure 5 Shown as Vgn.
[0062] Each of the n sections further includes a sixth FET 305. The drain of the sixth FET 305 is coupled to the source of the fourth FET 302, and the source of the sixth FET 305 is coupled to the second voltage level Vssfx. The gate of the sixth FET 305 is coupled to the fourth voltage level Vgn.
[0063] In one configuration, the third FET 301 and the fifth FET 304 are pFETs, and the fourth FET 302 and the sixth FET 305 are nFETs.
[0064] In one configuration, Vssfx may be ground or 0 V. Vddfx is a power supply voltage and is variable depending on the relevant process technology used in the fabrication of the delay cell. For example, for 6nm to 14nm processes, Vddfx may be in the range of 0.7V to 0.9V.
[0065] exist Figure 5 In the configuration of , a first inverter 401 is coupled to the output of the second stage to provide a first output of the delay unit. A second inverter 402 coupled in series to the first inverter provides a second output of the delay unit. The first inverter and the second inverter are coupled between a power supply voltage Vddfx and a ground voltage Vssfx.
[0066] Figure 6 An example circuit of a delay locked loop (DLL) 500 including an N-stage delay line 501 is shown in FIG. It should be understood that Figure 6The configured DLL shown may have applications in DLL-based serializer / deserializers (SerDes), DLL-based clock multipliers, time-to-digital converters, and the like.
[0067] exist Figure 6 In the configuration, each delay stage in the N-stage delay line includes a p-bit first stage, for example, a p-bit coarse DAC (first stage) in each delay line stage and a q-bit fine current-deficient delay element (second stage) in each delay line stage. Figure 6 The first and second levels can be used Figure 2 , Figure 3 , Figure 4 and Figure 5 This is achieved by the unit configuration.
[0068] Figure 6 The input of the DLL is the input clock Clk_in. The input of the N-stage delay line is shown as Clk_in, and the output of the N-stage delay line is a phase-shifted output clock signal Phi_out having multiple phases across one clock generation cycle. The phase detector 503 is configured to sense the phase difference between the output of the N-stage delay line and the input clock Clk_in. The loop filter 502 controls the N-stage delay line according to the sensed phase difference. The first stage can be based on Figure 2 or Figure 3 Any configuration shown is implemented, where Figure 3 In the resistance ladder of the equivalent circuit, N=p.
[0069] The hybrid combination proposed herein provides lower jitter than conventional undercurrent delay cells at comparable power in comparable processes. For example, in a 7nm lithography process, at 250uA in a 10Gbps serializer, the jitter provided by the present combination is expected to be approximately 1 / 3 of that of an undercurrent delay cell at comparable power. Although a 7nm lithography process is provided as an example, it should be understood that the topology of the delay cell provided herein is applicable to other processes.
[0070] like Figure 7 As shown, a method for providing a delay cell for use in a serial link based on a delay locked loop (DLL) is also provided herein, the method comprising: providing a first stage and a second stage, wherein the output of the first stage is an input to the second stage, the first stage comprises a resistive digital-to-analog converter, and the second stage comprises a current-deficient delay cell.
[0071] Even if specific feature combinations are listed in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of various aspects. In fact, many of these features can be combined in a manner that is not specifically listed in the claims and / or not disclosed in the specification. Although each dependent claim listed below can directly depend on only one claim, the disclosure of various aspects includes the combination of each dependent claim with each other claim in the claim set. The phrase "at least one" mentioned in the list of items refers to any combination of these items, including single members. For example, "at least one of a, b or c" is intended to cover a, b, c, ab, ac, bc and abc, and any combination with multiples of the same elements (for example, aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc and ccc, or any other ordering of a, b and c).
[0072] Unless explicitly stated, any element, action or instruction used in this article should not be interpreted as critical or essential. In addition, as used in this article, the articles "a" and "an" are intended to include one or more items and can be used interchangeably with "one or more". In addition, as used in this specification, the terms "set" and "group" are intended to include one or more items (e.g., related items, unrelated items, a combination of related items and unrelated items, etc.), and can be used interchangeably with "one or more". If only one item is intended to be used, the phrase "only one" or similar language is used. In addition, as used in this article, the terms "has", "have", "having", etc. are intended to be open terms. In addition, unless otherwise explicitly stated, the word "based on" means "at least partially based on".
Claims
1. A delay unit for a serial link based on a delay locked loop (DLL), comprising: First and second level, The output of the first stage is the input to the second stage, the first stage comprises a resistive digital-to-analog converter R-DAC, and the second stage comprises a current starvation delay unit.
2. The delay unit of claim 1 , wherein the first stage comprises a first field effect transistor (FET) and a second field effect transistor (FET), and wherein the drain of the first FET is coupled to the drain of the second FET, and wherein the gate of the first FET is coupled to the gate of the second FET and the input.
3. The delay unit according to claim 2, further comprising: A first resistor is coupled in series between a first voltage level and a source of the first FET, and a second resistor is coupled in series between a source of the second FET and a second voltage level. 4 . The delay cell of claim 2 , wherein the first FET is a pFET and the second FET is an nFET.
5. The delay unit of claim 1 , wherein the second stage comprises n sections coupled in series, each section comprising: a third field effect transistor FET, and a fourth field effect transistor FET, wherein the drain of the third FET is coupled to the drain of the fourth FET and to the output of the portion, and wherein the gate of the third FET is coupled to the gate of the fourth FET and to the input of the portion.
6. The delay unit of claim 5, wherein the second stage further comprises: a fifth field effect transistor FET, wherein the drain of the fifth FET is coupled to the source of the third FET, wherein the source of the fifth FET is coupled to the first voltage level, and wherein the gate of the fifth FET is coupled to the third voltage level.
7. The delay unit of claim 6, wherein the second stage further comprises: a sixth field effect transistor FET, wherein the drain of the sixth FET is coupled to the source of the fourth FET, wherein the source of the sixth FET is coupled to the second voltage level, and wherein the gate of the sixth FET is coupled to the fourth voltage level. 8 . The delay cell of claim 7 , wherein the third FET and the fifth FET are pFETs, and the fourth FET and the sixth FET are nFETs. 9 . The delay unit of claim 5 , wherein n is greater than or equal to 3.
10. The delay cell of claim 5, wherein an output of the second stage is coupled to the output of an nth of the n sections, and the input to the second stage is coupled to the input of a first of the n sections.
11. The delay cell of claim 1, further comprising an inverter coupled to an output of the second stage. 12 . The delay unit according to claim 1 , is manufactured according to a 7 nm lithography process.
13. A method for providing a delay unit for use in a delay locked loop (DLL) based serial link, comprising: A first stage and a second stage are provided, wherein an output of the first stage is an input to the second stage, the first stage comprises a resistive digital-to-analog converter, and the second stage comprises a current starvation delay cell.
14. The method of claim 13, wherein the first stage comprises a first field effect transistor (FET) and a second field effect transistor (FET), and wherein the drain of the first FET is coupled to the drain of the second FET, and wherein the gate of the first FET is coupled to the gate of the second FET and the input.
15. The method according to claim 14, further comprising: A first resistor is coupled in series between a first voltage level and a source of the first FET, and a second resistor is coupled in series between a source of the second FET and a second voltage level.
16. The method of claim 14, wherein the first FET is a pFET and the second FET is an nFET.
17. The method of claim 13, wherein the second stage comprises n sections coupled in series, each section comprising: a third field effect transistor FET, and a fourth field effect transistor FET, wherein the drain of the third FET is coupled to the drain of the fourth FET and to the output of the portion, and wherein the gate of the third FET is coupled to the gate of the fourth FET and to the input of the portion.
18. The method of claim 17, wherein the second stage further comprises: a fifth field effect transistor FET, wherein the drain of the fifth FET is coupled to the source of the third FET, wherein the source of the fifth FET is coupled to the first voltage level, and wherein the gate of the fifth FET is coupled to the third voltage level.
19. The method of claim 18, wherein the second stage further comprises: a sixth field effect transistor FET, wherein the drain of the sixth FET is coupled to the source of the fourth FET, wherein the source of the sixth FET is coupled to the second voltage level, and wherein the gate of the sixth FET is coupled to the fourth voltage level.
20. The method of claim 19, wherein the third FET and the fifth FET are pFETs, and the fourth FET and the sixth FET are nFETs.
21. The method of claim 17, wherein n is greater than or equal to 3.
22. The method of claim 17, wherein each of the n sections is coupled in series such that the input to the second stage is the input to a first section of the n sections and the output of the second stage is the output to a last section of the n sections.
23. The method of claim 13, further comprising: An inverter is coupled to the output of the second stage.
24. A delay locked loop (DLL), comprising a plurality of delay units, wherein the delay units include: A first stage and a second stage, wherein an output of the first stage is an input to the second stage, the first stage comprises a resistive digital-to-analog converter (R-DAC), and the second stage comprises a current starvation delay cell.
25. The DLL of claim 24, wherein the first stage comprises a first field effect transistor (FET) and a second field effect transistor (FET), and wherein a drain of the first FET is coupled to a drain of the second FET, and wherein a gate of the first FET is coupled to a gate of the second FET and the input.
26. The DLL of claim 25, further comprising: A first resistor is coupled in series between a first voltage level and a source of the first FET, and a second resistor is coupled in series between a source of the second FET and a second voltage level.
27. The DLL of claim 24, wherein the second stage comprises n sections coupled in series, each section comprising: a third field effect transistor FET, and a fourth field effect transistor FET, wherein the drain of the third FET is coupled to the drain of the fourth FET and the output of the portion, and wherein the gate of the third FET is coupled to the gate of the fourth FET and the input of the portion.
28. The DLL of claim 27, wherein the second stage further comprises: a fifth FET, wherein a drain of the fifth FET is coupled to a source of the third FET, wherein the source of the fifth FET is coupled to a first voltage level, and wherein a gate of the fifth FET is coupled to a third voltage level.
29. The DLL of claim 28, wherein the second stage further comprises a sixth FET, wherein a drain of the sixth FET is coupled to a source of the fourth FET, wherein a source of the sixth FET is coupled to a second voltage level, and wherein a gate of the sixth FET is coupled to a fourth voltage level.
30. A serial link comprising the delay locked loop (DLL) according to claim 24.