Test circuit and working method for improving test coverage

Abstract

A test circuit and operating method for improving test coverage ensures both at-speed faults and stuck-at faults in high-frequency clock domain logic can be tested during chip DFT, enabling stuck-at fault testing in low-frequency logic circuits without at-speed testing, thereby improving stuck-at test coverage for the entire chip. When the chip enters at-speed test mode, the scan enable (scan_enable) controls the second clock gating circuit. After scan_enable is pulled high, scan_enable is clocked via a third register, delaying the second clock gating circuit's output by one cycle. A third AND gate disables the clock output when scan_enable is pulled low.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a test circuit for improving test coverage, and a working method of the test circuit for improving test coverage. Background Art

[0002] The purpose of testing is to detect defects and faults arising during the chip manufacturing process. The core technology of DFT (Design For Test) lies in scan path design. The fundamental principle is to transform difficult-to-test sequential circuits into easily testable combinational circuits and sequential circuits with triggers. DFT establishes corresponding fault models based on the various faults arising during chip manufacturing. The most common fault models are stuck-at (static fault) and at-speed (high-speed fault). The stuck-at model is used to detect faults caused by shorts to ground or power due to the manufacturing process, while the at-speed model is used to detect faults caused by delays during the manufacturing process that fail to meet the timing requirements for functional implementation.

[0003] For stuck-at, during the capture phase, when scan_enable is low, a single scan_clock cycle is used for sampling and capture. This allows for observation of unexpected outputs on scan_out during the load / unload phase. For at-speed, it's crucial to verify that the functional circuit's delay information meets timing requirements. During testing, the chip must operate at its highest clock frequency. During the capture phase, two high-frequency clock cycles are generated: one for the launch clock and one for the capture clock. If a fault occurs, the capture clock will sample unexpected results, which can be observed on scan_out during the load / unload phase.

[0004] When performing netlist-level DFT design, the EDA tools commonly used are Synopsys' DFT compiler or Mentor's Tessent. Both tools propose solutions for at-speed testing by inserting OCC (On Chip Controller) logic circuits.

[0005] The basic principle of the OCC circuit is to use a low-speed scan_clock provided by the ATE during the load / unload phase. During the capture phase, a functional clock generated by the on-chip PLL is selected for at-speed testing, while the low-speed scan_clock is still used for stuck-at testing. During at-speed testing, the OCC internal logic also controls the generation of a functional clock of at least 2T during the capture phase to meet the launch clock and capture clock requirements.

[0006] Chips typically have multiple clock domains, some with internal clock frequencies significantly higher than the scan clock, while others have lower frequencies. At-speed testing is designed to identify the impact of production environments on path delays, which can prevent accurate output results from being observed within the expected timeframe. Logic circuits in high-frequency clock domains are particularly susceptible. At-speed testing of low-frequency clock domains is relatively unimportant and may even increase testing costs.

[0007] To complete the testing of the above two faults, the industry usually inserts an OCC circuit to switch between the two test modes through its internal logic, such as Figure 1 shown.

[0008] (1) When the OCC circuit is in at-speed test mode: scan_mode is high and pll_bypass is low (at_speed mode).

[0009] 1) In the load_unload phase, the scan_enable signal is in a high-level state, the output of the OR gate U9 is high, the output of the OR gate U9 is connected to the S pin of the second dual selector U7, the scan_clock is output to the Y pin of the second dual selector U7 via the B pin of the second dual selector U7, and the S pin of the third dual selector U8 is connected to scan_mode. At this time, the S pin of the third dual selector U8 is high, and the Y pin of the third dual selector U8 will output the scan_clock input from the Y pin of the second dual selector U7 to the B pin of the third dual selector U8;

[0010] 2) In the capture phase, the scan_enable signal changes from high level to low level, and completes the synchronization of the scan_enable signal from the scan_clock to the function_clock clock domain through the first register U0 and the second register U1 to obtain a stable scan_enable low level state. After the cross-clock domain synchronization is completed, the scan_enable is inverted by the NOT gate U2 and output together with the Qn-1 output of the second register U1 to the first AND gate U3. At the same time, it is given together with the Qn-2 output of the second register U1 to the second AND gate U4, and combined with the first dual selector U5 To realize the control of several cycles of the function_clock clock output of the first clock gating circuit U6, the output functional clock of the first clock gating circuit U6 passes through the second dual selector U7. At this time, the S pin of the second dual selector U7 is at a low level, so it is output from the A pin of the second dual selector U7 to the Y pin of the second dual selector U7. At this time, because it is still in the scan_mode state, scan_mode is at a high level, so the Y pin of the third dual selector U8 comes from the B pin of the third dual selector U8, that is, the function_clock of several clocks passing through the first clock gating circuit U6.

[0011] (2) When the OCC circuit is in stuck-at test mode: scan_mode is high, and pll_bypass is high (stuck-at mode). At this point, the output of OR gate U9 is always high. Regardless of the load_unload phase or the capture phase, the second dual selector U7 will pass the input of its B pin to its Y pin. Because scan_mode is high, the output of the Y pin of the third dual selector U8 is always scan_clock.

[0012] For low-frequency logic in a chip, whose operating frequency is even lower than the scan_clock, there's no need to insert an OCC circuit for at-speed testing. Without any clock manipulation for this low-frequency logic, all of the low-frequency logic will not be tracked and controlled by the scan_clock in test mode. Consequently, stuck-at faults in this circuitry cannot be tested, reducing the stuck-at test coverage of the entire chip.

[0013] If the low-frequency clock is processed in the conventional way of only doing stuck-at test on the entire chip, such as Figure 2As shown, the output pin Y of the second dual-way selector U10 will always output scan_clock in scan_mode. In this way, in the capture phase of the high-frequency logic at-speed test, because scan_clock is always on, the cycle of scan_enable being pulled low cannot be controlled in the capture phase of the low-frequency logic test because there is no OCC involved. As a result, the number of scan_clock cycles is unpredictable and the tool will not be able to generate correct at-speed test stimulus. Summary of the Invention

[0014] To overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide a test circuit that improves test coverage. When performing DFT on the chip, the test circuit can ensure that both at-speed faults and stuck-at faults of high-frequency clock domain logic can be tested, while the stuck-at fault can be tested when the low-frequency logic circuit is not subjected to at-speed testing, thereby improving the stuck-at test coverage of the entire chip.

[0015] The technical solution of the present invention is: the test circuit for improving test coverage includes a third register U11, a third AND gate U12, a second clock gating circuit U13, and a fourth dual selector U14;

[0016] During a stuck-at test for static faults, the second clock gating circuit enables the fourth dual selector to obtain a clock consistent with the scan clock scan_clock. The stuck-at test mode signal pll_bypass is set high to control the second clock gating circuit to be in a transparent state. The scan mode signal scan_mode is set high, and the fourth dual selector outputs scan_clock to the Function DFFs, obtaining an expected scan_clock.

[0017] When the chip enters the at-speed test mode, the scan enable scan_enable controls the second clock gating circuit. After scan_enable is pulled high, scan_enable is beat through the third register. The second clock gating circuit outputs the clock one cycle later. When scan_enable is pulled low through the third AND gate, the clock output is shut down.

[0018] The beneficial technical effects of the present invention are as follows:

[0019] 1. This circuit structure does not affect the insertion of the OCC circuit;

[0020] 2. This circuit does not affect the output of normal functional clock;

[0021] 3. This circuit can ensure that scan_clock can be output with a delay of one cycle when scan_enable goes from low to high;

[0022] 4. For low-frequency logic circuits that do not require at-speed testing, this circuit can be inserted to improve stuck-at related coverage.

[0023] A method for operating a test circuit to improve test coverage is also provided, comprising the following steps:

[0024] (1) During the stuck-at test, the Y pin of the fourth dual selector is made to obtain a clock consistent with the scan_clock through the second clock gating circuit. The EN pin of the second clock gating circuit is controlled by the high level of the stuck-at test mode signal pll_bypass. In the stuck-at mode, the second clock gating circuit is in a transparent state. The scan_clock passes through the second clock gating circuit to the B pin of the fourth dual selector. In the test mode, the scan_mode signal is high. The fourth dual selector outputs the scan_clock to the Function DFFs to obtain the expected scan_clock.

[0025] (2) When the chip enters the at-speed test mode, scan_enable controls the SE pin of the second clock gating circuit. After scan_enable is pulled high, scan_enable is beat through the third register. The ECK pin of the second clock gating circuit outputs the clock one cycle later. When scan_enable is pulled low through the third AND gate, the clock output is shut down. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. 4 shows a structural diagram of an OCC circuit.

[0027] Figure 2 Shown is a clock selection circuit for stuck-at testing only.

[0028] Figure 3 A schematic structural diagram of a circuit according to a specific embodiment of a test circuit for improving test coverage of the present invention is shown.

[0029] Figure 4 is with Figure 3 Matching timing diagrams of each signal. DETAILED DESCRIPTION

[0030] This test circuit for improving test coverage includes a third register U11, a third AND gate U12, a second clock gating circuit U13, and a fourth dual selector U14;

[0031] During a stuck-at test for static faults, the second clock gating circuit enables the fourth dual selector to obtain a clock consistent with the scan clock scan_clock. The stuck-at test mode signal pll_bypass is set high to control the second clock gating circuit to be in a transparent state. The scan mode signal scan_mode is set high, and the fourth dual selector outputs scan_clock to the Function DFFs, obtaining an expected scan_clock.

[0032] When the chip enters the at-speed test mode, the scan enable scan_enable controls the second clock gating circuit. After scan_enable is pulled high, scan_enable is beat through the third register. The second clock gating circuit outputs the clock one cycle later. When scan_enable is pulled low through the third AND gate, the clock output is shut down.

[0033] The beneficial technical effects of the present invention are as follows:

[0034] 1. This circuit structure does not affect the insertion of the OCC circuit;

[0035] 2. This circuit does not affect the output of normal functional clock;

[0036] 3. This circuit can ensure that scan_clock can be output with a delay of one cycle when scan_enable goes from low to high;

[0037] 4. For low-frequency logic circuits that do not require at-speed testing, this circuit can be inserted to improve stuck-at related coverage.

[0038] Preferably, if Figure 3 As shown, scan_enable is connected to the D pin of the third register and serves as the input of the third AND gate together with the Q pin output of the third register. scan_clock serves as the input of the third register and is connected to the CK pin of the second clock gating circuit. The ECK pin of the second clock gating circuit is connected to the B pin of the fourth dual selector. The functional clock function_clock and scan_mode are connected to the A pin and S pin of the fourth dual selector respectively. The Y pin of the fourth dual selector is connected to Function DFFs.

[0039] application Figure 3 The waveform of the low-frequency clock domain in at-speed test mode is as follows: Figure 4 shown.

[0040] A method for operating a test circuit to improve test coverage is also provided, comprising the following steps:

[0041] (1) During the stuck-at test, the Y pin of the fourth dual selector is made to obtain a clock consistent with the scan_clock through the second clock gating circuit. The EN pin of the second clock gating circuit is controlled by the high level of the stuck-at test mode signal pll_bypass. In the stuck-at mode, the second clock gating circuit is in a transparent state. The scan_clock passes through the second clock gating circuit to the B pin of the fourth dual selector. In the test mode, the scan_mode signal is high. The fourth dual selector outputs the scan_clock to the Function DFFs to obtain the expected scan_clock.

[0042] (2) When the chip enters the at-speed test mode, scan_enable controls the SE pin of the second clock gating circuit. After scan_enable is pulled high, scan_enable is beat through the third register. The ECK pin of the second clock gating circuit outputs the clock one cycle later. When scan_enable is pulled low through the third AND gate, the clock output is shut down.

[0043] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the scope of protection of the technical solution of the present invention.

Claims

1. A test circuit for improving test coverage, characterized by: It includes a third register (U11), a third AND gate (U12), a second clock gating circuit (U13), and a fourth dual-way selector (U14); During a stuck-at test, the second clock gating circuit enables the fourth dual selector to obtain a clock consistent with the scan clock scan_clock. The stuck-at test mode signal pll_bypass is set high to control the second clock gating circuit to be in a transparent state. The scan mode signal scan_mode is set high, and the fourth dual selector outputs scan_clock to the function register Function DFFs, obtaining an expected scan_clock. When the chip enters the high-speed fault at-speed test mode, the scan enable scan_enable controls the second clock gating circuit. After scan_enable is pulled high, scan_enable is beat through the third register. The second clock gating circuit outputs the clock one cycle later. When scan_enable is pulled low through the third AND gate, the clock output is shut down.

2. The test circuit for improving test coverage according to claim 1, wherein: scan_enable is connected to the D pin of the third register and serves as the input of the third AND gate together with the Q pin output of the third register. scan_clock serves as the input of the third register and is connected to the CK pin of the second clock gating circuit. The ECK pin of the second clock gating circuit is connected to the B pin of the fourth dual selector. The functional clock function_clock and scan_mode are connected to the A pin and S pin of the fourth dual selector respectively. The Y pin of the fourth dual selector is connected to Function DFFs.

3. The operating method of a test circuit for improving test coverage according to claim 2, characterized in that: It includes the following steps: (1) During the stuck-at test, the Y pin of the fourth dual selector is made to obtain a clock consistent with the scan_clock through the second clock gating circuit. The EN pin of the second clock gating circuit is controlled by the high level of the stuck-at test mode signal pll_bypass. In the stuck-at mode, the second clock gating circuit is in a transparent state. The scan_clock passes through the second clock gating circuit to the B pin of the fourth dual selector. In the test mode, the scan_mode signal is high. The fourth dual selector outputs the scan_clock to the Function DFFs to obtain the expected scan_clock. (2) When the chip enters the at-speed test mode, scan_enable controls the SE pin of the second clock gating circuit. After scan_enable is pulled high, scan_enable is beat through the third register. The ECK pin of the second clock gating circuit outputs the clock one cycle later. When scan_enable is pulled low through the third AND gate, the clock output is shut down.

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