Storage device detecting error in power-on reset signal and method of operating same

Abstract

A storage device and an operating method thereof are disclosed. The storage device includes: a memory device; a power port receiving a first external power voltage from the host device; a power supply circuit receiving a first external power voltage from the power supply port and generating a first internal power voltage based on the first external power voltage; a monitoring circuit receiving the first external power voltage from the power supply port and generating a first power-on reset signal based on monitoring of the first external power voltage; and a storage controller configured to control the memory device. The storage controller is driven based on a first internal power voltage and a first power-on reset signal, and the monitoring circuit detects a voltage drop in the first power-on reset signal transmitted from the monitoring circuit to the storage controller and provides an error detection signal to the storage controller in response to detecting the voltage drop.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0163767 filed in the Korean Intellectual Property Office on November 22, 2023, and Korean Patent Application No. 10-2024-0026457 filed in the Korean Intellectual Property Office on February 23, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a storage device, and more particularly, to a storage device that detects an error in a power-on reset signal and an operating method thereof. Background Art

[0004] The host can control the overall operation of the storage device. The host can exchange data with the storage device and can also supply power to the storage device. In the storage device, a storage controller that controls the memory device is driven based on power from the host.

[0005] However, when an error occurs in the process of supplying power to the storage controller, the storage controller is immediately shut down. In this case, the reason for shutting down the storage controller cannot be clarified. Summary of the invention

[0006] Embodiments of the present disclosure provide a storage device for detecting an error in a power-on reset signal and an operating method thereof.

[0007] A storage device is provided herein, which includes: a memory device; a power port configured to receive a first external power voltage from a host device; a power circuit configured to receive the first external power voltage from the power port and generate a first internal power voltage based on the first external power voltage; a monitoring circuit configured to receive the first external power voltage from the power port and generate a first power-on reset signal based on monitoring the first external power voltage; and a storage controller configured to control the memory device, wherein the storage controller is driven based on the first internal power voltage and the first power-on reset signal, and wherein the monitoring circuit is further configured to detect a voltage drop in the first power-on reset signal transmitted from the monitoring circuit to the storage controller and provide an error detection signal to the storage controller in response to detecting the voltage drop, thereby enabling detection of a shutdown cause of the storage controller, and wherein the voltage drop is the shutdown cause of the storage controller.

[0008] A method performed by a storage device is also provided, wherein the storage device includes a memory device, a power port, a power circuit, a storage controller and a monitoring circuit, the method including: receiving a first external power voltage from a host device by the power port; generating a first internal power voltage based on the first external power voltage by the power circuit; generating a first power-on reset signal by the monitoring circuit based on monitoring the first external power voltage; detecting a voltage drop in the first power-on reset signal transmitted from the monitoring circuit to the storage controller by the monitoring circuit; and providing an error detection signal to the storage controller by the monitoring circuit in response to detecting the voltage drop, thereby being able to detect a shutdown cause of the storage controller, the voltage drop being the shutdown cause of the storage controller, and the error detection signal corresponding to the shutdown cause.

[0009] In addition, the present invention provides a storage device, which includes: a memory device; a power port configured to receive a first external power voltage from a host device; a communication port configured to communicate with the host device; a power circuit configured to receive the first external power voltage from the power port and generate a first internal power voltage based on the first external power voltage; a monitoring circuit configured to receive the first external power voltage from the power port and generate a first power-on reset signal based on monitoring the first external power voltage; a storage controller, wherein the storage controller is driven based on the first internal power voltage and the first power-on reset signal; and a microcontroller unit (MCU) configured to communicate with the host device by utilizing the communication port, wherein the monitoring circuit is configured to: detect a voltage drop in the first power-on reset signal sent from the monitoring circuit to the storage controller, and provide an error detection signal to the storage controller in response to detecting the voltage drop, wherein the storage controller is also configured to record error detection information based on the error detection signal, thereby enabling detection of a shutdown cause of the storage controller, and wherein the voltage drop is a shutdown cause of the storage controller, and wherein the MCU is also configured to provide the error detection information received from the storage controller to the communication port. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the attached drawings.

[0011] Figure 1 is a block diagram of a storage system according to an embodiment of the present disclosure.

[0012] Figure 2 It is shown in detail Figure 1 Diagram of the storage system.

[0013] Figure 3 is a block diagram of a storage device according to some embodiments of the present disclosure.

[0014] Figure 4 It is shown in detail Figure 3 Diagram of the monitoring circuit.

[0015] Figure 5 is a timing diagram describing monitoring signals and error detection signals according to some embodiments of the present disclosure.

[0016] Figure 6 is a table describing monitoring signals according to some embodiments of the present disclosure.

[0017] Figure 7 is a flowchart of an operating method of a storage device according to an embodiment of the present disclosure.

[0018] Figure 8 is a flowchart of an operating method of a storage device according to some embodiments of the present disclosure.

[0019] Fig. 9 is a flow chart describing a method of operation of a storage controller after a storage controller shutdown according to some embodiments of the present disclosure.

[0020] Fig.10 is a block diagram of a storage system according to some embodiments of the present disclosure.

[0021] Fig.11 is described in Fig.10 A diagram of an operating method of a storage device after a storage controller is driven again. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present disclosure will be described in detail and clearly so that those skilled in the art can easily implement the embodiments of the present disclosure.

[0023] Figure 1 is a block diagram of a storage system according to an embodiment of the present disclosure. Figure 1 , the storage system 10 may include a host device 11 and a storage device 100. The storage system 10 may refer to a computing system configured to process various information, such as a personal computer (PC), a notebook computer, a laptop, a server, a workstation, a tablet PC, a smart phone, a digital camera, and a black box.

[0024] The host device 11 may provide an external power voltage V_ext to the storage device 100. The external power voltage V_ext may refer to at least one of power voltages for driving the storage device 100. The host device 11 may exchange data with the storage device 100. For example, the host device 11 may provide the storage device 100 with data to be stored in the storage device 100, or data existing in the storage device 100 may be provided from the storage device 100 to the host device 11.

[0025] The storage device 100 may include a power circuit 110 , a monitoring circuit 120 , a storage controller 130 , and a non-volatile memory device 140 .

[0026] The power supply circuit 110 may generate an internal power voltage based on the external power voltage V_ext received from the host device 11. The internal power voltage may refer to at least one of the power voltages used to drive the storage controller 130. For example, the power supply circuit 110 may generate an internal power voltage having a second power voltage level by converting an external power voltage V_ext having a first power voltage level. The second power voltage level may be different from the first power voltage level. The power supply circuit 110 may provide the internal power voltage to the storage controller 130.

[0027] The monitoring circuit 120 may generate a power on reset signal based on monitoring of the external power voltage V_ext. The power on reset signal may refer to a signal that allows the storage controller 130 to be driven based on the internal power voltage.

[0028] In some embodiments, when the power voltage level of the external power voltage V_ext exceeds the reference voltage level, the monitoring circuit 120 may generate a power-on reset signal having a first logic value. The reference voltage level may be predetermined based on the voltage levels required to drive the storage controller 130. Conversely, when the power voltage level of the external power voltage V_ext does not exceed the reference voltage level, the monitoring circuit 120 may generate a power-on reset signal having a second logic value. Each of the first logic value and the second logic value may be one of "0" and "1", and the first logic value and the second logic value may be different from each other. The signal having a logic value of "0" may be a low level signal, and the signal having a logic value of "1" may be a high level signal.

[0029] The storage controller 130 may be driven based on the internal power voltage and the power-on reset signal.

[0030] For example, the storage controller 130 may be powered on when the internal power voltage is received from the power supply circuit 110 and a power-on reset signal having a first logic value is received from the monitoring circuit 120. As another example, even if the internal power voltage is received from the power supply circuit 110, when a power-on reset signal having a second logic value is received from the monitoring circuit 120, the storage controller 130 may not be powered on or may be powered off when already powered on.

[0031] The nonvolatile memory device 140 may store data. The nonvolatile memory device 140 may operate under the control of the storage controller 130. For example, the storage controller 130 may store data in the nonvolatile memory device 140, or may read data stored in the nonvolatile memory device 140.

[0032] In some embodiments, the nonvolatile memory device 140 may be a NAND flash memory device, but the present disclosure is not limited thereto. For example, the nonvolatile memory device 140 may be one of various storage devices that can retain data stored therein even when power is turned off, such as a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (RRAM), and a ferroelectric random access memory (FRAM).

[0033] The monitoring circuit 120 may detect a voltage drop in a power-on reset signal transmitted from the monitoring circuit 120 to the storage controller 130. Even if a power-on reset signal having a first logic value is output from the monitoring circuit 120, the power-on reset signal transmitted to the storage controller 130 may have a second logic value. For example, even if the monitoring circuit 120 outputs a power-on reset signal of a high level, an error (i.e., a voltage drop) may occur in which the storage controller 130 receives a power-on reset signal having a low level. The monitoring circuit 120 is configured to allow detection of a shutdown cause of the storage controller 130. For example, a voltage drop may be a shutdown cause of the storage controller.

[0034] In some embodiments, a voltage drop in the power-on reset signal may be caused by at least one of interference from adjacent electronic components, high temperature, and physical shock on a transmission line through which the power-on reset signal is transmitted from the monitoring circuit 120 to the storage controller 130 .

[0035] The monitoring circuit 120 may determine whether a voltage drop occurs in the power-on reset signal by comparing an electrical signal of an output terminal of the monitoring circuit 120 through which the power-on reset signal is output with an electrical signal of an input terminal of the storage controller 130 through which the power-on reset signal is input. The first electrical signal may correspond to the power-on reset signal of the output terminal of the monitoring circuit 120. The second electrical signal may correspond to the power-on reset signal of the input terminal of the storage controller 130.

[0036] In some embodiments, the monitoring circuit 120 may determine whether the first electrical signal is the same as the second electrical signal. For example, the monitoring circuit 120 may generate a monitoring signal having a fifth logic value based on determining that the third logic value of the first electrical signal is the same as the fourth logic value of the second electrical signal. Conversely, the monitoring circuit 120 may generate a monitoring signal having a sixth logic value based on determining that the third logic value is different from the fourth logic value. In an embodiment, each of the third to sixth logic values ​​may be one of "0" and "1", and the fifth and sixth logic values ​​may be different from each other.

[0037] The monitoring circuit 120 may provide an error detection signal to the storage controller 130 in response to detecting a voltage drop in the power on reset signal. The error detection signal may indicate whether an error occurs in the power on reset signal.

[0038] For example, the monitoring circuit 120 may generate an error detection signal having a seventh logic value based on determining that a voltage drop occurs in the power-on reset signal. Conversely, the monitoring circuit 120 may generate an error detection signal having an eighth logic value based on determining that a voltage drop does not occur in the power-on reset signal. Each of the seventh logic value and the eighth logic value may be one of "0" and "1", and the seventh logic value and the eighth logic value may be different from each other.

[0039] When the storage controller 130 is driven again by the internal power voltage and the power-on reset signal after being shut down by the voltage drop in the power-on reset signal, the storage controller 130 may record error detection information based on the error detection signal received from the monitoring circuit 120. The error detection information may refer to information corresponding to the occurrence of an error in the power-on reset signal. Therefore, the error detection information may indicate that the shutdown cause of the storage controller 130 is the voltage drop in the power-on reset signal. Fig. 9 Describe this in detail.

[0040] When a voltage drop occurs in a power-on reset signal, a conventional storage device may be shut down in a state where any information about the voltage drop cannot be recorded.

[0041] The storage device according to the present disclosure may provide an error detection signal to the storage controller 130 in response to the monitoring circuit 120 detecting a voltage drop in the power-on reset signal provided to the storage controller 130. Therefore, the storage device 100 may record error detection information corresponding to the voltage drop in the power-on reset signal. In addition, the storage device 100 may provide the error detection information to the host device 11 upon request, or the storage controller 130 may debug the error based on the error detection information.

[0042] Figure 2 It is shown in detail Figure 1 FIG. 10 is a diagram of a storage system 10. Figure 2 , the host device 11 of the storage system 10 may include a communication port CP and a power port PP, and the storage device 100 of the storage system 10 may include a communication port CP, a power port PP, a power circuit 110, a monitoring circuit 120, a storage controller 130 and a non-volatile memory device 140.

[0043] The host device 11 and the storage device 100 can communicate with each other through the communication port CP. For example, the host device 11 can exchange data with the storage controller 130 through the communication port CP. For example, the communication port CP can use an in-band channel. The communication port CP can be a Peripheral Component Interconnect Express (PCIe) port.

[0044] The host device 11 may provide the external power voltage V_ext to the storage device 100 through the power port PP. The power port PP of the storage device 100 may receive the external power voltage V_ext from the host device 11. For example, the power port PP may use an out-of-band channel.

[0045] The power circuit 110 may provide the storage controller 130 with an internal power voltage V_int generated based on the external power voltage V_ext.

[0046] The monitoring circuit 120 may include a comparator 121 , a logic circuit 122 , and a state machine 123 .

[0047] The comparator 121 may receive an external power voltage V_ext from the power port PP. The comparator 121 may generate a power on reset signal POR based on monitoring of the external power voltage V_ext.

[0048] In some embodiments, the comparator 121 may generate a power on reset signal POR having a first logic value based on determining that the power voltage level of the external power voltage V_ext exceeds the reference voltage level.

[0049] The logic circuit 122 may detect a voltage drop in the power on reset signal POR transmitted from the comparator 121 to the storage controller 130 .

[0050] In some embodiments, the logic circuit 122 may determine whether a voltage drop occurs in the power on reset signal POR based on a comparison operation of the power on reset signal of the output terminal of the comparator 121 and the power on reset signal of the input terminal of the storage controller 130 .

[0051] For example, when the logic circuit 122 detects a voltage drop in the power-on reset signal POR, the logic circuit 122 may generate a monitoring signal having a sixth logic value. Figure 4 and Figure 6 Describe this in detail.

[0052] The state machine 123 may generate an error detection signal ERR in response to detecting a voltage drop in the power-on reset signal POR. For example, the state machine 123 may provide the error detection signal ERR having a seventh logic value to the storage controller 130 based on the monitoring signal having a sixth logic value. Conversely, the state machine 123 may provide the error detection signal ERR having an eighth logic value to the storage controller 130 based on the monitoring signal having a fifth logic value. Each of the seventh logic value and the eighth logic value may be one of "0" and "1", and the seventh logic value and the eighth logic value may be different from each other.

[0053] Then, even if the logic value of the monitoring signal changes from the sixth logic value to the fifth logic value (for example, even if there is no longer an error in the power-on reset signal POR), the state machine 123 may continuously provide the error detection signal ERR having the seventh logic value to the storage controller 130 until a separate signal is received from the storage controller 130. Figure 4 and Figure 5 Describe this in detail.

[0054] The storage controller 130 may be driven based on the internal power voltage V_int and the power on reset signal POR. The storage controller 130 may communicate with the nonvolatile memory device 140.

[0055] Figure 3 is a block diagram of a storage device according to some embodiments of the present disclosure. Figure 2 and Figure 3 The storage device 100 may include a power port PP, a power circuit 110 , a monitoring circuit 120 , and a storage controller 130 .

[0056] The power port PP can be Figure 2 The host device 11 receives the external power voltage V_ext. The power circuit 110 may receive the external power voltage V_ext from the power port PP and may generate an internal power voltage V_int based on the external power voltage V_ext.

[0057] The monitoring circuit 120 may include a comparator 121, a logic circuit 122, and a state machine 123. The comparator 121 may provide a power-on reset signal POR to the storage controller 130 based on monitoring of the external power voltage V_ext. The logic circuit 122 may detect a voltage drop in the power-on reset signal POR to generate a monitoring signal. The state machine 123 may generate an error detection signal ERR based on the monitoring signal and may provide the error detection signal ERR to the storage controller 130.

[0058] The storage controller 130 can Figure 2 The storage controller 130 communicates with the host device 11 through the communication port CP. The storage controller 130 may communicate with the nonvolatile memory device 140 to control the nonvolatile memory device 140.

[0059] Hereinafter, an operating method of the storage device 100 according to some embodiments of the present disclosure will be described in detail.

[0060] In the first operation ①, the power port PP may provide the external power voltage V_ext to each of the power circuit 110 and the monitoring circuit 120 .

[0061] In the second operation ②, the power circuit 110 may provide the internal power voltage V_int to the storage controller 130 .

[0062] In some embodiments, based on the conversion of the external power voltage V_ext, the power circuit 110 may generate an internal power voltage V_int including at least one of driving voltages required to drive the storage controller 130 .

[0063] In the third operation ③, the comparator 121 of the monitoring circuit 120 may provide a power-on reset signal POR to the storage controller 130 .

[0064] In some embodiments, based on determining that the power voltage level of the external power voltage V_ext exceeds the reference voltage level, the comparator 121 may generate a power on reset signal POR having a first logic value to be output to the storage controller 130 .

[0065] In the fourth operation ④, the logic circuit 122 of the monitoring circuit 120 may detect a voltage drop in the power-on reset signal POR.

[0066] In some embodiments, the logic circuit 122 may determine whether a voltage drop has occurred in the power on reset signal POR by comparing the power on reset signal of the output terminal of the comparator 121 with the power on reset signal of the input terminal of the storage controller 130 .

[0067] In the fifth operation ⑤, the state machine 123 may provide the error detection signal ERR to the storage controller 130 .

[0068] In some embodiments, the state machine 123 may generate the error detection signal ERR having a seventh logic value in response to detecting a voltage drop in the power on reset signal POR.

[0069] Figure 4 It is shown in detail Figure 3 The monitoring circuit diagram is shown in Figure 1. Figure 3 and Figure 4 , the monitoring circuit 120 may include a comparator 121 , a logic circuit 122 , and a state machine 123 .

[0070] The comparator 121 may receive an external power voltage V_ext and a reference voltage V_ref. The comparator 121 may generate a power on reset signal POR based on a comparison operation of a power voltage level of the external power voltage V_ext and a reference voltage level of the reference voltage V_ref.

[0071] The comparator 121 can Figure 3 The power port PP of the host device 11 receives the external power voltage V_ext from the host device 11. The comparator 121 may receive the reference voltage V_ref from a reference voltage generating device (not shown). The reference voltage generating device may be included in Figure 2The storage device 100 may generate a reference voltage V_ref based on an external power voltage V_ext received through the power port PP.

[0072] In some embodiments, when the power voltage level exceeds the reference voltage level, the comparator 121 may generate a power-on reset signal POR having a first logic value. Conversely, when the power voltage level does not exceed the reference voltage level, the comparator 121 may generate a power-on reset signal POR having a second logic value.

[0073] The comparator 121 may output a power-on reset signal POR to an output terminal OT.

[0074] The logic circuit 122 may receive the first electrical signal ES1 from the output terminal OT of the comparator 121. The first electrical signal ES1 corresponding to the power-on reset signal POR may refer to the power-on reset signal POR at the output terminal OT.

[0075] The logic circuit 122 may receive the second electrical signal ES2 from the input terminal IT of the storage controller 130. The input terminal IT may refer to a terminal through which the storage controller 130 receives the power-on reset signal POR output from the comparator 121. The second electrical signal ES2 corresponding to the power-on reset signal POR may refer to the power-on reset signal POR at the input terminal IT.

[0076] The second electrical signal ES2 may be different from the first electrical signal ES1. For example, the second voltage level of the second electrical signal ES2 may be lower than the first voltage level of the first electrical signal ES1. That is, the first voltage level may be a high level and the second voltage level may be a low level.

[0077] In some embodiments, the difference between the first electrical signal ES1 and the second electrical signal ES2 (i.e., a voltage drop in the power-on reset signal POR) may be caused by at least one of interference from adjacent electronic components, high temperature, and physical impact on the transmission line between the output terminal OT and the input terminal IT.

[0078] The logic circuit 122 may generate the monitor signal MS based on a comparison operation of the first electrical signal ES1 and the second electrical signal ES2 .

[0079] In some embodiments, the logic circuit 122 may determine whether the first electrical signal ES1 is the same as the second electrical signal ES2. The logic circuit 122 may generate a monitoring signal MS having a fifth logic value based on determining that the first electrical signal ES1 is the same as the second electrical signal ES2. Conversely, the logic circuit 122 may generate a monitoring signal MS having a sixth logic value based on determining that the first electrical signal ES1 is different from the second electrical signal ES2.

[0080] In some embodiments, the logic circuit 122 may be a NAND gate. Specifically, when the third logic value of the first electrical signal ES1 is "1" and the fourth logic value of the second electrical signal ES2 is "0", the NAND gate may generate the monitoring signal MS having a sixth logic value "1".

[0081] The logic circuit 122 may provide the monitoring signal MS to the state machine 123 .

[0082] The state machine 123 may receive the monitoring signal MS from the logic circuit 122 .

[0083] In some embodiments, the state machine 123 may refer to one of a first state S1 and a second state S2. For example, the first state S1 may indicate a normal state (i.e., no error occurs in the power-on reset signal POR). The second state S2 may indicate an error state (i.e., an error occurs in the power-on reset signal POR).

[0084] In detail, in the first state S1, the state machine 123 may generate the error detection signal ERR having an eighth logic value. In contrast, in the second state S2, the state machine 123 may generate the error detection signal ERR having a seventh logic value.

[0085] In response to the monitor signal MS indicating the sixth logic value, the state machine 123 may change state to indicate the second state S2 switched from the first state S1. In other words, based on detecting a voltage drop in the power-on reset signal POR, the state machine 123 may indicate the second state S2 (ie, an error state).

[0086] The state machine 123 may indicate the second state S2 (i.e., may output the error detection signal ERR having the seventh logic value) until a state reset signal is received from the storage controller 130. The state reset signal may refer to a signal for controlling the state machine 123 so that the state machine 123 changes with the first state S1 indicating switching from the second state S2.

[0087] In other words, after the storage controller 130 is shut down by the voltage drop in the power-on reset signal POR, when the storage controller 130 is powered on again by the internal power voltage and the power-on reset signal POR in which no error occurs, the state machine 123 continues to provide the error detection signal ERR having the seventh logic value to the storage controller 130. Therefore, based on the error detection signal ERR, the storage controller 130 can know that the shutdown is caused by the voltage drop in the power-on reset signal POR.

[0088] Figure 5 is a timing diagram describing monitoring signals and error detection signals according to some embodiments of the present disclosure. Figure 4 and Figure 5The monitoring signal MS and the error detection signal ERR are described based on the external power voltage V_ext, the reference voltage V_ref, the first electrical signal ES1, and the second electrical signal ES2. Figure 5 , the horizontal axis represents time and the vertical axis represents voltage level.

[0089] At the first time point t1, the external power voltage V_ext received from the power port may exceed the reference voltage V_ref. Figure 5 In FIG. 1 , the straight line represents the change of the external power voltage V_ext over time, but the present disclosure is not limited thereto.

[0090] The comparator may output a low-level power-on reset signal before the external power voltage V_ext exceeds the reference voltage V_ref, and may output a high-level power-on reset signal from a first time point t1 when the external power voltage V_ext exceeds the reference voltage V_ref.

[0091] The first electrical signal ES1 may have a low level before the first time point t1 and may have a high level after the first time point t1. The first electrical signal ES1 corresponding to a power-on reset signal of an output terminal of the comparator may be the same as an output signal of the comparator.

[0092] The second electrical signal ES2 may have a low level before the first time point t1, may have a high level from the first time point t1 to the second time point t2, and may have a low level during a time period in which an error occurs after the second time point t2. The time period in which an error occurs may refer to a time period in which a voltage drop (i.e., an error) occurs in the power-on reset signal sent from the comparator to the storage controller. At the second time point t2, the storage controller may be shut down.

[0093] Since the first and second electrical signals ES1 and ES2 are identical before the second time point t2, the monitoring signal MS may have a low level. However, starting from the second time point t2 when the first and second electrical signals ES1 and ES2 are different, the monitoring signal MS may have a high level.

[0094] The error detection signal ERR may maintain a low level and then may have a high level starting from a second time point t2 when the monitor signal MS transitions to a high level.

[0095] After the storage controller is shut down at the second time point t2, the storage controller may be powered on again based on the external power voltage V_ext received from the power port. In other words, the storage controller may be driven again based on the internal power voltage and the power-on reset signal (where no error occurs).

[0096] At the third time point t3, the storage controller may be in a state of being driven again, and the external power voltage V_ext may exceed the reference voltage V_ref. Each of the first electrical signal ES1 and the second electrical signal ES2 may have a high level. Because the first electrical signal ES1 and the second electrical signal ES2 have the same logic value, that is, a high level, the monitoring signal MS may have a low level. However, the error detection signal ERR may have a high level until the state machine receives a state reset signal from the storage controller.

[0097] The re-driven storage controller may receive the error detection signal ERR having a high level.

[0098] Figure 6 is a table describing monitoring signals according to some embodiments of the present disclosure. Figure 4 and Figure 6 The operation of the logic circuit that generates the monitor signal MS based on the first electrical signal ES1 and the second electrical signal ES2 is described.

[0099] For ease of description, an example is provided assuming that the first logic value of the power-on reset signal output from the comparator and the sixth logic value of the monitoring signal MS are "0" and the second logic value of the power-on reset signal output from the comparator and the fifth logic value of the monitoring signal MS are "1".

[0100] The logic circuit may detect a voltage drop in the power-on reset signal based on a comparison operation of the first electrical signal ES1 and the second electrical signal ES2. The logic circuit may generate a monitor signal MS according to whether the voltage drop occurs.

[0101] When the third logic value of the first electrical signal ES1 is “0”, the logic circuit may generate the monitoring signal MS having a logic value of “0” regardless of the fourth logic value of the second electrical signal ES2 . That is, the logic circuit may determine that a voltage drop has not occurred in the power-on reset signal.

[0102] When the third logic value of the first electrical signal ES1 is “1” and the fourth logic value of the second electrical signal ES2 is “1”, the logic circuit may generate the monitoring signal MS having a logic value of “0”. That is, the logic circuit may determine that a voltage drop has not occurred in the power-on reset signal.

[0103] When the third logic value of the first electrical signal ES1 is “1” and the fourth logic value of the second electrical signal ES2 is “0”, the logic circuit may generate a monitoring signal MS having a logic value of “1”. That is, the logic circuit may determine that a voltage drop has occurred in the power-on reset signal transmitted from the comparator to the storage controller.

[0104] Figure 6According to some embodiments, only the relationship between the input signals ES1 and ES2 and the output signal MS is shown by using a truth table, but the present disclosure is not limited thereto. The logic circuit may be a circuit designed to detect a voltage drop in a power-on reset signal. For example, the logic circuit may be a NAND gate.

[0105] Figure 7 is a flowchart of an operating method of a storage device according to an embodiment of the present disclosure. Figure 7 describe Figure 3 The storage device may include a power port, a power circuit, a monitoring circuit, and a storage controller. The power port, the power circuit, the monitoring circuit, and the storage controller may correspond to Figure 3 The power port PP, the power circuit 110, the monitoring circuit 120 and the storage controller 130.

[0106] In operation S110 , the power port may receive a first external power voltage from a host device.

[0107] In operation S120 , the power supply circuit may generate a first internal power voltage based on the first external power voltage.

[0108] In operation S130 , the monitoring circuit may generate a first power on reset signal POR based on monitoring of the first external power voltage.

[0109] In some embodiments, operation S130 may include determining, by the monitoring circuit, whether the first power voltage level of the first external power voltage exceeds a reference voltage level, and generating, by the monitoring circuit, a first power-on reset signal having a first logic value based on determining that the first power voltage level exceeds the reference voltage level. In this case, the storage controller may be powered on based on the first internal power voltage and the first power-on reset signal.

[0110] In some embodiments, operation S130 may include determining, by the monitoring circuit, whether the first power voltage level of the first external power voltage exceeds a reference voltage level, and generating, by the monitoring circuit, a first power-on reset signal having a second logic value based on determining that the first power voltage level does not exceed the reference voltage level. In this case, even if the internal power voltage is received, the storage controller is not powered on because the first power-on reset signal has the second logic value.

[0111] In operation S140 , the monitoring circuit may detect a voltage drop in the first power on reset signal POR.

[0112] In some embodiments, operation S140 may include: receiving a first electrical signal by the monitoring circuit via an output terminal of the monitoring circuit; receiving a second electrical signal by the monitoring circuit via an input terminal of the storage controller; and detecting a voltage drop in the first power-on reset signal POR by the monitoring circuit based on a comparison operation between the first electrical signal and the second electrical signal.

[0113] For example, the output terminal of the monitoring circuit may correspond to Figure 4 The first electrical signal may correspond to the first power-on reset signal of the output terminal of the monitoring circuit. In addition, the input terminal of the storage controller as a terminal receiving the first power-on reset signal may correspond to Figure 4 The second electrical signal may correspond to the first power-on reset signal of the input terminal of the storage controller 130. The second electrical signal may be different from the first electrical signal due to various reasons.

[0114] In some embodiments, the step of detecting a voltage drop in the first power-on reset signal POR by a monitoring circuit based on a comparison operation of the first electrical signal and the second electrical signal may include: determining by the monitoring circuit whether a first logic value of the first electrical signal is the same as a second logic value of the second electrical signal; and generating a monitoring signal having a sixth logic value based on determining that the first logic value and the second logic value are different.

[0115] For example, the monitoring signal having the sixth logic value may correspond to the occurrence of a voltage drop in the first power-on reset signal.

[0116] In some embodiments, the difference between the first electrical signal and the second electrical signal (i.e., a voltage drop in the first power-on reset signal POR) may be caused by at least one of interference from adjacent electronic components, high temperature, and physical impact on the transmission line through which the first power-on reset signal POR is transmitted from the monitoring circuit to the storage controller.

[0117] In detail, physical shock may be applied to the transmission line through impurities in the storage device, the transmission line may be exposed to high temperature depending on changes in the internal temperature or external temperature of the storage device, or electrical interference may be caused to the transmission line by any other electronic component adjacent to the transmission line in the storage device (for example, any other input / output line).

[0118] In operation S150 , the monitoring circuit may provide an error detection signal ERR to the storage controller in response to detecting a voltage drop in the first power on reset signal POR.

[0119] In some embodiments, operation S150 may include: generating, by the monitoring circuit, an error detection signal ERR having a seventh logic value in response to the monitoring signal having a sixth logic value; and providing, by the monitoring circuit, the error detection signal ERR having the seventh logic value to the storage controller until a state reset signal is received from the storage controller.

[0120] For example, when the monitoring circuit starts to output the error detection signal ERR having the seventh logic value in response to the monitoring signal having the sixth logic value, the monitoring circuit may output the error detection signal ERR having the seventh logic value to the storage controller regardless of the monitoring signal until a state reset signal is received from the storage controller. Fig. 9 Describe this in detail.

[0121] Figure 8 is a flowchart of an operation method of a storage device according to some embodiments of the present disclosure. Figure 8 Describe in detail Figure 3 An operating method of the storage device 100 is disclosed.

[0122] In operation S210 , the storage device may receive a first external power voltage from a host device through a power port.

[0123] In operation S230, the storage device may determine whether the first power voltage level of the first external power voltage exceeds the reference voltage level of the reference voltage. The storage device may perform operation S231 based on determining that the first power voltage level does not exceed the reference voltage level. The storage device may perform operation S232 based on determining that the first power voltage level exceeds the reference voltage level.

[0124] In operation S231, the storage device may generate a first power on reset signal POR having a low level in response to determining that the first power voltage level does not exceed the reference voltage level. Next, the storage device may perform operation S210 again.

[0125] In operation S232 , the storage device may generate a first power on reset signal PodR having a high level in response to determining that the first power voltage level exceeds the reference voltage level.

[0126] In operation S250, the logic circuit 122 may determine whether the first electrical signal ES1 is identical to the second electrical signal ES2. The storage device may perform operation S251 based on determining that the first electrical signal ES1 is identical to the second electrical signal ES2. The storage device may perform operation S252 based on determining that the first electrical signal ES1 is different from the second electrical signal ES2.

[0127] In operation S251 , the storage device may provide an error detection signal ERR having a low level to a storage controller.

[0128] In operation S252 , the storage device may provide the error detection signal ERR having a high level to the storage controller.

[0129] Fig. 9 is a flowchart describing a method of operating a storage controller after the storage controller is shut down according to some embodiments of the present disclosure. Fig. 9 The operation of the storage controller performed after the storage controller is shut down by the voltage drop of the first power-on reset signal POR is described. The storage controller may correspond to Figure 3 A storage controller 130 is provided.

[0130] After the storage controller is shut down, the power port may receive a second external power voltage from the host device.

[0131] The power supply circuit may generate a second internal power voltage based on the second external power voltage and may provide the second internal power voltage to the storage controller.

[0132] The monitoring circuit may generate a second power on reset signal POR based on monitoring of the second external power voltage and may provide the second power on reset signal POR to the storage controller.

[0133] For ease of description, the second external power voltage, the second internal power voltage and the second power-on reset signal POR are signals of the same type as the above-mentioned external power voltage, internal power voltage and power-on reset signal, and are defined to be distinguished from the first external power voltage, the first internal power voltage and the first power-on reset signal based on the signal generation time.

[0134] In operation S310, the storage controller may be powered on again (or may be driven again) based on the second internal power voltage and the second power on reset signal POR. In detail, the storage controller may be powered on based on the second internal power voltage in response to the second power on reset signal POR having a first logic value.

[0135] In operation S320, the storage controller may receive an error detection signal ERR from the monitoring circuit. In this case, the error detection signal ERR corresponding to the error occurrence of the first power on reset signal may have a high level.

[0136] In operation S330, the storage controller may record error detection information based on the error detection signal ERR. The error detection information may indicate that an error occurs in a process in which the first power on reset signal is provided to the storage controller.

[0137] In some embodiments, the storage controller may store the error detection information in a read-only memory device (eg, ROM) in the storage controller.

[0138] In some embodiments, the storage controller may provide the recorded error detection information to the host device upon request. Figure 2 Communication port CP.

[0139] In some embodiments, as another example, the storage controller may further include a debugging device. The storage controller may record error detection information in the debugging device. The debugging device may be implemented by firmware that executes a debugging algorithm that debugs errors caused when power is supplied to the storage device.

[0140] In some embodiments, the storage device may provide the recorded error detection information to a microcontroller unit (MCU). The MCU may provide the error detection information to a host. Fig.10 and Fig.11 Describe this in detail.

[0141] Fig.10 is a block diagram of a storage system according to some embodiments of the present disclosure. Fig.10 FIG. 2 shows a storage system 20 further including a microcontroller unit (MCU). Fig.10 , the storage system 20 may include a host device 21 and a storage device 200 .

[0142] The host device 21 may include a first communication port CP1, a second communication port CP2, and a power port PP. The host device 21, the first communication port CP1, and the power port PP may correspond to Figure 2 The host device 11, the communication port CP and the power port PP.

[0143] The storage device 200 may include a first communication port CP1, a second communication port CP2, a power port PP, a power circuit 210, a monitoring circuit 220, a storage controller 230, an MCU 235, and a non-volatile memory device 240. The first communication port CP1, the power port PP, the power circuit 210, the monitoring circuit 220, the storage controller 230, and the non-volatile memory device 240 may correspond to the communication port CP, the power port PP, the power circuit 110, the monitoring circuit 120, the storage controller 130, and the non-volatile memory device 140.

[0144] The storage controller 230 and the host device 21 may communicate through the first communication port CP1. For example, the storage controller 230 may exchange data with the host device 21.

[0145] In some embodiments, the first communication port CP1 may use an in-band channel. For example, the first communication port CP1 may be a PCIe port.

[0146] The MCU 235 and the host device 21 may communicate through the second communication port CP2. For example, the MCU 235 may provide error detection information to the second communication port CP2.

[0147] In some embodiments, the second communication port CP2 may use an out-of-band channel. For example, the second communication port CP2 may be a system management bus (SMBUS) port.

[0148] The power circuit 210 may generate an internal power voltage V_int based on the external power voltage V_ext received from the power port PP and may provide the internal power voltage V_int to the storage controller 230 .

[0149] The monitoring circuit 220 may generate a power on reset signal POR based on monitoring of the external power voltage V_ext and may provide the power on reset signal POR to the storage controller 230. The monitoring circuit 220 may detect a voltage drop of the power on reset signal POR and may provide an error detection signal ERR to the storage controller 230.

[0150] The storage controller 230 may be powered off based on a voltage drop of the power on reset signal POR, and may then be driven again by the internal power voltage and the power on reset signal being supplied again.

[0151] The storage controller 230 that is driven again may receive the error detection signal ERR from the monitoring circuit 220 .

[0152] The storage controller 230 may record error detection information in response to the error detection signal ERR having a high level.

[0153] The storage controller 230 may provide the recorded error detection information to the MCU 235 .

[0154] The MCU 235 may receive the error detection information from the storage controller 230. The MCU 235 may provide the error detection information to the host device 21 through the second communication port CP2.

[0155] Fig.11 is described in Fig.10 FIG. 1 is a diagram showing an operation method of a storage device after the storage controller is driven again. Fig.10 and Fig.11 The storage device 200 may include a power port PP, a first communication port CP1, a second communication port CP2, a power circuit 210, a monitoring circuit 220, a storage controller 230, and an MCU 235. Fig.10 Descriptions provided are not repeated when redundant.

[0156] Hereinafter, an operating method of the storage device 200 according to some embodiments of the present disclosure will be described in detail.

[0157] In the first operation ①, the storage controller 230 may be powered on again. That is, the storage controller may be shut down by a voltage drop (ie, an error) in a power-on reset signal and may be powered on again based on an internal power voltage and a power-on reset signal.

[0158] In the second operation ②, the storage controller 230 may receive a high-level error detection signal ERR from the monitoring circuit 220 .

[0159] In the third operation ③, the storage controller 230 may record error detection information in response to the error detection signal ERR having a high level.

[0160] In the fourth operation ④, the storage controller 230 may provide the recorded error detection information to the MCU 235. Therefore, the reason why the storage controller is shut down may be known.

[0161] In the fifth operation ⑤, the MCU 235 may provide error detection information to the second communication port CP2.

[0162] In detail, the MCU 235 may receive the error detection information from the storage controller 230. The MCU 235 may provide the error detection information to the host device through the second communication port CP2 according to a request of the host device.

[0163] According to an embodiment of the present disclosure, a storage device for detecting an error in a power-on reset signal and an operating method thereof are provided.

[0164] In addition, when an error occurs in a power-on reset signal that controls power supply to a storage controller, even if the storage controller is shut down, a notification indicating that an error has occurred in the power-on reset signal can be provided to the storage controller from outside the storage controller. Thus, a storage device capable of detecting an error in a power-on reset signal is provided.

[0165] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A storage device, comprising: Memory device; a power port configured to receive a first external power voltage from a host device; A power supply circuit configured as: receiving the first external power voltage from the power port, and generating a first internal power voltage based on the first external power voltage; A monitoring circuit is configured to: receiving the first external power voltage from the power port, and generating a first power-on reset signal based on monitoring the first external power voltage; as well as a storage controller configured to control the memory device, wherein the storage controller is driven based on the first internal power voltage and the first power-on reset signal, and Wherein, the monitoring circuit is further configured as: detecting a voltage drop in the first power-on reset signal transmitted from the monitoring circuit to the storage controller, and In response to detecting the voltage drop, an error detection signal is provided to the storage controller, thereby enabling detection of a shutdown cause of the storage controller, wherein the voltage drop is the shutdown cause of the storage controller.

2. The storage device according to claim 1, wherein: The monitoring circuit comprises: comparators, which are configured as: determining whether a first power voltage level of the first external power voltage exceeds a reference voltage level, generating the first power-on reset signal having a first logic value based on determining that the first power voltage level exceeds the reference voltage level, and generating the first power on reset signal having a second logic value different from the first logic value based on determining that the first power voltage level does not exceed the reference voltage level; and A logic circuit configured to: receiving a first electrical signal corresponding to the first power-on reset signal through an output terminal of the comparator, receiving a second electrical signal corresponding to the first power-on reset signal through an input terminal of the storage controller, and The voltage drop is detected based on a comparison operation of the first electrical signal and the second electrical signal.

3. The storage device according to claim 2, wherein: The logic circuit is further configured to: determining whether a third logic value of the first electrical signal is the same as a fourth logic value of the second electrical signal; outputting a monitoring signal having a fifth logic value based on determining that the third logic value is the same as the fourth logic value; and Based on determining that the third logic value is different from the fourth logic value, the monitor signal having a sixth logic value different from the fifth logic value is output.

4. The storage device according to claim 2, wherein: The logic circuit is a NAND gate.

5. The storage device according to claim 2, wherein: The monitoring circuit also includes a state machine configured to provide the error detection signal having a seventh logic value to the storage controller in response to the logic circuit detecting the voltage drop until a state reset signal is received from the storage controller.

6. The storage device according to claim 1, wherein: The monitoring circuit is further configured to: providing the error detection signal having a seventh logic value to the storage controller based on determining that the voltage drop has occurred in the first power-on reset signal; and Based on determining that the voltage drop has not occurred in the first power-on reset signal, the error detection signal having an eighth logic value different from the seventh logic value is provided to the storage controller.

7. The storage device according to claim 1, wherein: The voltage drop in the first power-on reset signal is caused by at least one of interference from adjacent electronic components, high temperature, and physical impact on a transmission line through which the first power-on reset signal is transmitted from the monitoring circuit to the storage controller.

8. The storage device according to claim 1, wherein: the power port receiving a second external power voltage from the host device after the storage controller is powered off by the voltage drop in the first power-on reset signal, wherein the power supply circuit generates a second internal power voltage based on the second external power voltage, wherein the monitoring circuit is further configured to generate a second power-on reset signal based on monitoring of the second external power voltage, and Wherein, the storage controller is further configured as: is driven again based on the second internal power voltage and the second power-on reset signal, and The error detection signal is received from the monitoring circuit after being driven again.

9. The storage device according to claim 1, wherein: The storage controller is further configured to: receiving the error detection signal from the monitoring circuit based on the storage controller being powered off and then driven again by the voltage drop in the first power-on reset signal; and Based on the error detection signal, error detection information indicating the voltage drop in the first power-on reset signal is recorded, wherein the error detection information indicates the shutdown cause.

10. The storage device according to claim 9, further comprising: a first communication port configured to communicate by utilizing an in-band channel, The storage controller is further configured to provide the error detection information to the host device through the first communication port.

11. The storage device according to claim 9, further comprising: a second communication port configured to communicate by utilizing an out-of-band channel; as well as A microcontroller unit is configured to receive the error detection information from the storage controller and provide the error detection information to the host device through the second communication port.

12. A method performed by a storage device, wherein: The storage device comprises a memory device, a power port, a power circuit, a storage controller and a monitoring circuit, and the method comprises: receiving a first external power voltage from a host device via the power port; generating, by the power supply circuit, a first internal power voltage based on the first external power voltage; generating, by the monitoring circuit, a first power-on reset signal based on monitoring of the first external power voltage; detecting, by the monitoring circuit, a voltage drop in the first power-on reset signal sent from the monitoring circuit to the storage controller; and The monitoring circuit provides an error detection signal to the storage controller in response to detecting the voltage drop, thereby enabling detection of a shutdown cause of the storage controller, the voltage drop being the shutdown cause of the storage controller, and the error detection signal corresponding to the shutdown cause.

13. The method according to claim 12, wherein: The step of generating the first power-on reset signal by the monitoring circuit based on monitoring the first external power voltage comprises: determining, by the monitoring circuit, whether a first power voltage level of the first external power voltage exceeds a reference voltage level; and The first power on reset signal having a first logic value is generated by the monitoring circuit based on a determination that the first power voltage level exceeds the reference voltage level.

14. The method according to claim 12, wherein: The step of detecting, by the monitoring circuit, the voltage drop in the first power-on reset signal sent from the monitoring circuit to the storage controller comprises: receiving, by the monitoring circuit, a first electrical signal corresponding to the first power-on reset signal passing through an output terminal of the monitoring circuit; receiving, by the monitoring circuit, a second electrical signal corresponding to the first power-on reset signal through an input terminal of the storage controller; and The voltage drop is detected by the monitoring circuit based on a comparison operation of the first electrical signal and the second electrical signal.

15. The method according to claim 14, wherein: The step of detecting the voltage drop based on the comparison operation of the first electrical signal and the second electrical signal by the monitoring circuit includes: determining, by the monitoring circuit, whether a third logic value of the first electrical signal is the same as a fourth logic value of the second electrical signal; and A monitoring signal having a sixth logical value is generated by the monitoring circuit based on determining that the third logical value is different from the fourth logical value.

16. The method according to claim 12, wherein: The step of providing the error detection signal to the storage controller by the monitoring circuit in response to detecting the voltage drop comprises: generating, by the monitoring circuit, the error detection signal having a seventh logic value in response to detecting the voltage drop; and The error detection signal having the seventh logic value is outputted to the storage controller by the monitoring circuit until a state reset signal is received from the storage controller.

17. The method according to claim 12, further comprising: receiving the error detection signal from the monitoring circuit when the storage controller is powered off by the voltage drop and is driven again; as well as Error detection information indicating the voltage drop in the first power-on reset signal is recorded by the storage controller based on the error detection signal, wherein the error detection information indicates the shutdown cause.

18. The method according to claim 12, further comprising: receiving a second external power voltage from the power port; generating, by the power supply circuit, a second internal power voltage based on the second external power voltage; as well as generating a second power-on reset signal by the monitoring circuit based on monitoring the second external power voltage, wherein the storage device is driven again based on the second internal power voltage and the second power-on reset signal, and The storage device receives the error detection signal from the monitoring circuit.

19. The method according to claim 12, wherein: The voltage drop in the first power-on reset signal is caused by at least one of interference from adjacent electronic components, high temperature, and physical impact on a transmission line through which the first power-on reset signal is transmitted from the monitoring circuit to the storage controller.

20. A storage device comprising: Memory device; a power port configured to receive a first external power voltage from a host device; a communication port configured to communicate with the host device; a power circuit configured to receive the first external power voltage from the power port and generate a first internal power voltage based on the first external power voltage; a monitoring circuit configured to receive the first external power voltage from the power port and generate a first power-on reset signal based on monitoring the first external power voltage; a storage controller, wherein the storage controller is driven based on the first internal power voltage and the first power-on reset signal; and a microcontroller unit configured to communicate with the host device by utilizing the communication port, Wherein, the monitoring circuit is configured as follows: detecting a voltage drop in the first power-on reset signal transmitted from the monitoring circuit to the storage controller, and providing an error detection signal to the storage controller in response to detecting the voltage drop, wherein the storage controller is further configured to record error detection information based on the error detection signal so as to be able to detect a shutdown reason of the storage controller, and wherein the voltage drop is the shutdown reason of the storage controller, and Wherein, the microcontroller unit is further configured to provide the error detection information received from the storage controller to the communication port.

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