Optimization design method of clock synchronization phase-locked loop

Abstract

The invention relates to an optimization design method of a clock synchronization phase-locked loop. The method comprises the following steps: preliminarily constructing a clock synchronization phase-locked loop based on a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider; the loop filter is a fractional order filter, and the fractional order filter is constructed based on an equivalent fractional order filter capacitor circuit; constructing a clock synchronous phase-locked loop simulation model, performing iterative optimization on parameters of the preliminarily constructed clock synchronous phase-locked loop through a multi-strategy particle swarm algorithm on the basis of a preset fitness function and constraint conditions, and obtaining an optimal parameter value corresponding to a minimum fitness value through the simulation model; and obtaining a final clock synchronization phase-locked loop based on the optimal parameter value. According to the invention, the problem that the performance of the constructed phase-locked loop is limited due to the fact that the fractional order phase-locked loop in the prior art is difficult to set in the aspects of parameter design, circuit implementation and the like and depends on experience is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of clock synchronization, and in particular relates to an optimization design method for a clock synchronization phase-locked loop. Background Art

[0002] Multi-source sensor networks are of great strategic significance in vehicle-mounted applications. The core of multi-source sensor networks is to achieve comprehensive perception of complex environments and intelligent decision-making by integrating data from different sensors. The efficient operation of such networks depends on strict time synchronization of all nodes. Specifically, by distributing the master clock timestamp to each node, the node adjusts its local clock to align with the master time using a phase-locked method, thereby achieving global clock synchronization. However, the clock synchronization accuracy directly affects the performance of multi-source sensor networks, so the optimization design of synchronization methods is of great research value.

[0003] In recent years, fractional-order phase-locked loops have shown significant performance potential in synchronization. For example, He Yu et al. proposed a three-phase phase-locked loop technology based on fractional-order filters, which effectively improved the synchronization performance of the power grid; Chen Pengfei et al. designed a phase-locked method based on fractional-order PID repetitive control, which successfully solved the problem of phase tracking synchronization failure of traditional phase-locked loops; Pan Zhifeng et al. combined fractional-order PID with a sliding average filter and proposed a three-phase phase-locked method to alleviate the harmonic distortion of the power grid voltage. These studies show that compared with traditional tuning methods, the fractional-order phase-locked loop method constructs a fractional-order phase-locked loop by introducing a fractional-order filter, which extends the order of the phase-locked loop from an integer to a real number, significantly improving the flexibility and performance of the system design. However, the existing fractional-order phase-locked method has problems such as difficulty in tuning and reliance on experience in parameter design and circuit implementation, which leads to limited performance of the constructed phase-locked loop.

[0004] Therefore, optimizing the parameters of the fractional-order clock synchronization phase-locked loop and providing feasible guidance for the design and implementation of the clock synchronization fractional-order phase-locked method are issues that need to be urgently addressed in the application of fractional-order phase-locked loops in clock synchronization. Summary of the invention

[0005] In view of the above analysis, the present invention aims to disclose an optimization design method for a clock synchronous phase-locked loop, which solves the problem that the fractional-order phase-locked loop in the prior art has difficulty in setting parameters and circuit implementation, and relies on experience, resulting in limited performance of the constructed phase-locked loop.

[0006] The purpose of the present invention is mainly achieved through the following technical solutions:

[0007] The present invention discloses an optimization design method for a clock synchronization phase-locked loop, comprising:

[0008] Based on a frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider, a clock synchronization phase-locked loop is preliminarily constructed; the loop filter is a fractional-order filter, and the fractional-order filter is constructed based on an equivalent fractional-order filter capacitor circuit;

[0009] Constructing a clock synchronization phase-locked loop simulation model, and iteratively optimizing the parameters of the clock synchronization phase-locked loop constructed initially through a multi-strategy particle swarm algorithm based on a preset fitness function and constraints, and obtaining the optimal parameter value corresponding to the minimized fitness value through the simulation model;

[0010] A final clock synchronization phase-locked loop is obtained based on the optimal parameter values.

[0011] Furthermore, the fractional-order filter includes an equivalent fractional-order capacitor filter circuit and an RC filter circuit;

[0012] The equivalent fractional-order capacitor filter circuit comprises a resistor R and N filter groups, the i-th filter group comprises a resistor Ri and a capacitor Ci connected in parallel, i∈{1,2…n}; the resistor R and the N filter groups are connected in series in sequence; wherein one end of the resistor R is electrically connected to the output end of the charge pump, and the other end is electrically connected to the first filter group, and the last filter group is grounded;

[0013] The RC filter circuit includes a resistor R0 and a capacitor C0 connected in series, the other end of the resistor R0 is electrically connected to the output end of the charge pump, and the other end of the capacitor C0 is grounded.

[0014] Furthermore, the preset fitness function is expressed as:

[0015] g=∫t|e(t)|dt

[0016] The constraints are:

[0017]

[0018] Where g is the fitness function, e(t) is the phase error at time t; Z is an integer; ts is the adjustment time; t 0 is the maximum permissible tracking time required by the clock synchronization process; E 0 is the maximum allowable clock synchronization error, Ess is the steady-state error, wb is the lowest value of the filter frequency range, and wh is the highest value of the filter frequency range.

[0019] Further, the parameters of the clock synchronization phase-locked loop optimized by the multi-strategy particle swarm algorithm include: the frequency range of the fractional-order filter [wb, wh], the capacitance order α and capacitance value C of the equivalent fractional-order filter capacitor circuit, and the capacitance value C of the RC filter circuit. 0 and the resistance value R0 , the approximation order N to be determined.

[0020] Furthermore, based on the frequency range [wb, wh] of the fractional-order filter, the differential operator s of the α-order capacitor is obtained according to the approximation principle of ORA: α The expression of is:

[0021]

[0022] The above formula is expanded into a factor addition form by the Residue method, and the transfer function of the α-order capacitor is obtained, which is expressed as:

[0023]

[0024] Among them, r i is the residue, p i for the extreme point;

[0025] Based on the transfer function of the α-order capacitor, the capacitance and resistance values ​​of the topological network of the equivalent fractional-order filter capacitor circuit are obtained by the following formula:

[0026]

[0027] Where R is the resistance value of resistor R, R i is the resistance value of the i-th resistor in the circuit topology network, C i is the ith capacitor in the circuit topology; C is the equivalent capacitance value.

[0028] Furthermore, the parameters of the clock synchronization phase-locked loop initially constructed are iteratively optimized by using a multi-strategy particle swarm algorithm, including:

[0029] S31: randomly initializing the flight position and flight speed of each particle in the particle swarm based on the parameters of the clock synchronous phase-locked loop to be optimized, and randomly dividing the particle swarm into two sub-populations, setting corresponding position update strategies for the two sub-populations; the flight position of each particle in the particle swarm is a possible solution of each parameter of the phase-locked loop;

[0030] S32: performing circuit simulation based on the flight position and flight speed of each particle, and obtaining the fitness value of the position of each particle in the two sub-populations based on a preset fitness function and constraint conditions;

[0031] S33: obtaining the local extreme value pbest and the global extreme value gbest of each particle based on the currently minimized fitness value; and based on the local extreme value pbest and the global extreme value gbest, using the corresponding position update strategy to update the position and velocity of each particle in the two sub-populations;

[0032] S34: Randomly select P particles from each sub-population and add them to the hybridization pool to perform hybridization to generate new particles, and add the P new particles generated by hybridization to the two sub-populations to replace the P particles with the lowest fitness in each population;

[0033] S35: Repeat S32-S34, iteratively optimize the position and speed of each particle until the maximum number of iterations is reached, and obtain the optimal parameter value corresponding to the minimized fitness function; during the iterative optimization process, if the algorithm reaches the maximum continuous non-improvement algebraic value, the particle swarm is perturbed based on the preset perturbation strategy and S32-S34 is repeated for iterative optimization.

[0034] Furthermore, an adaptive location update strategy is used to update the location of the first sub-population, which is expressed as:

[0035]

[0036] in, and They represent the velocity and position of the i-th particle in the first sub-swarm at the current moment, k represents the number of iterations of the current particle, and c 1 and c 2 is the learning factor, the value range is [0,4], r 1 and r 2 is a random number between [0,1], ω(k) is the adaptive inertia weight, which represents the influence of the speed value of the previous iteration on the speed value of the current iteration; is the local extreme point of particle i, is the global extreme point of the current particle swarm.

[0037] Furthermore, a discrete position update strategy is used to update the position of the second sub-population, which is expressed as:

[0038]

[0039] in, and They represent the velocity and position of the jth particle in the second population at the current moment, r 3 and r 4 are random numbers between [0,2] and [1,2], ω is a fixed inertia weight, G k is the average position value of multiple random particles.

[0040] Furthermore, the particles added to the hybridization pool are hybridized by the following formula to generate new particles:

[0041]

[0042] The new particle speed is:

[0043]

[0044] in, is the position of the new particle generated after hybridization, is the speed of the new particles generated after hybridization, and They represent the velocity and position of the mth particle in the first subpopulation at the current moment, respectively. and They represent the velocity and position of the mth particle in the second sub-population at the current moment, respectively, and α is a random number between [0,1].

[0045] Furthermore, the disturbance strategy includes:

[0046] Generate n disturbance points based on the current global optimal position, expressed as:

[0047]

[0048] Where n is the search dimension; R i An equally probable random number in the interval [0,1] is generated independently for each particle; is the global optimal extreme point of the kth iteration;

[0049] Determine the distance between each particle and the disturbance point If the distance of a particle exceeds the threshold, the particle is expelled at the preset expulsion distance to keep it away from the disturbance point;

[0050] The preset expulsion distance is expressed as:

[0051]

[0052] Among them, k is the current number of iterations, τ is the maximum number of iterations;

[0053] The particle position after being driven away is updated as follows:

[0054]

[0055] in, To update the position of the particle after being driven away, c and d are random numbers between [0,1] and [1,2] respectively; τ is the maximum number of iterations.

[0056] The present invention can achieve at least the following beneficial effects:

[0057] 1. The present invention constructs a fractional-order charge pump phase-locked loop, changes the loop filter order from an integer 1 to between 0 and 1, flexibly adjusts the order through a multi-strategy particle swarm algorithm, and takes into account parameters such as the filtering range and the approximation order, and performs equivalent circuit design based on the optimized parameters, thereby greatly improving the stability and performance of the phase-locked loop;

[0058] 2. The present invention develops a multi-strategy particle swarm algorithm, which improves the standard PSO through multi-population cross-hybridization, adaptive operators and disturbance point strategies. Multi-population cross-hybridization realizes population information exchange, and combined with the disturbance point strategy, it greatly enhances the algorithm's ability to jump out of the local optimum and avoids premature maturity of the algorithm in the early stage. At the same time, the elimination of old particles and the adaptive operator strategy ensure the algorithm's small-scale fine search capability in the later stage, optimizes and selects multiple parameters in the phase-locked loop, and avoids the problem of time-consuming and labor-intensive manual debugging and poor results. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. In the entire drawings, the same reference symbols represent the same components;

[0060] Figure 1 A flow chart of an optimization design method for a clock synchronization phase-locked loop in an embodiment of the present invention;

[0061] Figure 2 Schematic diagram of clock synchronization principle in a multi-source sensor network in an embodiment of the present invention;

[0062] Figure 3 Schematic diagram of a conventional charge pump clock synchronous phase-locked loop structure in an embodiment of the present invention;

[0063] Figure 4 Schematic diagram of the structure of a fractional-order clock synchronous phase-locked loop in an embodiment of the present invention;

[0064] Figure 5 A schematic diagram of a multi-strategy particle swarm algorithm parameter optimization process in an embodiment of the present invention;

[0065] Figure 6 This is a schematic diagram showing the comparison of the results of the MSPSO algorithm and other commonly used algorithms under the CTE14 standard test set in an embodiment of the present invention;

[0066] Figure 7 It is a schematic diagram of the comparison of FOCPPLL optimization between the MSPSO algorithm and other commonly used algorithms under different population sizes in an embodiment of the present invention;

[0067] Figure 8 Comparison of control voltage curves of optimized FOCPPLL and CPPPLL with the same parameters in the embodiment of the present invention;

[0068] Fig. 9 Schematic diagram of the optimized FOCPPLL synchronization process in an embodiment of the present invention;

[0069] Fig.10 This is the implementation process of the 2.46-order fractional-order clock synchronous phase-locked loop circuit in the embodiment of the present invention;

[0070] Fig.11 2.46-order fractional-order clock synchronous phase-locked loop circuit characteristics in an embodiment of the present invention. DETAILED DESCRIPTION

[0071] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used to illustrate the principles of the present invention together with the embodiments of the present invention.

[0072] The embodiment of the present invention discloses a method for optimizing the design of a clock synchronization phase-locked loop, such as Figure 1 As shown, the following steps are included:

[0073] Step S1: Preliminarily constructing a clock synchronization phase-locked loop based on a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider; the loop filter is a fractional-order filter, and the fractional-order filter is constructed based on an equivalent fractional-order filter capacitor circuit;

[0074] In a multi-source sensor communication network, a master clock such as a satellite synchronization system distributes signals such as timestamps containing clock information to other clock synchronization modules in the network through the communication network. The clock synchronization module corrects the local clock by referring to the master clock to achieve clock synchronization of all devices in the entire network, such as Figure 2 The core of the clock synchronization module is the phase-locked loop; the basic principle of the traditional charge-pump phase-locked loop (CPPLL) is as follows Figure 3As shown in FIG. 1 , it includes a loop filter (LF), a voltage-controlled oscillator (VCO), a phase frequency detector (PFD), a charge pump (CP), and a frequency divider. These five parts form a closed-loop control to lock the phase of the input signal and synchronize the local clock with the network master clock. The frequency signal of the master clock is used as the reference input signal (REF). The PFD compares the phase and frequency of the reference signal (REF) and the feedback signal (FB), and generates an error signal (ERR). The ERR is then filtered through the loop filter (LF) to obtain a low-frequency voltage and generate a control voltage signal (VC) to control the VCO and adjust its oscillation frequency so that its output signal (OUT) is aligned and locked with the REF signal frequency. When a frequency divider (N) is added to the feedback loop, the VCO output frequency is divided by the frequency divider ratio (N) and then compared with the REF signal. When CPPLL is working normally, if the loop loses lock, the frequency and phase detector module will generate a corresponding phase error voltage, which is converted into a stable DC control voltage after passing through the loop filter. It acts on the voltage-controlled oscillator module to change its operating frequency, causing the phase of the output signal to change accordingly, thereby reducing the phase difference between the input signal and the output signal. This cycle continues in sequence, and eventually the frequency and phase difference between the input signal and the output signal can be eliminated, achieving a locked state.

[0075] In particular, the fractional-order clock synchronous phase-locked loop of this embodiment is configured as follows: Figure 4 In the structure shown, the frequency and phase detector includes two D flip-flops and a feedback clearing logic gate, and the feedback clearing logic gate is an AND gate; the D terminals of the two D flip-flops are both connected to a high level, and the R terminals are electrically connected to the output terminal of the logic gate; the CK terminal of the first D flip-flop is the main clock input terminal, and the Q terminal is electrically connected to the first input terminal of the logic gate; the CK terminal of the second D flip-flop is the local clock input terminal, and the Q terminal is electrically connected to the second input terminal of the logic gate.

[0076] The charge pump comprises three N-type MOS tubes and three P-type MOS tubes arranged in sequence;

[0077] Among them, the drain of the first N-type MOS tube is connected to the power supply, the source is electrically connected to the source of the second N-type MOS tube, and the gate is electrically connected to the gate of the second N-type MOS tube; the drain of the second N-type MOS tube is electrically connected to the source of the third N-type MOS tube; the gate of the third N-type MOS tube is electrically connected to the second input end of the logic gate, and the drain is electrically connected to the drain of the first P-type MOS tube; the gate of the first P-type MOS tube is electrically connected to the first input end of the logic gate, the source is electrically connected to the drain of the second P-type MOS tube, and the gate of the second P-type MOS tube is electrically connected to the gate and drain of the third P-type MOS tube,

[0078] The two transistors are grounded together, the source of the second P-type MOS transistor is electrically connected to the source of the third P-type MOS transistor, and are connected together to a power source.

[0079] The fractional-order filter includes an equivalent fractional-order capacitor filter circuit and an RC filter circuit;

[0080] The equivalent fractional-order capacitor filter circuit comprises a resistor R and N filter groups, the i-th filter group comprises a resistor Ri and a capacitor Ci connected in parallel, i∈{1,2…n}; the resistor R and the N filter groups are connected in series in sequence; wherein one end of the resistor R is electrically connected to the output end of the charge pump, and the other end is electrically connected to the first filter group, and the last filter group is grounded;

[0081] The RC filter circuit includes a resistor R0 and a capacitor C0 connected in series, the other end of the resistor R0 is electrically connected to the output end of the charge pump, and the other end of the capacitor C0 is grounded.

[0082] The voltage-controlled oscillator comprises three controllable MOS tubes, three inverters and three capacitors; wherein the gates of the three MOS tubes are electrically connected to the output end of the filter; the input end of the first inverter is electrically connected to the source level of the third MOS tube, and is commonly connected to the local clock input end of the frequency and phase detector; the output end of the first inverter is electrically connected to the drain of the first MOS tube, the source level of the first MOS tube is electrically connected to the input end of the second inverter, the output end of the second inverter is electrically connected to the drain of the second MOS tube, the source level of the second MOS tube is electrically connected to the input end of the third inverter, and the output end of the third inverter is electrically connected to the drain of the third MOS tube; the source levels of the three MOS tubes are respectively connected to ground after passing through a capacitor.

[0083] In the clock synchronization phase-locked loop initially constructed, the parameters of the fractional-order filter are all undetermined parameters, which are obtained through subsequent multi-strategy particle swarm algorithm optimization.

[0084] Step S2: constructing a clock synchronization phase-locked loop simulation model, and iteratively optimizing the parameters of the clock synchronization phase-locked loop constructed initially through a multi-strategy particle swarm algorithm based on a preset fitness function and constraint conditions, and obtaining the optimal parameter value corresponding to the minimized fitness value through the simulation model;

[0085] Specifically, in the design of CPPLL (charge pump phase-locked loop), LF (loop filter) is a key module, which is used to filter the input error signal and convert it into a control signal to adjust the output of the voltage-controlled oscillator, which can not only remove high-frequency noise components, but also bring better phase noise shaping capability, loop stability, tracking speed and locking range. Usually the LF of CPPLL is first-order or second-order, and the voltage-controlled oscillator is generally first-order, so CPPLL can generally be divided into second-order and third-order. The second-order loop system is stable, but the performance is limited in terms of phase noise shaping capability, tracking speed and synchronization range. The third-order loop has a more ideal clock synchronization performance, but the system has many parameters to be adjusted and there is a problem of loop instability.

[0086] The difference between the fractional-order charge pump phase-locked loop (FOCPPLL) and the traditional CPPLL is that the filter order value α changes from an integer 1 to between 0 and 1. By flexibly adjusting the order α, the contradiction between the stability and performance of the phase-locked loop can be reconciled. Specifically, using fractional-order capacitors instead of traditional integer-order capacitors to build FOCPPLL, the order is expanded from an integer to a real number, which not only ensures the clock synchronization performance but also overcomes the problem of loop instability.

[0087] Specifically, in order to realize the fractional-order capacitor and phase-locked loop, it is necessary to determine the frequency range of the fractional-order filter [w b ,w h ], the capacitance order α and equivalent capacitance value C of the equivalent fractional filter capacitor circuit, and the capacitance value C of the RC filter circuit 0 and the resistance value R 0 , and the approximation order N to be determined. However, the excessive number of parameters in the fractional-order clock synchronous phase-locked loop makes manual debugging difficult and the performance cannot be guaranteed. Although some studies have proposed some FOCPPLLs, most of them are basically limited to the discussion of fractional order α, without considering the approximation order N, frequency range w b 、w h Impact on loop performance. To address the above issues, this embodiment adopts a multi-strategy particle swarm algorithm (MSPSO) to adjust the parameters of the fractional-order clock synchronous phase-locked loop and its equivalent approximation parameters. The MSPSO algorithm is an improvement on the PSO algorithm, and adopts multiple populations, adaptation and disturbance point strategies to avoid the shortcomings of the traditional PSO algorithm.

[0088] By setting the order and coefficient of the loop reasonably through intelligent algorithms, excellent dynamic performance can be obtained to achieve rapid locking and tracking of the local clock to the master clock. The phase-locked loop essentially tracks the input through feedback, so it can be regarded as a control system. In a control system, steady-state error and adjustment time are the main parameters of system performance. ITAE (Time Absolute Error Score) is a commonly used indicator in control system design. This standard measures the dynamic and steady-state performance of the system. The smaller the value, the better the system performance. Therefore, it is reasonable to use ITAE to measure the performance of the control system. The mathematical expression of ITAE can be written as:

[0089] ITAE=∫t|e(t)|dt;

[0090] Where t is the system operation time, e(t) is the error at each moment, which is the phase difference between the local clock and the master clock in this embodiment. If the ITAE of the system is too high, it means that the tracking effect is poor. Therefore, this embodiment uses ITAE as the objective function, and optimizes all parameters in the system through algorithm iteration to achieve the minimum ITAE and the optimal control effect. Therefore, the problem designed and optimized in this paper is specifically abstracted as minimizing a constrained global optimization problem, which is expressed as follows:

[0091]

[0092] Where g is the constrained ITAE; ts is the adjustment time; t 0 is the maximum permissible tracking time required by the clock synchronization process; E 0 is the maximum allowable clock synchronization error; Z is an integer.

[0093] The MSPSO algorithm developed in this embodiment is an improvement on the PSO algorithm. The algorithm inherits the advantages of the PSO algorithm, such as fast convergence speed and no influence of initial values ​​when searching for the optimal solution. At the same time, in view of the problem that the particle swarm algorithm is prone to fall into local minima when searching for the optimal solution on a complex surface in a high-dimensional space, the MSPSO algorithm adopts multi-swarm cross-hybridization, adaptive operators and perturbation strategies in combination with the characteristics of the problem to avoid the shortcomings of the traditional PSO algorithm.

[0094] For example, Figure 5 As shown, the parameters of the clock synchronization phase-locked loop constructed initially are iteratively optimized by the MSPSO algorithm, including:

[0095] S31: randomly initializing the flight position and flight speed of each particle in the particle swarm based on the parameters of the clock synchronous phase-locked loop to be optimized, and randomly dividing the particle swarm into two sub-populations, setting corresponding position update strategies for the two sub-populations; the flight position of each particle in the particle swarm is a possible solution of each parameter of the phase-locked loop;

[0096] More specifically, firstly based on the frequency range of the fractional order filter [w b ,w h ], the equivalent capacitance order α and equivalent capacitance value C of the equivalent fractional filter capacitor circuit, the capacitance value C of the RC filter circuit 0 and the resistance value R 0 , the undetermined approximation order N constructs a particle swarm and initializes it to obtain a set of random particles {p 1 ,p 2 ,…p n}.

[0097] S32: performing circuit simulation based on the flight position and flight speed of each particle, and obtaining the fitness value of the position of each particle in the two sub-populations based on a preset fitness function and constraint conditions;

[0098] S33: obtaining the local extreme value pbest and the global extreme value gbest of each particle based on the currently minimized fitness value; and based on the local extreme value pbest and the global extreme value gbest, using the corresponding position update strategy to update the position and velocity of each particle in the two sub-populations;

[0099] Specifically, when the PSO algorithm optimizes multiple parameters at the same time, it often converges prematurely and easily falls into local minima because the PSO algorithm needs to take into account both local exploration and global optimization. The present invention improves the standard PSO algorithm by dividing the population, adding multi-population hybridization, adaptive operators and perturbation strategies to improve the parameter optimization effect;

[0100] Preferably, an adaptive position update strategy is used to update the position of the first sub-population, and an adaptive operator is introduced to balance the global search capability in the early stage and the local search capability in the later stage, thereby optimizing the algorithm speed, which is expressed as:

[0101]

[0102] in, and They represent the velocity and position of the i-th particle in the first sub-swarm at the current moment, k represents the number of iterations of the current particle, and c 1 and c 2 is the learning factor, the value range is [0,4], r 1 and r 2 is a random number between [0,1], ω(k) is the adaptive inertia weight, which represents the influence of the speed value of the previous iteration on the speed value of the current iteration; is the local extreme point of particle i, is the global extreme point of the current particle swarm;

[0103] The discrete position update algorithm is used to update the position of the second sub-population, so that the particles tend to move away from the group to increase the probability of jumping out of the local optimum, which is expressed as:

[0104]

[0105] in, and They represent the velocity and position of the jth particle in the second population at the current moment, r 3 and r 4 are random numbers between [0,2] and [1,2], ω is a fixed inertia weight, G k is the average position value of multiple random particles.

[0106] Among them, the position X represents the parameter value, and the speed value v can be regarded as the rate of change of the parameter in each iteration.

[0107] S34: Randomly select P particles from each sub-population and add them to the hybridization pool to perform hybridization to generate new particles, and add the P new particles generated by hybridization to the two sub-populations to replace the P particles with the lowest fitness in each population;

[0108] Specifically, the particles added to the hybridization pool are hybridized by the following formula to generate new particles:

[0109]

[0110] The new particle speed is:

[0111]

[0112] in, is the position of the new particle generated after hybridization, is the speed of the new particles generated after hybridization, and They represent the velocity and position of the mth particle in the first subpopulation at the current moment, respectively. and They represent the velocity and position of the mth particle in the second sub-population at the current moment, respectively, and α is a random number between [0,1];

[0113] That is, this embodiment realizes information exchange between two populations through hybridization and ensures the optimization performance of the algorithm. The existence of the second sub-population can effectively prevent the algorithm from falling into the local optimum. By setting the cross-hybridization operation, the connection between populations is realized, and the poor individuals in the original population are eliminated to enhance the optimization ability of the algorithm.

[0114] S35: Repeat S32-S34, iteratively optimize the position and speed of each particle until the maximum number of iterations is reached, and obtain the optimal parameter value corresponding to the minimized fitness function; during the iterative optimization process, if the algorithm reaches the maximum continuous non-improvement algebraic value, then perturb the particle swarm based on the preset perturbation strategy and repeat S32-S34 for iterative optimization;

[0115] During the iteration process, when the algorithm continuously evolves without improvement for a number of generations exceeding the tolerable value, multiple additional disturbance points will be generated to randomly expel existing particles, increasing the possibility of escaping from the local optimum and avoiding falling into the local optimum.

[0116] Specifically, the disturbance strategy includes:

[0117] Generate n disturbance points based on the current global optimal position, expressed as:

[0118]

[0119] Where n is the search dimension; R i An equally probable random number in the interval [0,1] is generated independently for each particle; is the global optimal extreme point of the kth iteration;

[0120] Determine the distance between each particle and the disturbance point If the distance of a particle exceeds the threshold, the particle will be expelled at the preset expulsion distance to keep it away from the disturbance point and prevent it from falling into the local optimum.

[0121] The distance between the particle and the disturbance point It is expressed as:

[0122]

[0123] The preset expulsion distance is expressed as:

[0124]

[0125] Among them, k is the current number of iterations, τ is the maximum number of iterations;

[0126] The particle position after being driven away is updated as follows:

[0127]

[0128] in, To update the position of the particle after being driven away, c and d are random numbers between [0,1] and [1,2] respectively; τ is the maximum number of iterations.

[0129] The MSPSO multi-strategy particle swarm algorithm proposed in this embodiment adds multi-population cross-hybridization, adaptive operator and disturbance point strategy to improve the standard PSO; multi-population cross-hybridization realizes population information exchange, and cooperates with the disturbance point strategy to greatly enhance the ability of the algorithm to jump out of the local optimum and avoid premature maturity of the algorithm in the early stage. At the same time, the elimination of old particles and the adaptive operator strategy ensure the small-scale fine search capability of the algorithm in the later stage.

[0130] It should be noted that this embodiment uses the MSPSO multi-strategy particle swarm algorithm to continuously iterate to find the optimal solution for each parameter. In each iteration, each particle updates the position and speed of the current particle according to the parameters of the local extreme point pbest and the global extreme point gbest in the iteration: the local extreme point pbest and the global extreme point gbest represent the historical local extreme point and global extreme point of the corresponding parameter in the optimization process, respectively. Pbest is an array that stores the historical optimum (local optimal extreme value) of a single particle obtained for each parameter in the iteration process for all parameters to be optimized; similarly, gbest stores the historical optimum (global optimal extreme value) of all particles for all parameters. According to the formula, all particles will search for feasible solutions in the direction of a compromise between their own historical optimum (local optimum) and global optimum.

[0131] In order to verify the effect of the multi-strategy particle swarm algorithm (MSPSO) developed in this embodiment, the CTE14 standard test set was used to compare with the standard particle swarm algorithm (PSO), genetic algorithm (GA), attraction repulsion optimization algorithm (AROA), flamingo algorithm (FSA) and other intelligent algorithms. The objective function in the test set was executed 50 times and the average value was taken for comparison. The algorithm parameters are as follows: the maximum number of iterations is 200 times and the population size is 50. Figure 6 The average fitness and data distribution of each algorithm for a total of 23 objective functions in the CTE14 standard test set are compared. From the results, it can be seen that the MSPSO algorithm developed in this paper is better than other algorithms, verifying its effectiveness. Then the MSPSO algorithm is set to a population size of 10, 30, and 50 and applied to the parameter optimization of the FOCPPLL proposed in this paper. The corresponding convergence curve is shown in the figure below. Figure 7 As shown in FIG. 1 , it can be seen from the convergence curve that the multi-strategy particle swarm algorithm proposed in this embodiment has the lowest fitness value and the best optimization effect.

[0132] This embodiment performs performance simulation on the optimized FOCPPLL based on a 30 MHz main clock frequency. Figure 8The control voltage curve is shown to observe the stabilization process of FOCPPLL. The figure also compares integer-order phase-locked loops with the same parameters. It can be observed that the FOCPPLL after parameter optimization can achieve shorter locking time and more stable signals than the integer-order phase-locked loop. Fig. 9 The local clock signal corresponding to the 30MHz master clock input signal is shown, and the phase error between the local clock and the master clock is compared. Fig. 9 As can be seen in the figure, the local clock lags behind the master clock in the initial stage. As the frequency of the local clock increases, the clocks are synchronized. Due to system oscillation, the local clock may lead or lag behind the master clock. This is related to Figure 8 This is consistent with the control voltage oscillation phenomenon in . Figure 8 It can be seen that when the time reaches about 5μs, FOCPPL is basically stable, and CPPLL is still in an oscillating state, indicating that the optimized FOCPPLL has a shorter synchronization time and a more stable clock.

[0133] Step S3: obtaining a final clock synchronization phase-locked loop based on the optimal parameter value;

[0134] Specifically, after the order of the equivalent filter capacitor C is improved to a fractional order, its transfer function expression is as follows:

[0135]

[0136] Among them, α is the fractional order, if α=1, it is an ordinary filter capacitor, and c is the equivalent capacitance value.

[0137] However, in the real world, fractional-order capacitors do not exist, and are only approximated by integer orders. This embodiment uses Oustaloup's recursive approximation (ORA) to perform equivalent approximation on fractional-order capacitors. a In the specified frequency range [w b ,w h ] can be calculated as:

[0138]

[0139] Among them, N is the approximation order to be determined;

[0140] The above formula is expanded into a factor addition form by the Residue method, and the transfer function of the α-order capacitor is obtained, which is expressed as:

[0141]

[0142] Among them, r i is the residue, p ifor the extreme point;

[0143] Based on the transfer function of the α-order capacitor, the capacitance and resistance values ​​of the topological network of the equivalent fractional-order filter capacitor circuit are obtained by the following formula:

[0144]

[0145] Where R is the resistance value of resistor R, R i is the resistance value of the i-th resistor in the circuit topology network, C i is the ith capacitor in the circuit topology; C is the equivalent capacitance value.

[0146] As a specific embodiment, based on the 30 MHz master clock frequency commonly used in multi-source sensor communication networks and conventional parameter settings of the clock synchronization phase-locked loop, such as the voltage-controlled oscillator gain of 30*10 6 Hz / V, output amplitude 1V, charge pump initial current 20*10 -6 A, charge pump gain 6*10 -5 , the phase frequency detector has a time lag of 1*10 -11 s, after optimization by the aforementioned optimization algorithm, the following parameter values ​​of the phase-locked loop are obtained:

[0147]

[0148] Substituting the above parameters into FOCPPLL, that is, a 1st-order 110 pF filter capacitor in the 3rd-order CPPLL becomes 0.46th-order, and a 2.46th-order FOCPPLL is obtained. Its circuit diagram is as follows: Fig.10 As shown;

[0149] According to the phase difference between the main clock and the local clock, the two Q terminals of the PFD respectively output UP and DOWN signals to control the charging and discharging process of the subsequent charge pump. The reset signal generated by the UP and DOWN signals after passing through the logic gate is connected to the R terminal. The charge pump is composed of a current mirror and a MOS switch. The UP and DOWN signals control the drain of the charge pump MOS tube to charge and discharge the subsequent capacitor. The control signal Vctrl enters the ring voltage-controlled oscillator after filtering. The three inverters of the ring voltage-controlled oscillator provide sufficient negative feedback gain to make the VCO oscillate continuously. The controllable MOS equivalent resistor and capacitor form an RC circuit to provide a controllable time constant for the VCO. The control signal adjusts the gate voltage of the MOS tube to change the time constant of the ring voltage-controlled oscillator and thus adjust the oscillation frequency.

[0150] In this embodiment, a 0.46-order capacitor is designed to replace a 1st-order filter capacitor in a 3rd-order CPPLL to construct a 2.46-order FOCPPLL circuit;

[0151] Specifically, the order α, approximation order N, and frequency range w obtained by MSPSO algorithm optimization are b 、w h Substitute the same parameters into the differential operator s of the 0.46-order capacitor α The expression of , we get the following formula:

[0152]

[0153] By using the residue method to expand the above formula into a factor addition form, we get the following result:

[0154]

[0155] Thus, the specific transfer function of the 0.46-order capacitor is obtained. All the numerator constant terms in the above formula are represented by the series r, and all the denominator constant terms are represented by the series p. Substituting the fractional-order capacitance value C, it can be standardized as follows:

[0156]

[0157] Then the above fraction is realized through an RC topology network, such as Fig.10 , where R 1 To R 5 is the resistance in the circuit topology, C 1 To C 5 is the capacitance in the circuit topology. They are:

[0158]

[0159] Where R is the resistance value of resistor R, R i is the resistance value of the i-th resistor in the circuit topology network, C i is the ith capacitor in the circuit topology; C is the equivalent capacitance value.

[0160] The obtained capacitance and resistance values ​​are compared with the passive component library of the IEC60063 standard, and rounded to the nearest standard value to solve the problem that the capacitance and resistance values ​​optimized by the algorithm may not exist in the physical world. The final corrected standard filter capacitance and resistance values ​​of the 2.46-order FOCPPLL after correction are as follows:

[0161]

[0162] Fig.11The operation results of the 2.46-order FOCPPLL circuit are shown, and the control voltage before and after the calibration of the component parameters is compared. As can be seen from the figure, due to the calibration error, the system characteristics have changed to a certain extent, but the control voltage of the equivalent circuit is always kept within 0.1V relative to the theoretical value. Compared with CPPLL, the locking time and synchronization performance of the constructed 2.46-order FOCPPLL circuit are still better than CPPLL, which proves the effectiveness of the proposed method and circuit.

[0163] In summary, the optimization design method of the clock synchronization phase-locked loop of the present invention constructs a fractional-order charge pump phase-locked loop, changes the loop filter order value from an integer 1 to between 0 and 1, and flexibly adjusts the order through the MSPSO multi-strategy particle swarm algorithm, and takes into account parameters such as the filtering range and the approximation order, and performs equivalent circuit design based on the optimized parameters, which greatly improves the stability and performance of the phase-locked loop. In addition, the present invention improves the standard PSO algorithm through multi-population cross-hybridization, adaptive operators and disturbance point strategies, develops the MSPSO multi-strategy particle swarm algorithm, realizes population information exchange through multi-population cross-hybridization, cooperates with the disturbance point strategy, greatly enhances the ability of the algorithm to jump out of the local optimum, and avoids premature maturity of the algorithm in the early stage; at the same time, the elimination of old particles and the adaptive operator strategy ensure the small-scale fine search capability of the algorithm in the later stage, optimizes and selects multiple parameters in the phase-locked loop, and avoids the problem of time-consuming and labor-intensive manual debugging and poor effect.

[0164] Those skilled in the art will appreciate that all or part of the process of the method in the above embodiment can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0165] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A clock synchronization phase-locked loop optimization design method, characterized in that: include: Based on the frequency detector, charge pump, loop filter, voltage-controlled oscillator and frequency divider, a clock synchronization phase-locked loop is preliminarily constructed; The loop filter is a fractional-order filter, and the fractional-order filter is constructed based on an equivalent fractional-order filter capacitor circuit; Constructing a clock synchronization phase-locked loop simulation model, and iteratively optimizing the parameters of the clock synchronization phase-locked loop constructed initially through a multi-strategy particle swarm algorithm based on a preset fitness function and constraints, and obtaining the optimal parameter value corresponding to the minimized fitness value through the simulation model; A final clock synchronization phase-locked loop is obtained based on the optimal parameter values.

2. The optimization design method of a clock synchronization phase-locked loop according to claim 1, characterized in that: The fractional-order filter includes an equivalent fractional-order capacitor filter circuit and an RC filter circuit; The equivalent fractional-order capacitor filter circuit comprises a resistor R and N filter groups, the i-th filter group comprises a resistor Ri and a capacitor Ci connected in parallel, i∈{1,2…n}; the resistor R and the N filter groups are connected in series in sequence; wherein one end of the resistor R is electrically connected to the output end of the charge pump, and the other end is electrically connected to the first filter group, and the last filter group is grounded; The RC filter circuit includes a resistor R0 and a capacitor C0 connected in series, the other end of the resistor R0 is electrically connected to the output end of the charge pump, and the other end of the capacitor C0 is grounded.

3. The optimization design method of a clock synchronization phase-locked loop according to claim 1, characterized in that: The preset fitness function is expressed as: g=∫t|e(t)|dt The constraints are: Where g is the fitness function, e(t) is the phase error at time t; Z is an integer; ts is the adjustment time; t0 is the maximum allowable tracking time required by the clock synchronization process; E0 is the maximum allowable clock synchronization error, Ess is the steady-state error, and w b is the lowest value of the filtering frequency range, w h This is the highest value of the filter frequency range.

4. The optimization design method of the clock synchronization phase-locked loop according to claim 2, characterized in that: The parameters of the clock synchronization phase-locked loop optimized by the multi-strategy particle swarm algorithm include: the frequency range of the fractional order filter [w b ,w h ], the capacitance order α and capacitance value C of the equivalent fractional-order filter capacitor circuit, the capacitance value C0 and resistance value R0 of the RC filter circuit, and the approximation order N to be determined.

5. The optimization design method of a clock synchronization phase-locked loop according to claim 4, characterized in that: Based on the frequency range of fractional order filter [w b ,w h ], according to the approximation principle of ORA, the differential operator s of the α-order capacitance is obtained α The expression of is: The above formula is expanded into a factor addition form by the Residue method, and the transfer function of the α-order capacitor is obtained, which is expressed as: Among them, r i is the residue, p i for the extreme point; Based on the transfer function of the α-order capacitor, the capacitance and resistance values ​​of the topological network of the equivalent fractional-order filter capacitor circuit are obtained by the following formula: Where R is the resistance value of resistor R, R i is the resistance value of the i-th resistor in the circuit topology network, C i is the ith capacitor in the circuit topology; C is the equivalent capacitance value.

6. The optimization design method of a clock synchronization phase-locked loop according to claim 1, characterized in that: The parameters of the clock synchronization phase-locked loop constructed initially are iteratively optimized by using a multi-strategy particle swarm algorithm, including: S31: randomly initializing the flight position and flight speed of each particle in the particle swarm based on the parameters of the clock synchronous phase-locked loop to be optimized, and randomly dividing the particle swarm into two sub-populations, setting corresponding position update strategies for the two sub-populations; the flight position of each particle in the particle swarm is a possible solution of each parameter of the phase-locked loop; S32: performing circuit simulation based on the flight position and flight speed of each particle, and obtaining the fitness value of the position of each particle in the two sub-populations based on a preset fitness function and constraint conditions; S33: obtaining the local extreme value pbest and the global extreme value gbest of each particle based on the currently minimized fitness value; and based on the local extreme value pbest and the global extreme value gbest, using the corresponding position update strategy to update the position and velocity of each particle in the two sub-populations; S34: Randomly select P particles from each sub-population and add them to the hybridization pool to perform hybridization to generate new particles, and add the P new particles generated by hybridization to the two sub-populations to replace the P particles with the lowest fitness in each population; S35: Repeat S32-S34, iteratively optimize the position and speed of each particle until the maximum number of iterations is reached, and obtain the optimal parameter value corresponding to the minimized fitness function; during the iterative optimization process, if the algorithm reaches the maximum continuous non-improvement algebraic value, the particle swarm is perturbed based on the preset perturbation strategy and S32-S34 is repeated for iterative optimization.

7. The optimization design method of a clock synchronization phase-locked loop according to claim 6, characterized in that: Adopt the adaptive position update strategy to update the position of the first sub-population, which can be expressed as: in, and Respectively represent the velocity and position of the i-th particle in the first sub-swarm at the current moment, k represents the number of iterations of the current particle, c1 and c2 are learning factors, ranging from [0,4], r1 and r2 are random numbers between [0,1], ω(k) is the adaptive inertia weight, representing the influence of the velocity value of the previous iteration on the velocity value of the current iteration; is the local extreme point of particle i, is the global extreme point of the current particle swarm.

8. The optimization design method of a clock synchronization phase-locked loop according to claim 6, characterized in that: The discrete position update strategy is used to update the position of the second sub-population, which can be expressed as: in, and Respectively represent the velocity and position of the jth particle in the second population at the current moment, r3 and r4 are random numbers between [0,2] and [1,2], ω is a fixed inertia weight, G k is the average position value of multiple random particles.

9. The optimization design method of a clock synchronization phase-locked loop according to claim 6, characterized in that: The particles added to the hybridization pool are hybridized using the following formula to generate new particles: The new particle speed is: in, is the position of the new particle generated after hybridization, is the speed of the new particles generated after hybridization, and They represent the velocity and position of the mth particle in the first sub-population at the current moment, respectively. and They represent the velocity and position of the mth particle in the second sub-population at the current moment, respectively, and α is a random number between [0,1].

10. The optimization design method of a clock synchronization phase-locked loop according to claim 6, characterized in that: The disturbance strategy includes: Generate n disturbance points based on the current global optimal position, expressed as: Where n is the search dimension; R i An equally probable random number in the interval [0,1] is generated independently for each particle; is the global optimal extreme point of the kth iteration; Determine the distance between each particle and the disturbance point If the distance of a particle exceeds the threshold, the particle is expelled at the preset expulsion distance to keep it away from the disturbance point; The preset expulsion distance is expressed as: Among them, k is the current number of iterations, τ is the maximum number of iterations; The particle position after being driven away is updated as follows: in, To update the position of the particle after being driven away, c and d are random numbers between [0,1] and [1,2] respectively; τ is the maximum number of iterations.

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