Method for reducing generation of defects in polycrystalline silicon etching process

Abstract

The invention discloses a method for reducing generation of defects in a polycrystalline silicon etching process. The method at least comprises the following steps: providing a substrate; forming a first dielectric layer and a polycrystalline silicon layer on the substrate; forming a patterned first photoresist layer on the polycrystalline silicon layer; injecting F ions into the polycrystalline silicon layer for at least two times; by controlling the technological parameters of each time of F ion implantation, products generated by reaction of F ions and the first photoresist layer on the upper surface of the polycrystalline silicon layer are reduced, so that defects generated in the subsequent polycrystalline silicon etching process are reduced.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, and in particular to a method for reducing defect generation in a polysilicon etching process. Background Art

[0002] In CMOS image sensor products, polysilicon (Poly) is used as the gate electrode. When the concentration of N-type ions (for example, phosphorus (P) and arsenic (As)) is limited, a voltage drop will be formed, and an electric field will exist therein, thereby causing silicon oxide (SiO 2 ) The electrons at the interface are easily attracted to one side of the gate electrode by the electric field, resulting in a depletion layer at the interface.

[0003] The main function of the NPO (NMOS Poly pre-dope) process is to allow the doped N-type ions of the NMOS polysilicon to reach the interface between the polysilicon and the gate oxide layer after the polysilicon is deposited, thereby preventing the occurrence of polysilicon depletion. The purpose of the F ion injection in the NPO process is to improve the random telegraph signal (RTS) noise.

[0004] In order to make polysilicon etch a better morphology, the polysilicon etching (Poly Etch) process usually uses a hard mask (HM) as an etching barrier layer. PEOX (Plasma Enhanced Oxide) is used as HM1, which usually has a low deposition rate and high density to prevent ions from precipitating in polysilicon. Low Temperature Oxide (LTO) is used as HM2 to reduce the impact on gate damage.

[0005] In the formation process of CMOS image sensors, a large number of random cone defects (Random Cone Defect) are found in the polysilicon etching process. CMOS image sensors are sensitive to some special cone defects (Special Cone Defect). Some cone defects will cause loss of yield, seriously affecting the stability of the yield of CMOS image sensors. Summary of the invention

[0006] Based on the above problems, an embodiment of the present invention provides a method for reducing defects in a polysilicon etching process, characterized in that the method comprises at least: providing a substrate; forming a first dielectric layer and a polysilicon layer on the substrate; forming a patterned first photoresist layer on the polysilicon layer; implanting F ions into the polysilicon layer at least twice; and controlling the process parameters of each F ion implantation to reduce products formed by the reaction of F ions with the first photoresist layer on the upper surface of the polysilicon layer, thereby reducing defects in a subsequent polysilicon etching process.

[0007] In some embodiments, the method further comprises: 2 H 2 and O 2 The first photoresist layer after reacting with F ions is removed by dry etching; the residue on the surface of the polysilicon layer is removed by wet etching; a hard mask layer is formed on the polysilicon layer; a patterned second photoresist layer is formed on the hard mask layer; a portion of the hard mask layer and a portion of the polysilicon layer are removed by etching to form a polysilicon gate.

[0008] In some embodiments, the process parameters of performing at least two F ion implantations on the polysilicon layer include: each F ion implantation dose is selectable, and a total dose of multiple F ion implantations reaches a threshold.

[0009] In some embodiments, the process parameters of performing at least two F ion implantations on the polysilicon layer include: the first F ion implantation parameters include: an implantation energy of 5-15K, a first implantation dose controlled at 1E15-4E15 / cm 2 The second F ion implantation parameters include: implantation energy 5-15K, control of the second implantation dose at 1E15-4E15 / cm 2 between; the total dose of two F ion implantations reaches a threshold.

[0010] In some embodiments, the method further comprises: 2 H 2 Dry etching removes the first photoresist layer after the reaction with F ions; 2 and N 2 H 2 The remaining first photoresist layer after the reaction with F is removed by dry etching; the residue on the surface of the polysilicon layer is removed by wet etching; a hard mask layer is formed on the polysilicon layer; a patterned second photoresist layer is formed on the hard mask layer; a portion of the hard mask layer and a portion of the polysilicon layer are removed by etching to form a polysilicon gate.

[0011] In some embodiments, the 2 H 2The process parameters of dry etching to remove the first photoresist layer after reaction with F include: gas pressure range: 500~2000mT; RF power range: 1500~3000w, RF time range: 10~90s; N 2 H 2 The gas flow rate range is: 2000~6000sccm; 2 and N 2 H 2 The process parameters of dry etching to remove the first photoresist layer after reacting with F include: 2 and N 2 H 2 The process parameters of dry etching are: gas pressure range: 500~2000mT; RF power range: 1500~3000w, RF time range: 10~90s; 2 / N 2 H 2 Gas flow ratio: 1 / 9; the second time through O 2 and N 2 H 2 The process parameters of dry etching are: gas pressure range: 500~2000mT; RF power range: 1500~3000w, RF time range: 10~90s; 2 / N 2 H 2 The gas flow ratio is: 9 / 1.

[0012] In some embodiments, the thickness of the patterned first photoresist layer is greater than 3100 Å.

[0013] In some embodiments, the 2 H 2 The dry etching removes 5% to 15% of the first photoresist layer after reacting with F.

[0014] In some embodiments, the implanting of F ions into the polysilicon layer at least twice comprises: implanting P ions into the polysilicon layer; and implanting F ions into the polysilicon layer at least twice.

[0015] In some embodiments, the method is applied to a CMOS image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The invention discloses a method for etching polysilicon to form a gate for an image sensor.

[0017] Figures 2 to 7 for Figure 1 A schematic diagram of the structure of the process of etching polysilicon to form a gate for an image sensor.

[0018] Figure 8 The invention discloses a new method for etching polysilicon to form a gate for an image sensor.

[0019] Figures 9 to 15 for Figure 8 A schematic diagram of the structure of the process of etching polysilicon to form a gate for an image sensor. DETAILED DESCRIPTION

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present invention. For ordinary technicians in this field, the present invention can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

[0021] Figure 1 The present invention provides a method for etching polysilicon to form a gate for an image sensor, and the method comprises the following steps.

[0022] Step S11: providing a substrate.

[0023] For step S11, refer to Figure 2 , the substrate 101 may be a doped or undoped semiconductor material, such as silicon, germanium, silicon germanium, silicon germanium on insulator (SGOI) or a combination thereof. The substrate 101 may include a substrate of multiple epitaxial layers. The substrate 101 includes a pixel region and a logic region of the image sensor. The pixel region of the image sensor is used to receive an external optical signal and convert it into an electrical signal for imaging. The specific structure of the pixel region and the logic region of the image sensor is not described in detail here.

[0024] Step S12: forming a first dielectric layer and a polysilicon layer on the substrate.

[0025] For step S12, refer to Figure 2 , a first dielectric layer 102 and a polysilicon layer 103 may be formed on the substrate 101 by deposition. The first dielectric layer 102 is silicon oxide.

[0026] Step S13: forming a patterned first photoresist layer on the polysilicon layer.

[0027] For step S13, refer to Figure 2 The first photoresist layer 104 can be formed on the polysilicon layer 103 by spin coating. The first photoresist layer 104 is a photoresist. Through exposure and development, a patterned first photoresist layer 104 is formed.

[0028] Step S14: implanting at least F ions into the polysilicon layer.

[0029] For step S14, refer to Figure 3 , F ions 105 are implanted into the polysilicon layer 103. Part of the F ions 105 are implanted into the first photoresist layer 104, and react with the first photoresist layer to form reactants 106. Part of the F ions 105 are implanted into the polysilicon layer 103. Before the F ion implantation, a P ion implantation step is required.

[0030] Step S15: By O 2 and N 2 H 2 The first photoresist layer after reacting with the F ions is removed by dry etching.

[0031] For step S15, refer to Figure 4 , through O 2 and N 2 H 2 The first photoresist layer (or reactant 106) after reacting with the F ions is removed by dry etching. In this step, the reactant 106 on the surface of the polysilicon layer 103 cannot be completely removed, and part of the reactant 106 will remain on the surface of the polysilicon layer 103. The reactant 106 has a strong hardness and is prone to forming defects in the subsequent etching process.

[0032] Step S16: removing residues on the surface of the polysilicon layer by wet etching.

[0033] In step S16 , the residue is removed by wet etching, but the reactant 106 is still difficult to remove.

[0034] Step S17: forming a hard mask layer on the polysilicon layer, and forming a patterned second photoresist layer on the hard mask layer.

[0035] For step S17, refer to Figure 5 A hard mask layer 107 is deposited on the polysilicon layer 103, and a patterned second photoresist layer 108 is formed on the hard mask layer 107. The hard mask layer 107 is made of silicon oxide, silicon nitride, silicon oxynitride, etc. The second photoresist layer 108 is photoresist.

[0036] Step S18: etching and removing a portion of the hard mask layer and a portion of the polysilicon layer to form a polysilicon gate.

[0037] For step S18, refer to Figure 6 and Figure 7, after etching away a part of the hard mask layer 107, there are still reactants 106 on the surface of the polysilicon layer 103. Due to the existence of the reactants 106, after etching away a part of the polysilicon layer 103, there is unetched polysilicon 103 on the surface of the substrate 101, thus forming a defect 109. This defect 109 will reduce the yield of the image sensor chip.

[0038] In order to avoid the formation of defects 109 during the subsequent etching process of polysilicon 103 due to the reaction products 106 of F ions and the first photoresist layer 104, the present invention also provides a new polysilicon etching process.

[0039] Figure 8 A method for etching polysilicon to form a gate for an image sensor according to the present invention. The method includes the following steps.

[0040] Step S21: Provide a substrate.

[0041] For step S21, refer to Fig. 9 , the substrate 201 may be a doped or undoped semiconductor material, such as silicon, germanium, silicon germanium, silicon germanium on insulator (SGOI), or a combination thereof. The substrate 201 may include a substrate with multiple epitaxial layers. The substrate 201 includes a pixel region and a logic region of the image sensor. The pixel region of the image sensor is used to receive external optical signals and convert them into electrical signals for imaging. The specific structures of the pixel region and the logic region of the image sensor are not described in detail herein.

[0042] Step S22: Form a first dielectric layer and a polysilicon layer on the substrate.

[0043] For step S22, refer to Fig. 9 , the first dielectric layer 202 and the polysilicon layer 203 can be formed on the substrate 201 by deposition. The first dielectric layer 202 is silicon oxide.

[0044] Step S23: Form a patterned first photoresist layer on the polysilicon layer.

[0045] For step S23, refer to Fig. 9 , the first photoresist layer 204 can be formed on the polysilicon layer 103 by spin coating. The first photoresist layer 204 is photoresist. Through exposure and development, a patterned first photoresist layer 204 is formed. The thickness of the patterned first photoresist layer 204 is greater than 3100A.

[0046] Step S24: Inject F ions into the polysilicon layer at least twice.

[0047] Step S25: controlling the process parameters of each F ion implantation to reduce the products generated by the reaction between the F ions and the first photoresist layer on the upper surface of the polysilicon layer, thereby reducing the generation of defects in the subsequent polysilicon etching process.

[0048] For steps S24 and S25, refer to Fig.10 , F ions 205 are implanted twice into the polysilicon layer 203. Fig.11 , a second F ion 205 is implanted into the polysilicon layer 203 .

[0049] Part of the F ions 205 are implanted into the first photoresist layer 204 and react with the first photoresist layer to form reactants 206. Part of the F ions 205 are implanted into the polysilicon layer 203. Before implanting the F ions, another step of implanting the P ions is required.

[0050] The process parameters of performing at least two F ion implantations on the polysilicon layer include: the F ion implantation dose each time is selectable, and the total dose of the multiple F ion implantations reaches a threshold value.

[0051] The process parameters for performing at least two F ion implantations on the polysilicon layer include: the first F ion implantation parameters include: the implantation energy is 5-15K, the first implantation dose is controlled at 1E15-4E15 / cm 2 The second F ion implantation parameters include: implantation energy of 5-15K, and control of the second implantation dose at 1E15-4E15 / cm 2 between; the total dose of two F ion implantations reaches a threshold.

[0052] Further, refer to Fig.12 , through N 2 H 2 and O 2 The first photoresist layer (or the reactant 206 ) after reacting with the F ions is removed by dry etching; and the residue on the surface of the polysilicon layer 203 is removed by wet etching.

[0053] In another embodiment, N 2 H 2 Dry etching removes a portion of the first photoresist layer (or reactant 106) after reacting with F ions. The process parameters include: gas pressure range: 500~2000mT; RF power range: 1500~3000w, RF time range: 10~90s; N 2 H 2 The gas flow rate range is: 2000~6000sccm. 2 H 2Dry etching removes 5% to 15% of the first photoresist layer after the reaction with the F ions. 2 and N 2 H 2 The remaining portion of the first photoresist layer after the reaction with the F ions (or the reactant 106) is removed by dry etching. 2 and N 2 H 2 The process parameters of dry etching are: gas pressure range: 500~2000mT; RF power range: 1500~3000w, RF time range: 10~90s; 2 / N 2 H 2 Gas flow ratio: 1 / 9; the second time through O 2 and N 2 H 2 The process parameters of dry etching are: gas pressure range: 500~2000mT; RF power range: 1500~3000w, RF time range: 10~90s; 2 / N 2 H 2 The gas flow ratio is: 9 / 1.

[0054] Further, refer to Fig.13 A hard mask layer 207 is deposited on the polysilicon layer 203, and a patterned second photoresist layer 208 is formed on the hard mask layer 207. The hard mask layer 207 is made of silicon oxide, silicon nitride, silicon oxynitride, etc. The second photoresist layer 208 is photoresist.

[0055] Further, refer to Fig.14 : Part of the hard mask layer 207 and part of the polysilicon layer 203 are removed by etching to form a polysilicon gate.

[0056] Further, refer to Fig.15 , ion implantation is performed on the substrate 201 to form a source 208 and a drain 209 of the transistor.

[0057] Figure 1 In the embodiment shown, for step S18, refer to Figure 6 and Figure 7 After etching away a portion of the hard mask layer 107, reactants 106 still exist on the surface of the polysilicon layer 103. Due to the presence of reactants 106, after etching away a portion of the polysilicon layer 103, unremoved polysilicon 103 exists on the surface of the substrate 101, thereby forming defects 109. The defects 109 reduce the yield of the image sensor chip.

[0058] Figure 8The embodiment shown shows that by implanting F ions at least twice, defects caused by subsequent polysilicon etching due to products of the reaction between F ions and the first photoresist layer can be significantly reduced, thereby improving the yield of the image sensor.

[0059] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present invention. Although it is not explicitly stated here, those skilled in the art may make various modifications, improvements and corrections to the present invention. Such modifications, improvements and corrections are suggested in the present invention, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present invention. It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, as an example and not a limitation, the alternative configurations of the embodiments of the present invention may be considered to be consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.

Claims

1. A method for reducing defects in polysilicon etching process, It is characterized in that At least: providing a substrate; forming a first dielectric layer and a polysilicon layer on the substrate; forming a patterned first photoresist layer on the polysilicon layer; implanting F ions into the polysilicon layer at least twice; By controlling the process parameters of each F ion implantation, the products generated by the reaction between the F ions and the first photoresist layer on the upper surface of the polysilicon layer are reduced, thereby reducing the generation of defects in the subsequent polysilicon etching process.

2. The method according to claim 1, It is characterized in that Further including: By N 2 H 2 and O 2 Dry etching to remove the first photoresist layer after reacting with F ions; removing residues on the surface of the polysilicon layer by wet etching; forming a hard mask layer on the polysilicon layer; forming a patterned second photoresist layer on the hard mask layer; A portion of the hard mask layer and a portion of the polysilicon layer are removed by etching to form a polysilicon gate.

3. The method according to claim 1, It is characterized in that The process parameters for performing at least two F ion implantations on the polysilicon layer include: The implantation dose of F ions each time is selectable, and the total dose of multiple implantations of F ions reaches a threshold value.

4. The method according to claim 1, It is characterized in that The process parameters for performing at least two F ion implantations on the polysilicon layer include: The parameters of the first F ion implantation include: implantation energy 5-15K, control of the first implantation dose at 1E15-4E15 / cm 2 between; The parameters of the second F ion implantation include: implantation energy 5-15K, control of the second implantation dose at 1E15-4E15 / cm 2 between; The total dose of the two F ion implantations reaches a threshold.

5. The method according to claim 1, It is characterized in that Further including: By N 2 H 2 Dry etching to remove the portion of the first photoresist layer that has reacted with the F ions; Through O 2 and N 2 H 2 Dry etching is used to remove the remaining first photoresist layer after reaction with F; removing residues on the surface of the polysilicon layer by wet etching; forming a hard mask layer on the polysilicon layer; forming a patterned second photoresist layer on the hard mask layer; A portion of the hard mask layer and a portion of the polysilicon layer are removed by etching to form a polysilicon gate.

6. The method according to claim 5, It is characterized in that Said by N 2 H 2 The process parameters for dry etching to remove the first photoresist layer after reaction with F include: Air pressure range: 500~2000mT; The RF power range is: 1500~3000w, and the RF time range is: 10~90s; N 2 H 2 Gas flow range: 2000~6000sccm; Said 2 and N 2 H 2 The process parameters for dry etching to remove the first photoresist layer after reacting with F include: First time through O 2 and N 2 H 2 The process parameters of dry etching are: Air pressure range: 500~2000mT; The RF power range is: 1500~3000w, and the RF time range is: 10~90s; O 2 / N 2 H 2 The gas flow ratio is: 1 / 9; Second pass O 2 and N 2 H 2 The process parameters of dry etching are: Air pressure range: 500~2000mT; The RF power range is: 1500~3000w, and the RF time range is: 10~90s; O 2 / N 2 H 2 The gas flow ratio is: 9 / 1.

7. The method according to claim 1, It is characterized in that The thickness of the patterned first photoresist layer is greater than 3100 Å.

8. The method according to claim 5, It is characterized in that Said by N 2 H 2 The dry etching removes 5% to 15% of the first photoresist layer after reacting with F.

9. The method according to claim 1, It is characterized in that The step of implanting F ions into the polysilicon layer at least twice comprises: Implanting P ions into the polysilicon layer; The polysilicon layer is implanted with F ions at least twice.

10. The method according to claim 1, It is characterized in that The method is applied to a CMOS image sensor.

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