Package substrate and manufacturing method thereof

Abstract

Relates to a packaging substrate and a manufacturing method thereof. A package substrate according to an example includes a silicon-based core. The silicon-based core includes a through-hole portion penetrating in a thickness direction of the silicon-based core. The through-hole portion includes a through-hole space in which an electrode is disposed, and a through-hole inner diameter surface surrounding the through-hole space. The package substrate includes a through electrode disposed in the through hole space. The through electrode includes metal crystal particles having a preferred growth orientation as a thickness direction of the silicon-based core. In this case, it is possible to provide a package substrate that has excellent electrical reliability and suppresses misalignment of the conductive layer pattern when forming the rewiring layer.

Description

Technical Field

[0001] The present invention relates to a packaging substrate and a method for manufacturing the same. Background Art

[0002] In the manufacture of electronic products, the process of realizing circuits on semiconductor chips is called the front-end (FE), and the process of assembling the chips into a state that can be used in actual products is called the back-end (BE), which includes the packaging process.

[0003] Recently, the four core technologies of the semiconductor industry that enable the rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology is developing in various forms such as line widths of nanometer units below microns, more than tens of millions of units, high-speed operations, and large amounts of heat dissipation, but there is no corresponding perfect packaging technology to back it up. Therefore, the electrical performance of semiconductors is more determined by packaging technology and its electrical connections than the performance of semiconductor technology itself.

[0004] Recently, research is being conducted on the application of ceramic materials to high-end package substrates. By forming through holes in the ceramic substrate and applying conductive materials to the through holes, the wiring length between the component and the motherboard can be shortened, and excellent electrical characteristics can be achieved.

[0005] Prior art literature

[0006] Patent Literature

[0007] Japanese Patent No. 4803964

[0008] Japanese Patent No. 5258735 Summary of the invention

[0009] Problem to be solved

[0010] An object of the example is to provide a package substrate and the like which has excellent electrical reliability and suppresses mis-alignment of a conductive layer pattern when forming a redistribution layer.

[0011] Means of solving the problem

[0012] A package substrate according to an embodiment of the present specification includes a silicon-based core.

[0013] The silicon-based core includes a through-via portion penetrating along a thickness direction of the silicon-based core.

[0014] The through-hole portion includes: a through-hole space, which is a space for arranging an electrode; and a through-hole inner diameter surface, which surrounds the through-hole space.

[0015] The packaging substrate includes a through electrode arranged in the through hole space.

[0016] The through-electrode includes metal crystal particles having a preferred growth orientation in a thickness direction of the silicon-based core.

[0017] The silicon-based core may include a surface.

[0018] The contact angle of the silicon-based core surface with respect to pure water may be 40° or less.

[0019] When the package substrate is viewed in cross section in the thickness direction, the cross-sectional area of ​​the through-electrode may be 95% or more relative to the cross-sectional area of ​​the through-hole space.

[0020] The silicon-based core may include: an upper surface; and a lower surface facing the upper surface.

[0021] The through hole space may include: a first opening portion contacting an upper surface of the silicon-based core; a second opening portion contacting a lower surface of the silicon-based core; and a minimum inner diameter portion, which is a portion with a minimum inner diameter.

[0022] The minimum inner diameter portion may be disposed between the first opening portion and the second opening portion.

[0023] The thickness of the silicon-based core may be 200 μm to 1000 μm.

[0024] The through electrode may have a diameter of 40 μm to 200 μm.

[0025] The package substrate may include a first redistribution layer disposed on the silicon-based core.

[0026] The first redistribution layer may include: a conductive layer; and another conductive layer disposed on the conductive layer.

[0027] The width of the other conductive layer may be smaller than or equal to the width of the first conductive layer.

[0028] According to another embodiment of the present specification, a method for manufacturing a packaging substrate includes: a preparation step of manufacturing a silicon-based core, wherein the silicon-based core includes a through-hole portion extending through the core in a thickness direction; a through-electrode forming step of forming a through-electrode in the through-hole portion to manufacture a through-electrode silicon-based core; and a manufacturing step of manufacturing a packaging substrate from the through-electrode silicon-based core.

[0029] The through-hole portion includes: a through-hole space, which is a space for arranging an electrode; and a through-hole inner diameter surface, which surrounds the through-hole space.

[0030] In the through-electrode forming step, metal ions are deposited in the through-hole space along a thickness direction of the silicon-based core to form the through-electrode.

[0031] The silicon-based core may include a surface facing in an in-plane direction of the silicon-based core.

[0032] The through-electrode forming step may include: an electrode seed layer configuration process, configuring an electrode seed layer in parallel with a surface in the in-plane direction of the silicon-based core; a gold plating process, depositing the metal ions from the electrode seed layer along a thickness direction of the silicon-based core to form the through-electrode.

[0033] The silicon-based core may include a surface.

[0034] The contact angle of the silicon-based core surface with respect to pure water may be 40° or less.

[0035] The thickness of the silicon-based core may be 200 μm to 1000 μm.

[0036] The through electrode may have a diameter of 50 μm to 150 μm.

[0037] Effects of the Invention

[0038] The package substrate and the like of the example have excellent electrical reliability, and misalignment of a conductive layer pattern can be suppressed when a rewiring layer is formed on the package substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1A is a cross-sectional view illustrating a package substrate according to an embodiment of an example.

[0040] Figure 1B Yes Description Figure 1A Cross-sectional view of a silicon-based core.

[0041] Figure 2 is a cross-sectional view illustrating a package substrate according to another embodiment of the example.

[0042] Figure 3 is a cross-sectional view illustrating a package substrate according to another embodiment of the example.

[0043] Figure 4 is a conceptual diagram illustrating a process of configuring an electrode seed layer in a method for manufacturing a packaging substrate according to another embodiment of the present specification.

[0044] Figure 5A This is a side view of the packaging substrate of Example 1.

[0045] Figure 5B This is a side view of the package substrate of Comparative Example 1.

[0046] Description of Reference Numerals

[0047] 100: Package substrate

[0048] 10: Silicon-based core

[0049] 101: through hole portion 102: through hole space 103: through hole inner diameter surface

[0050] 104: top of silicon core 105: bottom of silicon core

[0051] 106: first opening 107: second opening 108: minimum inner diameter portion

[0052] 109: A surface in the in-plane direction of the silicon-based core

[0053] 20: Through electrode

[0054] 40: first redistribution layer 41: conductive layer 42: insulating layer

[0055] 50: Electrode seed layer

[0056] Dt: thickness direction of the silicon core DETAILED DESCRIPTION

[0057] Hereinafter, the embodiments are described in detail with reference to the accompanying drawings so that those with common knowledge in the technical field to which the present invention belongs can easily implement it. However, the present invention can be implemented in various forms and is not limited to the embodiments described herein. In the entire specification, the same reference numerals are given to similar parts.

[0058] Throughout this specification, the term "combination of these" included in the Markush form expression refers to a mixture or combination of one or more selected from the group consisting of the constituent elements recorded in the Markush form expression, and means that one or more selected from the group consisting of the constituent elements is included.

[0059] Throughout this specification, terms such as "first", "second" or "A", "B" are used to distinguish the same term from each other. In addition, for the expression of a single quantity, unless it is clearly defined in the text, it also includes the expression of multiple quantities.

[0060] In the present specification, the "~" group may refer to a compound corresponding to "~" or a derivative of "~" contained in the compound.

[0061] In this specification, disposing B on A means disposing B in direct contact with A or disposing B on A with another layer between A and B, and is not limited to disposing B in contact with the surface of A.

[0062] In this specification, connecting B on A means that A and B are directly connected or connected through other components. Unless otherwise specified, it is not limited to the direct connection between A and B.

[0063] In the present specification, the expression of individual quantities is interpreted as including the single quantity or plural quantities explained in the text unless otherwise specified.

[0064] In this specification, the shapes, relative sizes, angles, etc. of various structures in the drawings are exemplary and may be exaggerated for the purpose of explanation, and the rights are not limited to the interpretation of the drawings.

[0065] In this specification, A and B are adjacent to each other means that A and B are in contact, or A and B are not in contact with each other but are close to each other. In this specification, the expression that A and B are adjacent to each other shall not be limited to A and B being in contact unless otherwise specified.

[0066] In this specification, unless otherwise specified, a fine line refers to a line having a width of 5 μm or less, and as an example, refers to a line having a width of 1 to 4 μm or less.

[0067] In order to achieve high integration of the package substrate and optimize the signal transmission path, a through hole is formed in the silicon core, and a conductive layer can be formed in the through hole. However, the smaller the inner diameter of the through hole, the more difficult it is to form a conductive layer with stable reliability in the through hole.

[0068] When a through-hole filling process of simply filling a metal in a through-hole is performed, the metal filled before the process is completed blocks both openings of the through-hole, and the through-hole can no longer be filled.

[0069] A method of forming a metal film on the inner diameter surface of the through hole and filling the inner side of the through hole with an insulating resin may also be applicable. However, in the case of forming a rewiring layer on a silicon-based core having such a structure, the insulating resin may have difficulty in stably supporting the rewiring layer. Therefore, a dimple phenomenon may occur in which the rewiring layer formed on the through hole is sunken downward, and an undulation phenomenon may occur in which a corrugated wrinkle is formed on the surface of the rewiring layer. This phenomenon may cause misalignment of the rewiring layer.

[0070] The inventors of the example applied a through electrode including metal crystal particles with adjusted preferential growth orientation to the through-hole portion of the silicon-based core. Based on this, the inventors confirmed that it is possible to provide a packaging substrate having excellent electrical reliability and capable of suppressing misalignment of a rewiring layer formed on the silicon-based core, thereby completing the example.

[0071] Hereinafter, examples will be described in detail.

[0072] Figure 1A is a cross-sectional view illustrating a package substrate according to an embodiment of an example. Figure 1B Yes Description Figure 1A Referring to the cross-sectional view of the silicon-based core. Figure 1A and Figure 1B Describe the example.

[0073] The package substrate 100 according to an example may include a silicon-based core 10 .

[0074] The silicon-based core 10 may have a substrate shape. The silicon-based core 10 is not limited as long as it is a silicon-based material substrate that can be used as an electronic component.

[0075] The silicon-based core 10 may be a glass core. For example, the silicon-based core 10 may be applied to an alkali borosilicate glass plate, an alkali-free borosilicate glass plate, an alkali-free alkaline earth borosilicate glass plate, etc. The silicon-based core 10 may be applied to a glass substrate for electronic devices, such as those manufactured by Schott, AGC, Corning, etc., but is not limited thereto.

[0076] In order to control the surface energy, the silicon-based core 10 may be a silicon-based core coated with a hydrophilic polymer, which adjusts the surface energy within a set range in an example according to needs. In order to control the surface energy, the silicon-based core 10 may be a silicon-based core laminated with a thin film, which adjusts the surface energy within a set range in an example according to needs.

[0077] The surface of the silicon-based core 10 may include: an upper surface (not shown); and a side surface (not shown) connected to the upper surface and formed along the thickness direction of the silicon-based core 10. The surface of the silicon-based core 10 may include a lower surface facing the upper surface.

[0078] The side surface is formed along the thickness direction of the silicon-based core 10, which not only means that the side surface is perpendicular to the upper surface of the silicon-based core 10, but also means that at least a part of the side surface forms another angle (inclination angle) other than 90 degrees with the upper surface.

[0079] The side surface may be a plane or a curved surface.

[0080] The silicon-based core 10 may include a cavity (not shown) which is a space formed by being recessed inside.

[0081] The cavity may be formed by a portion of the upper surface / lower surface of the silicon-based core 10 being recessed along the thickness direction of the silicon-based core 10 , or may be formed by penetrating along the thickness direction of the silicon-based core 10 .

[0082] A component can be installed in the cavity, and the package substrate 100 and the component can be electrically connected. As for the component, in addition to semiconductor components such as CPU, GPU, memory chip, etc., capacitor components, transistor components, impedance components and other modules can also be used. That is, as long as it is a semiconductor component installed in a semiconductor device, it can be used as the component without limitation.

[0083] The silicon-based core 10 may include a through-via portion 101 penetrating along a thickness direction of the silicon-based core 10 .

[0084] The through-hole portion 101 includes a through-hole space 102 which is a space for arranging an electrode, and a through-hole inner diameter surface 103 which surrounds the through-hole space 102 .

[0085] The through hole space 102 may have a uniform inner diameter in the thickness direction of the silicon-based core 10 in practice. The through hole space 102 may have an inner diameter that varies in the thickness direction of the silicon-based core 10 .

[0086] The cross section of the through hole space 102 may be a rectangular quadrilateral. In addition to the rectangular quadrilateral, the cross section of the through hole space 102 may also be an hourglass, a triangle, a trapezoid, etc. The cross section of the through hole space 102 refers to the cross section of the silicon-based core 10 in the thickness direction.

[0087] The through-hole inner diameter surface 103 refers to the surface of the silicon-based core 10 formed inside the through-hole portion 101 .

[0088] The package substrate 100 includes a through electrode 20 disposed in the through hole space 102. The through electrode 20 may be a conductive layer having a column shape. The through electrode 20 may have a diameter that varies along the thickness direction of the silicon-based core 10. The through electrode 20 may actually have a uniform inner diameter along the thickness direction of the silicon-based core 10.

[0089] The cross section of the through electrode 20 may be a rectangular shape. In addition to the rectangular shape, the cross section of the through electrode 20 may also be an hourglass shape, a triangle, a trapezoid, etc. The cross section of the through electrode 20 refers to the cross section of the silicon-based core 10 in the thickness direction.

[0090] The diameter and cross-section of the through-electrode 20 may be substantially the same as the diameter and cross-section of the through-hole space 102 .

[0091] The through-electrode 20 is disposed in the through-hole space 102 , and can transmit an electrical signal along the thickness direction of the silicon-based core 10 , and can electrically connect the element with a main board, a redistribution layer, and the like.

[0092] Physical properties of silicon-based core and through-electrode

[0093] The through electrode 20 may include metal crystal particles having a preferred growth orientation as the thickness direction of the silicon-based core 10. The through electrode 20 may have a preferred growth orientation as the thickness direction of the silicon-based core 10.

[0094] The metal crystal having a preferred growth orientation in the thickness direction of the silicon-based core 10 means that the size of the crystal in the thickness direction of the silicon-based core 10 is larger than the size of the crystal in the in-plane direction of the silicon-based core 10. In other words, the metal crystal having a preferred growth orientation in the thickness direction of the silicon-based core 10 means that the number of grain boundaries per unit length in the thickness direction of the silicon-based core 10 is smaller than the number of grain boundaries per unit length in the in-plane direction of the silicon-based core 10.

[0095] When the through electrode 20 has the above-mentioned features, the through electrode 20 may be formed to occupy most of the through hole space 102. Thus, the generation of voids inside the through electrode 20 or cracks on the surface of the through electrode 20 may be effectively suppressed.

[0096] In this case, the through electrode 20 can be adjusted so that the number of grain boundaries of metal crystals per unit length in the thickness direction of the silicon-based core 10 is below a predetermined level. Thus, the resistance characteristics of the through electrode 20 can be stably adjusted, and the heat generation of the package substrate 100 can be reduced during the element driving process.

[0097] The through-hole space 102 may include a first opening portion (not shown) contacting an upper surface of the silicon-based core 10 , and a second opening portion contacting a lower surface of the silicon-based core 10 .

[0098] The through electrode 20 may include: one end is arranged on the first opening side, and the other end is arranged on the second opening side. The metal crystals arranged on the one end side of the through electrode 20 may have a preferred growth orientation as the thickness direction of the silicon-based core 10. The metal crystals arranged on the other end side of the through electrode 20 may have a preferred growth orientation as the thickness direction of the silicon-based core 10. In this case, the heat generation characteristics of the package substrate can be adjusted by reducing the resistance characteristics of the through electrode 20, and the occurrence of defects such as voids can be stably suppressed during the formation of the through electrode 20.

[0099] The preferred growth orientation of the metal crystals in the through-electrode 20 can be measured in the following manner. The silicon-based core is separated to expose the surface of the through-electrode, or the through-electrode is separated from the silicon-based core. Then, for the surface of the through-electrode, the grain boundaries of the metal crystals in the through-electrode are imaged by a scanning electron microscope (SEM) to measure the preferred growth orientation.

[0100] In addition, the preferred growth orientation of the metal crystals in the through-electrode 20 can be measured by X-ray diffraction (XRD).

[0101] The material of the through electrode 20 is not limited as long as it is conductive. The material of the through electrode 20 may be any one selected from the group consisting of copper, nickel, aluminum, gold, silver, and a combination thereof. The material of the through electrode 20 may be copper.

[0102] The silicon-based core 10 may include a surface. A contact angle of the surface of the silicon-based core 10 with respect to pure water may be 40° or less.

[0103] In an example, the hydrophilicity of the surface of the silicon-based core 10 can be adjusted by controlling the contact angle of the surface of the silicon-based core 10 with respect to pure water. In this case, when the through-electrode 20 is formed by wet plating or the like, the affinity between the electrolytic plating solution containing metal ions and the through-hole inner diameter surface 103 is improved, and the electrolytic plating solution can be evenly distributed throughout the through-hole space 102. This can help form the through-electrode 20 with a more uniform density in the thickness direction of the silicon-based core 10 while suppressing the formation of voids.

[0104] The contact angle of the silicon core 10 surface with respect to pure water is measured by a surface analyzer and a goniometer method. Specifically, a 100 μL droplet of pure water as a probe liquid is injected onto the silicon core 10 surface, the injected droplet is photographed (captured), and then the contact angle is calculated from the photographed image.

[0105] The contact angle of the surface of the silicon-based core 10 for pure water may be 40° or less. The contact angle may be 35° or less. The contact angle may be 30° or less. The contact angle may be 25° or less. The contact angle may be 20° or less. The contact angle may be 17° or less. The contact angle may be 1° or more. In this case, it may help to form a through electrode 20 that suppresses defects and has excellent electrical characteristics.

[0106] When observed from the cross section in the thickness direction of the package substrate 100, the cross-sectional area of ​​the through-electrode 20 may be 95% or more relative to the cross-sectional area of ​​the through-hole space 102, and when observed from the cross section in the thickness direction of the package substrate 100, the cross-sectional area of ​​the through-electrode 20 may be 98% or more relative to the cross-sectional area of ​​the through-hole space 102. When observed from the cross section in the thickness direction of the package substrate 100, the cross-sectional area of ​​the through-electrode 20 may be 99% or more relative to the cross-sectional area of ​​the through-hole space 102. When observed from the cross section in the thickness direction of the package substrate 100, the cross-sectional area of ​​the through-electrode 20 may be 100% or less relative to the cross-sectional area of ​​the through-hole space 102. In this case, when a redistribution layer is formed on the upper surface or the lower surface of the package substrate 100, the through-electrode 20 stably supports the redistribution layer, and the occurrence of the pit phenomenon can be suppressed. In addition, the through-electrode 20 can stably transmit electrical signals between the element and the redistribution layer, etc.

[0107] When observing the cross section of the package substrate 100 in the thickness direction, the cross-sectional area of ​​the through hole space 102 versus the cross-sectional area of ​​the through electrode 20 can be measured using a transmission electron microscope (TEM).

[0108] Structure of silicon-based core and through-electrode

[0109] Figure 2 FIG. 1 is a cross-sectional view illustrating a package substrate according to another embodiment of the present invention. Figure 2 Describe the example.

[0110] The package substrate includes a silicon-based core. The specific structure of the package substrate is directly applicable to the above Figure 1A and Figure 1B The following description will focus on the differences.

[0111] The silicon-based core 10 may include: an upper surface 104; and a lower surface 105 facing the upper surface 104. The through-hole space 102 may include: a first opening 106 in contact with the upper surface 104 of the silicon-based core 10; a second opening 107 in contact with the lower surface 105 of the ceramic core; and a minimum inner diameter portion 108, which is a portion with the smallest inner diameter. The minimum inner diameter portion 108 may be disposed between the first opening 106 and the second opening 107.

[0112] The through hole space 102 may have an inner diameter that varies along the thickness direction of the silicon core 10. In this example, the smallest inner diameter portion 108 is disposed between the first opening 106 and the second opening 107, so that the through electrode 20 filled in the through hole space 102 will not be separated from the silicon core 10.

[0113] The inner diameter of the first opening 106 may be 40 μm to 200 μm. The inner diameter may be greater than 60 μm. The inner diameter may be greater than 80 μm. The inner diameter may be greater than 100 μm. The inner diameter may be less than 180 μm. The inner diameter may be less than 160 μm. The inner diameter may be less than 140 μm. The inner diameter may be less than 120 μm.

[0114] The diameter of the through electrode 20 in the first opening 106 may be 40 μm to 200 μm. The diameter may be 60 μm or more. The diameter may be 80 μm or more. The diameter may be 100 μm or more. The diameter may be 180 μm or less. The diameter may be 160 μm or less. The diameter may be 140 μm or less. The diameter may be 120 μm or less.

[0115] The inner diameter of the second opening 107 may be 40 μm to 200 μm. The inner diameter may be greater than 60 μm. The inner diameter may be greater than 80 μm. The inner diameter may be greater than 100 μm. The inner diameter may be less than 180 μm. The inner diameter may be less than 160 μm. The inner diameter may be less than 140 μm. The inner diameter may be less than 120 μm.

[0116] The diameter of the through electrode 20 in the second opening 107 may be 40 μm to 200 μm. The diameter may be 60 μm or more. The diameter may be 80 μm or more. The diameter may be 100 μm or more. The diameter may be 180 μm or less. The diameter may be 160 μm or less. The diameter may be 140 μm or less. The diameter may be 120 μm or less.

[0117] In this case, both high integration and electrical reliability of the package substrate 100 can be stably controlled.

[0118] The inner diameter of the minimum inner diameter portion 108 may be 50% to 99% of the smaller value of the inner diameter of the first opening portion 106 and the inner diameter of the second opening portion 107. The inner diameter of the minimum inner diameter portion 108 may be 60% or more of the smaller value of the inner diameter of the first opening portion 106 and the inner diameter of the second opening portion 107. The inner diameter of the minimum inner diameter portion 108 may be 70% or more of the smaller value of the inner diameter of the first opening portion 106 and the inner diameter of the second opening portion 107. The inner diameter of the minimum inner diameter portion 108 may be 90% or less of the smaller value of the inner diameter of the first opening portion 106 and the inner diameter of the second opening portion 107. The inner diameter of the minimum inner diameter portion 108 may be 80% or less of the smaller value of the inner diameter of the first opening portion 106 and the inner diameter of the second opening portion 107. In this case, the through-electrode 20 can be stably formed without breakage in the thickness direction of the silicon-based core 10 , and the through-electrode 20 is not easily separated from the silicon-based core 10 .

[0119] In an example, by controlling the diameters of the silicon-based core 10 and the through-electrode 20 at the same time, a package substrate 100 having high integration and stable electrical reliability can be provided. The diameter of the through-electrode 20 refers to an average diameter of the through-electrode 20 .

[0120] The thickness of the silicon-based core 10 may be 200 μm or more. The thickness may be 250 μm or more. The thickness may be 400 μm or more. The thickness may be 500 μm or more. The thickness may be 1000 μm or less.

[0121] The diameter of the through electrode 20 may be 40 μm to 200 μm. The diameter may be 60 μm or more. The diameter may be 80 μm or more. The diameter may be 100 μm or more. The diameter may be 180 μm or less. The diameter may be 160 μm or less. The diameter may be 140 μm or less. The diameter may be 120 μm or less.

[0122] In this case, the through-electrode 20 can be formed without disconnection, and the package substrate 100 having high integration can be provided.

[0123] Other packaging substrate components

[0124] Figure 3 FIG. 1 is a cross-sectional view illustrating a package substrate according to another embodiment of the present invention. Figure 3 Describe the example.

[0125] The package substrate includes a silicon-based core. The specific structure of the package substrate is directly applicable to the above Figure 1A , Figure 1B and Figure 2 The following description will focus on the differences.

[0126] The package substrate 100 may include a first rewiring layer 40 disposed on a silicon-based core 10 .

[0127] The first rewiring layer 40 may include: a conductive layer 41 ; and an insulating layer 42 surrounding the conductive layer 41 .

[0128] The first redistribution layer 40 may be mixed with an insulating layer 42 and a conductive layer 41. The first redistribution layer 40 may be formed in a form in which a conductive layer 41 having a preset position and form is buried in the insulating layer 42. The conductive layer 41 may be formed as a thin line at least in a portion of the first redistribution layer 40. The first redistribution layer 40 may be electrically connected to the upper terminal, components, etc. of the package substrate 100.

[0129] The first redistribution layer 40 may be formed by repeatedly forming and removing the insulating layer 42 and the conductive layer 41 .

[0130] The conductive layer 41 is equivalent to a wire for transmitting an electrical signal. The conductive layer 41 may include a conductive material. For example, the conductive layer 41 may include at least one of copper, nickel, aluminum, gold, or silver. Copper or the like may be used as a material for the conductive layer 41. The material for the conductive layer 41 may be the same material as that for the through-electrode 20.

[0131] The insulating layer 42 is not limited as long as it can be used as an insulating layer in a semiconductor element or a package substrate. For example, the insulating layer 42 can be composed of an epoxy resin containing a filler, etc. For example, the insulating layer 42 can be formed by a build-up laminate material such as Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd., a primer material, etc., but is not limited thereto.

[0132] The first redistribution layer 40 may include two or more conductive layers 41. The first redistribution layer 40 may include: a conductive layer (not shown); and another conductive layer (not shown) disposed on the conductive layer.

[0133] The width of the other conductive layer may be less than or equal to the width of the first conductive layer. The width of the other conductive layer may be less than the width of the first conductive layer.

[0134] The thickness of the other conductive layer may be less than or equal to the thickness of the first conductive layer. The thickness of the other conductive layer may be less than the thickness of the first conductive layer.

[0135] The pitch of the other conductive layer may be less than or equal to the pitch of the first conductive layer. The pitch of the other conductive layer may be less than the pitch of the first conductive layer.

[0136] In the multi-layered first redistribution layer 40, a conductive layer with a smaller width upward can be configured. In the multi-layered first redistribution layer 40, a conductive layer with a thinner thickness upward can be configured. Thus, the package substrate 100 can achieve stable electrical connection with a semiconductor element having a fine pattern.

[0137] The package substrate 100 may include a second redistribution layer (not shown) disposed under the silicon-based core 10 .

[0138] The second redistribution layer may include: a conductive layer; and an insulating layer surrounding the conductive layer. The materials and forming methods of the conductive layer and the insulating layer of the second redistribution layer may be the same as those of the conductive layer and the insulating layer of the first redistribution layer. The description of the conductive layer and the insulating layer of the second redistribution layer is repeated in the above content, so the description is omitted.

[0139] The second redistribution layer may include two or more conductive layers. The second redistribution layer may include: a conductive layer; and another conductive layer disposed under the conductive layer.

[0140] The width of the other conductive layer may be greater than or equal to the width of the first conductive layer. The width of the other conductive layer may be greater than the width of the first conductive layer.

[0141] The thickness of the other conductive layer may be greater than or equal to the thickness of the first conductive layer. The thickness of the other conductive layer may be greater than the thickness of the first conductive layer.

[0142] The pitch of the other conductive layer may be greater than or equal to the pitch of the first conductive layer. The pitch of the other conductive layer may be greater than the pitch of the first conductive layer.

[0143] In the second redistribution layer of the multilayer structure, a conductive layer with a larger width as it goes downwards can be configured. In the second redistribution layer of the multilayer structure, a conductive layer with a larger thickness as it goes downwards can be configured. Thus, the package substrate 100 can achieve a stable electrical connection with a mainboard formed with a wide or thick conductive layer.

[0144] The package substrate 100 may further include bumps (not shown) disposed under the second redistribution layer.

[0145] The bumps can be arranged under the redistribution layer in a predetermined form. For example, the bumps can be arranged under a portion of the package substrate 100 to contact with a main board or the like.

[0146] Semiconductor Package

[0147] A semiconductor package according to another embodiment of the example includes: a package substrate; and a component electrically connected to the package substrate.

[0148] The package substrate is mounted on the mainboard and can be electrically connected to the mainboard.

[0149] The description of the package substrate and components overlaps with the above content, so the description is omitted.

[0150] Method for manufacturing package substrate

[0151] According to another embodiment of the example, a method for manufacturing a packaging substrate includes: a preparation step of manufacturing a silicon-based core, wherein the silicon-based core includes a through-hole portion extending through the core in the thickness direction; a through-electrode forming step of forming a through-electrode in the through-hole portion to manufacture a through-electrode silicon-based core; and a manufacturing step of manufacturing a packaging substrate from the through-electrode silicon-based core.

[0152] In the preparation step, a silicon-based core having a through via portion formed therein may be prepared, or the through via portion may be formed in a silicon-based substrate to manufacture the silicon-based core.

[0153] The silicon-based substrate may be a glass substrate. For example, the silicon-based substrate may be an alkali borosilicate glass plate, an alkali-free borosilicate glass plate, an alkali-free alkaline earth borosilicate glass plate, etc. The silicon-based substrate may be a glass substrate for electronic devices, for example, a glass substrate manufactured by Schott, AGC, Corning, etc., but is not limited thereto.

[0154] In the preparation step, a glass substrate is used as the silicon-based substrate, and the silicon-based core can be manufactured by etching the glass substrate. Specifically, defects can be formed at a predetermined position on the surface of the glass substrate. As a method for forming defects, mechanical etching, laser irradiation, etc. can be used.

[0155] After forming the defect, a through-hole portion may be formed by physical or chemical etching. In the case of chemical etching, wet etching using an etching solution may be performed. There is no limitation on the etching solution as long as it is generally applicable to etching of a glass substrate. For example, the etching solution may be a sulfuric acid solution, a nitric acid solution, or a hydrofluoric acid solution.

[0156] During the etching process, the remaining surface of the glass substrate except for the region where the defect is formed is masked, and etching can be performed without masking.

[0157] A defect is formed at one point on the upper surface of a glass substrate, and a defect is formed at another point on the lower surface of the glass substrate facing the one point and then etched, thereby manufacturing a silicon-based core having a through-hole portion.

[0158] The through-hole portion includes: a through-hole space, which is a space for arranging an electrode; and a through-hole inner diameter surface, which surrounds the through-hole space.

[0159] The description of the materials, characteristics, structure, etc. of the silicon-based core and the components included in the silicon-based core overlaps with the above contents, and thus the description is omitted.

[0160] In order to adjust the surface energy of the silicon-based core to be within a set range in the example, a hydrophilic polymer may be coated on at least a portion of the surface of the silicon-based core, or a hydrophilic film may be stacked on the surface of the silicon-based core.

[0161] In the through-electrode forming step, metal ions are deposited in the through-hole space along a thickness direction of the silicon-based core to form the through-electrode.

[0162] In an example, metal ions may be deposited in a bottom-up direction or a top-down direction of the through-hole space. In this case, during the growth of metal crystals constituting the through-electrode, the deposited metal crystals may be suppressed while blocking the two openings of the through-hole portion. Thus, the plating solution may be stably supplied to the growth surface of the metal crystals, thereby forming a through-electrode that actually fills the through-hole space completely and suppresses the formation of voids.

[0163] Figure 4 1 is a conceptual diagram illustrating a process of configuring an electrode seed layer in a method for manufacturing a package substrate according to another embodiment of the present specification. Figure 4 Describe the example.

[0164] The silicon-based core 10 manufactured in the preparation step may include a surface 109 in the in-plane direction of the silicon-based core. The surface 109 may be the upper surface of the silicon-based core 10 or the lower surface of the silicon-based core 10.

[0165] The through-electrode forming step may include: an electrode seed layer configuration process, configuring an electrode seed layer 50 in parallel with a surface 109 in the in-plane direction of the silicon-based core; a gold plating process, depositing the metal ions from the electrode seed layer 50 along a thickness direction Dt of the silicon-based core to form the through-electrode.

[0166] During the electrode seed layer configuration process, the electrode seed layer 50 may be configured in parallel with the upper surface or the lower surface of the silicon-based core 10. The electrode seed layer 50 is in contact with and configured in parallel with the one surface 109 of the silicon-based core. The electrode seed layer 50 may be configured in parallel with the one surface 109 of the silicon-based core via other components.

[0167] A photoresist layer (not shown) may be disposed between the surface of the electrode seed layer 50 and the one surface 109 of the silicon-based core. Thus, the one surface 109 of the silicon-based core is in contact with the electrode seed layer 50 and is suppressed from being damaged.

[0168] The photoresist layer may be patterned so that the through hole space 102 may be exposed to the electrode seed layer 50. That is, a photoresist layer patterned so as to remove a region in contact with the through hole space 102 in the photoresist layer may be used. In this case, the growth of metal crystals in the through electrode may be prevented from being hindered by the photoresist layer, and the formation of a copper film on one surface 109 in the in-plane direction of the silicon-based core may be suppressed in the through electrode formation step.

[0169] The electrode seed layer 50 may be a metal plate including a metal element constituting the through-electrode. The electrode seed layer 50 may be a metal film including a metal element constituting the through-electrode. The electrode seed layer 50 may be a metal tape electroplated with a metal element constituting the through-electrode.

[0170] The through electrode forming step may include a gold plating process, wherein metal ions are deposited from the electrode seed layer 50 along a thickness direction Dt of the silicon-based core to form the through electrode.

[0171] In the gold plating process, metal ions can be deposited by electrolytic gold plating. The metal ions can be copper ions, nickel ions, aluminum ions, gold ions or silver ions. The metal ions can be copper ions.

[0172] During the gold plating process, the silicon-based core 10 is immersed in an electrolytic plating solution so that the surface of the electrode seed layer 50 and the inner diameter surface 103 of the through hole are in contact with the electrolytic plating solution, and current can be applied to the electrolytic plating solution through the electrode. At this time, metal ions begin to deposit on the electrode seed layer 50 and form metal crystals, which grow along a thickness direction Dt of the silicon-based core to manufacture a through electrode.

[0173] In the through-electrode forming step, the silicon-based core 10 may include a surface. A contact angle of the surface of the silicon-based core 10 with respect to pure water may be 40° or less.

[0174] In the through-electrode forming step, the hydrophilicity of the surface of the silicon-based core 10 can be adjusted by controlling the contact angle of the surface of the silicon-based core 10 with respect to pure water. As a result, the affinity between the through-hole inner diameter surface 103 and the electrolytic plating solution can be improved, thereby making it possible to stably form the through-electrode while substantially completely filling the through-hole space.

[0175] The description of the measurement method of the contact angle of pure water on the surface of the silicon-based core 10 and the specific contact angle range of the surface of the silicon-based core 10 overlaps with the above content, and thus the description is omitted.

[0176] The electrolytic plating solution may contain: water-soluble copper salt, sulfuric acid, chloride ions, accelerators, inhibitors, leveling agents, wetting agents, polishing agents, etc.

[0177] For example, the leveling agent may include compounds containing polyvinyl imidazole, compounds containing polyvinyl pyrrolidone, polyethylene imine and imidazole compounds, 3-diethylamino-7-(4-dimethylaminophenylazo)-5-phenylchlorophenazine, etc., and the concentration may be 0.01g / L to 3g / L based on the total plating solution, and may be 0.02g / L to 0.8g / L.

[0178] For example, the polish may include 3-mercapto-1-propanesulfonic acid sodium salt and bipyridine, and the concentration may be 0.01 g / L to 3 g / L, or 0.02 g / L to 0.5 g / L based on the total amount of the electroplating solution.

[0179] By properly adjusting the concentration of the glazing agent, accelerator, inhibitor, leveling agent, etc., the plating speed can be controlled by physically blocking the plating solution or hindering chemical bonding during electroplating.

[0180] During the electroplating process, the current density of electrolytic copper plating can be 3mA / cm 2 Up to 50mA / cm 2 , the processing time can be 500 seconds to 2000 seconds.

[0181] Thus, it is possible to form a through electrode which can suppress the occurrence of voids and cracks and prevent the pitting phenomenon in the redistribution layer.

[0182] The through-electrode may have a preferred growth orientation in the thickness direction of the silicon-based core 10. The description of the preferred growth orientation of the through-electrode overlaps with the above content, and thus the description is omitted.

[0183] After the through-electrode is formed, the electrode seed layer 50 and the photoresist layer may be removed to manufacture a through-electrode silicon-based core.

[0184] In the manufacturing step, a through-electrode silicon-based core may be manufactured as a package substrate. In the manufacturing step, a package substrate may be manufactured by forming a redistribution layer on and / or under the through-electrode silicon-based core. The redistribution layer may be a first redistribution layer formed on the silicon-based core. The redistribution layer may be a second redistribution layer formed under the silicon-based core.

[0185] The rewiring layer may include: a conductive layer; and an insulating layer surrounding the conductive layer. The description of the conductive layer and the insulating layer is repeated with the above content, so the description is omitted.

[0186] The conductive layer can be formed by a dry method or a wet method.

[0187] The dry method is a method of performing sputtering to form a seed layer in the area where the conductive layer is to be configured, and performing electroplating in the area where the seed layer is formed to form the conductive layer. When forming the seed layer, metals such as titanium, chromium, and nickel can be sputtered, and these metals and copper can be sputtered at the same time. The anchoring effect of the interaction between the metal particles and the surface of the glass core, crack prevention layer, or insulating layer caused by sputtering can improve the adhesion of the conductive layer.

[0188] The wet method is a method in which the portion requiring the conductive layer is primed and then gold-plated. The primer may contain a compound having a functional group such as an amine. Depending on the degree of adhesion required, the primer may contain a compound having a functional group such as an amine and a silane coupling agent at the same time. When a silane coupling agent is used, the surface of the primer treatment object is pre-treated with the silane coupling agent, and then a compound having a functional group such as an amine is applied to the pre-treated area to form a base coat.

[0189] After forming the seed layer or the primer layer, a conductive layer can be formed by electroplating metal. Copper plating can be applied when forming the conductive layer, but it is not limited to this. Before electroplating metal, the part that does not need to form a conductive layer in the seed layer or the primer layer can be inactivated, or the part that needs to form a conductive layer can be activated before electroplating. The activation or inactivation treatment method can be applied to light irradiation treatment such as irradiation of a laser of a specific wavelength, chemical treatment, etc. However, the activation or inactivation treatment can be omitted, and the conductive layer can be patterned by etching according to a preset shape after electroplating metal.

[0190] After forming the conductive layer, an insulating layer surrounding the conductive layer may be formed. The insulating layer may be manufactured in a thin film shape. Specifically, the insulating layer is formed by laminating the thin film shape insulating layer under reduced pressure. In this case, the insulating layer surrounds the conductive layer without gaps, thereby making the package substrate have electrical reliability.

[0191] According to requirements, connection terminals, bumps, a cover layer, etc. may be formed on the upper surface and / or the lower surface of the packaging substrate, or a process of mounting components on the substrate may also be implemented.

[0192] The following examples are described in more detail by using specific embodiments. The following examples are only used to help understand the power of the examples, and the scope of the examples is not limited thereto.

[0193] Manufacturing example: Manufacturing a package substrate

[0194] Example 1: A defect was formed on the surface of a glass plate SG7.8 from Corning by laser irradiation, and then a plurality of through-holes were formed by wet etching, thereby manufacturing a silicon-based core. The inner diameter of the through-hole space in the through-hole was adjusted to 100 μm.

[0195] A photoresist layer is coated and cured on the lower surface of the silicon core, and the photoresist layer is patterned so that the through hole space is not blocked by the photoresist layer. A metal tape of copper material is attached to the surface of the patterned photoresist layer as an electrode seed layer.

[0196] Then, the silicon-based core with the metal tape attached thereto is immersed in an electrolytic plating solution, and then electrolytic copper plating is performed to form a through electrode in the through-hole space.

[0197] After the electrodes are penetrated, the metal tape and the photoresist layer are removed, thereby completing the packaging substrate.

[0198] Comparative Example 1: A silicon-based core used in Example 1 was prepared. Metal sputtering was performed on the inner diameter surface of the through hole of the silicon-based core to form a metal seed layer. Specifically, a nickel target was used to form a nickel layer on the inner diameter surface of the through hole, and a copper target was used to form a copper layer on the nickel layer, thereby completing the metal seed layer. After the silicon-based core having the metal seed layer was immersed in an electrolytic plating solution, electrolytic copper plating was performed in the same manner as in Example 1 to form a through electrode in the through hole space, thereby completing the packaging substrate.

[0199] Comparative Example 2: A metal seed layer was formed on the inner diameter surface of the through hole of the silicon core under the same conditions as in Comparative Example 1. The silicon core with the metal seed layer was immersed in an electrolytic plating solution, and then electrolytic copper plating was performed to form a through electrode with a thickness of 1 μm, thereby completing a package substrate.

[0200] Evaluation Example: Measurement of the contact angle of a silicon-based core with respect to pure water

[0201] The contact angle of the silicon-based core surface of the embodiment and the comparative example with respect to pure water was measured by the angle measurement method using a surface analyzer. Specifically, a 100 μL droplet of pure water as a probe liquid was injected onto the silicon-based core surface, the injected droplet was photographed, and the contact angle was calculated from the photographed image.

[0202] The measured values ​​of Examples and Comparative Examples are shown in Table 1 below.

[0203] Evaluation example: Evaluation of whether pits appear

[0204] A rewiring layer was formed on the package substrate of each embodiment and comparative example. Specifically, a nickel target was used to form a nickel layer on the package substrate, and a copper target was used to form a copper layer on the nickel layer, thereby completing the metal seed layer. Then, electrolytic copper plating was performed on the metal seed layer to form a conductive layer with a thickness of 1 μm. A deposited thin film, i.e., ABF, of Ajinomoto Co., Ltd. was configured on the patterned conductive layer and decompression lamination was performed to form the first rewiring layer.

[0205] Then, the surface of the first redistribution layer on the through electrode was observed with an optical microscope to evaluate whether a pit phenomenon occurred. If the surface was more than 1 μm recessed from the peripheral portion, it was evaluated as unqualified, and if the surface was less than 1 μm recessed from the peripheral portion or was smooth, it was evaluated as qualified.

[0206] The evaluation results of each example and comparative example are shown in Table 1 below.

[0207] Evaluation example: Evaluation of through-electrode shape

[0208] The side surfaces of the package substrates of Comparative Examples 1 and 2 were observed using an optical microscope. The side surface image of the package substrate of Comparative Example 1 is as follows: Figure 5A It is shown that the side image of the package substrate of Comparative Example 2 is as follows Figure 5B Shown.

[0209] Table 1

[0210]

[0211] In Table 1, in the evaluation of whether or not pits occurred, Example 1 and Comparative Example 1 were evaluated as acceptable, while Comparative Example 2 was evaluated as unacceptable. This means that when a through electrode that does not completely fill the through-hole space is formed, pits may occur when forming a rewiring layer.

[0212] In the Figure 5A and Figure 5B In FIG. 1 , it is shown that the through electrodes of Comparative Examples 1 and 2 are formed only in a part of the through hole space. This means that when the preferred growth orientation of the metal crystals contained in the through electrode is in the thickness direction of the silicon-based core, a through electrode with no voids and excellent electrical reliability can be manufactured.

[0213] The preferred embodiments of the present invention are described in detail above, but the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention defined in the claims are also included in the scope of the present invention.

Claims

1. A packaging substrate, characterized in that: including a silicon-based core; The silicon-based core comprises: a through hole portion extending through the silicon-based core in a thickness direction; The through hole portion comprises: The through-hole space is the space for configuring electrodes, and A through hole inner diameter surface, surrounding the through hole space; The packaging substrate includes a through electrode arranged in the through hole space; The through-electrode includes metal crystal particles having a preferred growth orientation in a thickness direction of the silicon-based core.

2. The packaging substrate according to claim 1, characterized in that: The silicon-based core comprises a surface; The contact angle of the surface of the silicon-based core with respect to pure water is 40° or less.

3. The packaging substrate according to claim 1, characterized in that: When viewed in a cross section in a thickness direction of the package substrate, a cross-sectional area of ​​the through-electrode accounts for 95% or more of a cross-sectional area of ​​the through-hole space.

4. The packaging substrate according to claim 1, characterized in that: The silicon-based core comprises: upper surface, and a lower surface, facing the upper surface; The through hole space comprises: The first opening is in contact with the upper surface of the silicon-based core, a second opening portion in contact with the lower surface of the silicon-based core, and The minimum inner diameter part is the part with the smallest inner diameter; The minimum inner diameter portion is arranged between the first opening portion and the second opening portion.

5. The packaging substrate according to claim 1, characterized in that: The thickness of the silicon-based core is 200 μm to 1000 μm; The through electrode has a diameter of 40 μm to 200 μm.

6. The packaging substrate according to claim 1, characterized in that: include: A first redistribution layer is disposed on the silicon-based core; The first redistribution layer includes: a conductive layer, and another conductive layer, disposed on the first conductive layer; The width of the other conductive layer is smaller than or equal to the width of the first conductive layer.

7. A method for manufacturing a packaging substrate, characterized in that: include: a preparation step of manufacturing a silicon-based core including a through-hole portion penetrating in a thickness direction, a through-electrode forming step of forming a through-electrode in the through-via portion to manufacture a through-electrode silicon-based core, and A manufacturing step of manufacturing a packaging substrate from the through-electrode silicon-based core; The through hole portion comprises: The through-hole space is the space for configuring electrodes, and A through hole inner diameter surface, surrounding the through hole space; In the through-electrode forming step, metal ions are deposited in the through-hole space along a thickness direction of the silicon-based core to form the through-electrode.

8. The method for manufacturing a packaging substrate according to claim 7, wherein: The silicon-based core includes a surface in an in-plane direction of the silicon-based core; The through electrode forming step comprises: an electrode seed layer configuration process, configuring an electrode seed layer in parallel with a surface in the in-plane direction of the silicon-based core, and In the gold plating process, the metal ions are deposited from the electrode seed layer along a thickness direction of the silicon-based core to form the through electrode.

9. The method for manufacturing a packaging substrate according to claim 7, wherein: The silicon-based core includes a surface, and a contact angle of the silicon-based core surface with respect to pure water is below 40°.

10. The method for manufacturing a packaging substrate according to claim 7, wherein: The thickness of the silicon-based core is 200 μm to 1000 μm, The through electrode has a diameter of 50 μm to 150 μm.

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