ORing FET control circuit and power supply system
By using four transistors in the ORing FET control circuit for symmetrically matching voltage comparison, the problem of high conduction threshold voltage and insufficient control sensitivity in the prior art is solved, and a lower threshold voltage and higher control sensitivity are achieved.
Patent Information
- Application Number
- CN202311569393.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-21
- Publication Date
- 2025-05-23
AI Technical Summary
The comparison circuit in the existing ORing circuit results in a large threshold voltage required for the field effect tube to conduct, insufficient control sensitivity, and cannot achieve the fastest protection when the source and drain voltages of the field effect tube are close.
In the ORing FET control circuit, the base-collective voltage and base-emitter voltage of the other two transistors are used to match the base-emitter voltage and base-emitter voltage of the other two transistors to achieve symmetric matching of the source and drain voltages of the field effect transistor.
The threshold voltage required for field effect tube conduction is significantly reduced, and the control sensitivity is improved, so that it can be quickly protected when the source and drain voltages of the field effect tube are close.
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Figure CN120033972A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the technical field of switching power supplies, and in particular to an ORing FET control circuit and a power supply system. Background Art
[0002] In a power system where many power products are connected in parallel to an output bus, an ORing (or gate) circuit is generally set between a single power module and the output bus to prevent an abnormality in a power module in the power system from causing an abnormality in the entire power system.
[0003] At present, commonly used ORing circuits can usually include one or more FETs (Field-Effect Transistor) and a comparison circuit that controls them. The comparison circuit is generally composed of two transistors, which compare the voltage changes of the source and drain of the field effect transistor through the two transistors to control the on and off of the field effect transistor.
[0004] However, the comparison circuit in the related art uses the base-collector voltage of one transistor to match the base-emitter voltage of another transistor, which will result in a larger threshold voltage required for the field effect transistor to turn on, insufficient control sensitivity, and failure to provide the fastest protection when the source and drain voltages of the field effect transistor are close. Summary of the invention
[0005] The main purpose of the embodiments of the present application is to provide an ORing FET control circuit and a power supply system, aiming to solve the problem of how to reduce the threshold voltage required for the field effect tube to turn on and improve the control sensitivity.
[0006] To achieve the above object, an embodiment of the present application provides an ORing FET control circuit, wherein the ORing FET control circuit is connected between a single power module and an output bus, and the ORing FET control circuit includes:
[0007] A field effect tube, wherein the source of the field effect tube is connected to the power module, and the drain of the field effect tube is connected to the output bus;
[0008] A first triode, wherein the emitter of the first triode is connected to the source of the field effect tube, and the collector of the first triode is connected to the gate of the field effect tube;
[0009] A second triode, wherein a first end of the second triode is connected to the drain of the field effect tube, and a base and a second end of the second triode are short-circuited;
[0010] a third triode, wherein the collector of the third triode is connected to the base of the first triode, and the base and emitter of the third triode are short-circuited;
[0011] a fourth triode, wherein a first end of the fourth triode is connected to a base and an emitter of the second triode, a base and a second end of the fourth triode are short-circuited, and the base and the emitter of the third triode are connected;
[0012] The collector of the first transistor and the second end of the fourth transistor are connected to a working power supply.
[0013] In addition, to achieve the above-mentioned purpose, an embodiment of the present application further provides a power supply system, which includes: at least one power supply module, and the power supply module is connected to the output bus through the ORing FET control circuit as described above.
[0014] The embodiment of the present application proposes an ORing FET control circuit and a power supply system, which overcomes the problem that the comparison circuit in the related art causes the threshold voltage required for the field effect tube to be turned on to be large and the control sensitivity is insufficient. The ORing FET control circuit includes: a field effect tube, the source of the field effect tube is connected to the power module, and the drain of the field effect tube is connected to the output bus; a first triode, the emitter of the first triode is connected to the source of the field effect tube, and the collector of the first triode is connected to the gate of the field effect tube; a second triode, the first end of the second triode is connected to the drain of the field effect tube, and the base and the second end of the second triode are short-circuited; a third triode, the collector of the third triode is connected to the base of the first triode, and the base and the emitter of the third triode are short-circuited; a fourth triode, the first end of the fourth triode is connected to the base and the emitter of the second triode, the base and the second end of the fourth triode are short-circuited, and the base and the emitter of the third triode are connected. The ORing FET control circuit provided in the embodiment of the present application is provided with four transistors. When comparing the source and drain voltages of the field effect tube, the base-collector voltage plus the base-emitter voltage of two transistors is used to match the base-emitter voltage plus the base-collector voltage of the other two transistors. Compared with the technical solutions in the related art, the matching is more symmetrical, which can significantly reduce the threshold voltage required for the field effect tube to turn on and improve the control sensitivity. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.
[0016] Figure 1A schematic diagram of the structure of an ORing FET control circuit provided in one embodiment of the present application;
[0017] Figure 2 A schematic diagram of the structure of an ORing FET control circuit provided in another embodiment of the present application;
[0018] Figure 3 A schematic diagram of the structure of an ORing FET control circuit provided in yet another embodiment of the present application;
[0019] Figure 4 A schematic diagram of the structure of a power supply system provided in an embodiment of the present application.
[0020] The realization of the purpose, functional features and advantages of the embodiments of the present application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.
[0021] Description of Figure Numbers:
[0022] Label name Label name Q1 / 104 The first transistor Q2 / 106 The second transistor Q3 / 108 The third transistor Q4 / 110 The fourth transistor Q5 / 102 Field Effect Transistor VCC Auxiliary power supply R1 / 112 First resistor R2 / 114 Second resistor 120 Power module voltage node 122 Output bus voltage node 100 Power Module 200 ORing FET Control Circuit 202 Output bus DETAILED DESCRIPTION
[0023] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the embodiments of the present application.
[0024] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.
[0025] In addition, in the embodiments of the present application, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the embodiments of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In addition, the meaning of "and / or" appearing in the full text is to include three parallel schemes. Taking "A and / or B" as an example, it includes scheme A, or scheme B, or a scheme that satisfies both A and B.
[0026] In the embodiments of the present application, unless otherwise clearly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly limited. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.
[0027] It should also be understood that the references to "one embodiment" or "some embodiments" described in the specification of the embodiments of the present application mean that one or more embodiments of the embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.
[0028] In the field of communication power supply, it is often the case that multiple power supplies are connected in parallel to the same bus. The ORing circuit is used between a single power module and the output bus to prevent the entire power system from being affected when a problem occurs in one power module, thereby improving the reliability of the entire power system.
[0029] The commonly used ORing circuit solution currently uses one or more field effect tubes in parallel between the power module and the output bus, and is equipped with a control circuit with a comparison function. When the voltage of the power module is greater than the voltage of the output bus, the current is allowed to flow from the power module to the output bus; when the voltage of the power module is lower than the output bus, the current of the output bus is prevented from flowing back to the power module.
[0030] The related art discloses an improved controller for an O-ring field effect transistor, which uses two bipolar transistors to selectively control the on and off of the field effect transistor to realize the ORing function. The emitter of the first bipolar transistor is connected to the source of the field effect transistor, and the collector of the second bipolar transistor is connected to the drain of the field effect transistor. The two bipolar transistors are used as a comparison circuit to compare the voltage changes of the source and drain of the field effect transistor to control the on and off of the field effect transistor. However, in this solution, there is a difference between the base-emitter voltage of the first bipolar transistor and the base-collector voltage of the second bipolar transistor, so that the comparison circuit still has an input offset, and the fastest protection cannot be achieved when the voltage of the source and drain of the field effect transistor is close.
[0031] Based on this, the embodiment of the present application provides an ORing FET control circuit and power supply system, which overcomes the problem that the comparison circuit in the related art will cause the threshold voltage required for the field effect tube to turn on to be large and the control sensitivity to be insufficient. The embodiment of the present application sets four transistors in the ORing FET control circuit. When comparing the source and drain voltages of the field effect tube, the base-collector voltage plus the base-emitter voltage of two transistors is used to match the base-emitter voltage plus the base-collector voltage of the other two transistors. Compared with the technical solutions in the related art, the matching is more symmetrical, which can significantly reduce the threshold voltage required for the field effect tube to turn on and improve the control sensitivity.
[0032] The ORing FET control circuit and power supply system provided in the embodiments of the present application are specifically described through the following embodiments. First, the ORing FET control circuit in the embodiments of the present application is described.
[0033] The present application embodiment provides an ORing FET control circuit, referring to Figure 1 , Figure 1 A schematic diagram of the structure of an ORing FET control circuit provided in an embodiment of the present application, wherein the ORing FET control circuit is connected between a power module and an output bus, and includes:
[0034] A field effect transistor Q5, wherein the source of the field effect transistor Q5 is connected to the power module, and the drain of the field effect transistor Q5 is connected to the output bus;
[0035] A first transistor Q1, wherein the emitter of the first transistor Q1 is connected to the source of the field effect transistor Q5, and the collector of the first transistor Q1 is connected to the gate of the field effect transistor Q5;
[0036] A second transistor Q2, wherein a first end of the second transistor Q2 is connected to the drain of the field effect transistor Q5, and a base and a second end of the second transistor Q2 are short-circuited;
[0037] A third triode Q3, wherein the collector of the third triode Q3 is connected to the base of the first triode Q1, and the base and emitter of the third triode Q3 are short-circuited;
[0038] A fourth triode Q4, wherein a first end of the fourth triode Q4 is connected to a base and an emitter of the second triode Q2, a base and a second end of the fourth triode Q4 are short-circuited, and connected to a base and an emitter of the third triode Q3;
[0039] The collector of the first transistor and the second end of the fourth transistor are connected to a working power supply.
[0040] It should be noted that, in the present embodiment, four triodes (bipolar transistors) are used to selectively control the on or off of the field effect transistor Q5. When comparing the source and drain voltages of the field effect transistor Q5, the base-collector voltage plus the base-emitter voltage of the two bipolar transistors is used to match the base-emitter voltage plus the base-collector voltage of the other two bipolar transistors. Compared with the technical solution of using two bipolar transistors in the related art and using the base-collector voltage of one bipolar transistor to match the base-emitter voltage of another bipolar transistor when comparing the source and drain voltages of the field effect transistor Q5, the two reference objects used to characterize the source voltage and the drain voltage of the field effect transistor Q5 in the present embodiment are more symmetrically matched, so that the field effect transistor Q5 can have a smaller threshold voltage (when the field effect transistor Q5 can be biased on, the minimum voltage drop between the output voltage of the power module and the output bus voltage is called the "threshold voltage" of the circuit), and the circuit has higher control sensitivity.
[0041] As an example, in this embodiment, when the first end of the second transistor Q2 is the collector, the first end of the fourth transistor Q4 is the emitter; when the first end of the second transistor Q2 is the emitter, the first end of the fourth transistor Q4 is the collector.
[0042] As an example, the working power supply in this embodiment can be realized by connecting an auxiliary power supply to a resistor, or can be realized by other feasible methods, which is not limited in this embodiment.
[0043] In some feasible embodiments, when the source voltage and the drain voltage of the field effect transistor Q5 are equal, the first bias voltage is equal to the second bias voltage; wherein the first bias voltage is the voltage between the base of the third transistor Q3 and the emitter of the first transistor Q1, and the second bias voltage is the voltage between the base of the fourth transistor Q4 and the first end of the second transistor Q2.
[0044] In this embodiment, the first bias voltage is the sum of the base-collector voltage of the third transistor Q3 and the base-emitter voltage of the first transistor Q1, and the second bias voltage is the sum of the voltage between the base and the first end of the fourth transistor Q4 and the voltage between the base and the first end of the second transistor Q2. Since the first end of the second transistor Q2 is the collector, the first end of the fourth transistor Q4 is the emitter, and the first end of the second transistor Q2 is the emitter, the first end of the fourth transistor Q4 is the collector. Therefore, it is equivalent to that the first bias voltage and the second bias voltage are both generated by the base-collector voltage of one transistor. The first bias voltage is obtained by adding the base-emitter voltage of a transistor. Since the four transistors are all transistors of the same type, when the source voltage and the drain voltage of the field effect transistor Q5 are equal, the first bias voltage and the second bias voltage are also equal. In the related art, the base-collector voltage of a bipolar transistor is matched with the base-emitter voltage of another bipolar transistor. Since the structures of the base-collector and the base-emitter of the transistor must be different, the solution in the related art still has an input offset, so that the threshold voltage of the field effect transistor Q5 and the circuit control sensitivity are not as good as the technical solution provided in this embodiment.
[0045] In some feasible embodiments, the collector of the first transistor Q1 is connected to the first bias current, the base of the fourth transistor Q4 is connected to the second bias current, and the gate voltage of the field effect transistor Q5 is determined according to the flow direction of the first bias current and the second bias current.
[0046] In this embodiment, as an example, the first bias current and the second bias current may be connected through a working power supply and a resistor, or may be directly given in other feasible ways, which is not limited in this embodiment.
[0047] In this embodiment, when the ORing FET control circuit is working, the on state of the field effect transistor Q5 is mainly determined by the difference between the input voltage of the power module and the output bus voltage. Depending on the difference between the input voltage of the power module and the output bus voltage, the bias state of the second transistor and the fourth transistor will be affected, thereby affecting the flow direction of the first bias current and the second bias current, and ultimately affecting the gate voltage of the field effect transistor Q5 and the conduction state between the source and drain.
[0048] In some feasible embodiments, when the source voltage of the field effect transistor Q5 is less than the drain voltage, the second transistor Q2 and the fourth transistor Q4 are reverse biased, so that the second bias current flowing into the base of the third transistor Q3 increases, the current flowing into the base of the first transistor Q1 increases, the first bias current increases, the collector voltage of the first transistor Q1 decreases, and the gate voltage of the field effect transistor Q5 is pulled down.
[0049] In this embodiment, the source voltage of the field effect transistor Q5 is less than the drain voltage, indicating that the input voltage of the power module is less than the output bus voltage. At this time, the ORing FET control circuit provided in this embodiment can lower the gate voltage of the field effect transistor Q5, so that the source and drain of the field effect transistor Q5 are cut off, thereby avoiding the backflow of bus current.
[0050] In some feasible embodiments, when the source voltage of the field effect transistor Q5 is greater than the drain voltage, the second transistor Q2 and the fourth transistor Q4 are forward biased, so that the second bias current flowing into the base of the third transistor Q3 is reduced, the current flowing into the base of the first transistor Q1 is reduced, the first bias current is reduced, the collector voltage of the first transistor Q1 is increased, and the gate voltage of the field effect transistor Q5 is pulled up.
[0051] In this embodiment, the source voltage of the field effect transistor Q5 is greater than the drain voltage, indicating that the input voltage of the power module is less than the output bus voltage. At this time, the ORing FET control circuit provided in this embodiment can increase the gate voltage of the field effect transistor Q5, so that the source and drain of the field effect transistor Q5 are conductive, thereby enabling the power module to output current to the output bus normally.
[0052] In some feasible embodiments, the first transistor Q1 and the second transistor Q2 are arranged in a first package, and the third transistor Q3 and the fourth transistor Q4 are arranged in a second package.
[0053] As an example, the first package and the second package are DFN2020-6 packages.
[0054] It should be noted that, in this embodiment, in order to further reduce the impact of device differences on the threshold voltage, the first transistor Q1 and the second transistor Q2 can be placed in the same DFN2020-6 package, and the third transistor Q3 and the fourth transistor Q4 can be placed in the same DFN2020-6 package, so that the ORing FET control circuit can obtain a lower threshold voltage and can potentially further increase the repeatability of the ORing FET control circuit.
[0055] In some feasible embodiments, the ORing FET control circuit further includes:
[0056] A first resistor R1, one end of the first resistor R1 is connected to the collector of the first transistor Q1;
[0057] a second resistor R2, one end of which is connected to the base of the fourth transistor Q4;
[0058] An auxiliary power supply VCC, the auxiliary power supply VCC is connected to the other end of the first resistor R1 and the other end of the second resistor R2, and the auxiliary power supply VCC is used to provide an operating voltage for the field effect transistor Q5, the first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4.
[0059] It can be understood that, in this embodiment, the auxiliary power supply VCC is the working power supply for supplying power to each transistor, the first bias current flows to the transistor through the first resistor R1, and the second bias current flows to the transistor through the second resistor R2.
[0060] Reference Figure 2 In some feasible embodiments, the first end of the second transistor Q2 is a collector, the second end of the second transistor Q2 is an emitter, the first end of the fourth transistor Q4 is an emitter, and the second end of the fourth transistor Q4 is a collector.
[0061] In this embodiment, if Figure 2 As shown, Figure 2 1 shows a node 120 of the power module output voltage and an output node 122 for providing voltage to the output bus; the field effect tube 102 is connected between the power module output voltage node 120 and the output bus voltage node 122, wherein the source of the field effect tube 102 is connected to the node 120, and the drain of the field effect tube 102 is connected to the output node 122; the emitter of the first transistor 104 is connected to the source of the field effect tube 102, and the collector of the first transistor 104 is connected to the gate of the field effect tube 102; the collector of the second transistor 106 is connected to the drain of the field effect tube 102, and the second transistor 106 is connected to the gate of the field effect tube 102. The base of transistor 106 is connected to the emitter of the second triode 106, connected in the form of a diode; the collector of the third triode 108 is connected to the base of the first triode 104, and the base of the third triode 108 is connected to the emitter of the third triode 108, connected in the form of a diode; the emitter of the fourth triode 110 is connected to the base and emitter of the second triode 106, and the base and collector of the fourth triode 110 are connected together, connected in the form of a diode; the base and collector of the fourth triode 110 are connected to the base and emitter of the third triode 108 together.
[0062] In this embodiment, the working power supply of the ORing FET control circuit is the auxiliary power supply ORing_Vcc, which is connected to the collector of the first transistor 104 through the first resistor 112; the auxiliary power supply ORing_Vcc is connected to the base and collector of the fourth transistor 110 through the second resistor 114, and the second resistor 114 is connected to the base and emitter of the third diode 108. When the ORing FET control circuit is working, the opening and closing of the field effect tube 102 is determined by the difference between the output voltage 120 of the power module and the output bus voltage 122.
[0063] When the output voltage 120 of the power module is lower than the bus voltage 122, the body diode of the field effect tube 102 is reverse biased. Since the voltage of the output bus is higher than the voltage of the power module at this time, the second transistor 106 and the fourth transistor 110 connected in the form of a diode are also reverse biased. At this time, the current flowing into the base and emitter of the third transistor 108 increases, thereby increasing the current flowing into the base of the first transistor 104; the collector current of the first transistor 104 increases and the collector voltage decreases, which pulls down the gate voltage of the field effect tube 102, and the field effect tube 102 is in a cut-off state, preventing the current of the output bus from flowing back into the power module.
[0064] When the power module voltage 120 is higher than the bus voltage 122, the body diode of the field effect tube 102 is forward biased. At this time, the second transistor 106 and the fourth transistor 110 connected in the form of a diode are also forward biased, and the current flowing through the second transistor 106 and the fourth transistor 110 increases; the current flowing into the base of the third transistor 108 decreases, resulting in a decrease in the collector current of the third transistor 108, which in turn causes the collector current of the first transistor 104 to decrease and the collector voltage to increase. When the collector voltage of the first transistor 104 increases, the gate voltage of the field effect tube 102 increases accordingly. When the gate turn-on voltage is reached, the field effect tube 102 is turned on, allowing current to flow from the power module to the output bus.
[0065] In this embodiment, the base-emitter voltage of the fourth transistor 110 and the base-collector voltage of the second transistor 106 can better match the base-collector voltage of the third transistor 108 and the base-emitter voltage of the first transistor 104, and the ORing FET control circuit can obtain a lower threshold voltage and more sensitive control.
[0066] In the ORing FET control circuit provided in this embodiment, when the second triode 106 adopts a diode connection mode, the base and emitter of the second triode 106 are short-circuited together; when the fourth triode 110 adopts a diode connection mode, the base and collector of the fourth triode 110 are short-circuited together. In other embodiments provided in this application, the second triode 106 can also short-circuit the base and collector together to form a diode connection mode, and the fourth triode 110 can also short-circuit the base and emitter together to form a diode connection mode.
[0067] Reference Figure 3 In some feasible embodiments, the first end of the second transistor Q2 is an emitter, the second end of the second transistor Q2 is a collector, the first end of the fourth transistor Q4 is a collector, and the second end of the fourth transistor Q4 is an emitter.
[0068] In this embodiment, if Figure 3 As shown, Figure 3 The figure shows a node 120 of the power module output voltage and an output node 122 for providing voltage to the output bus; the field effect tube 102 is connected between the power module output voltage node 120 and the output bus voltage node 122, wherein the source of the field effect tube 102 is connected to the node 120, and the drain of the field effect tube 102 is connected to the output node 122; the emitter of the first transistor 104 is connected to the source of the field effect tube 102, and the collector of the first transistor 104 is connected to the gate of the field effect tube 102; the emitter of the second transistor 106 is connected to the drain of the field effect tube 102, and the collector of the second transistor 106 is connected to the gate of the field effect tube 102. The base of transistor 106 is connected to the collector of the second triode 106, connected in the form of a diode; the collector of the third triode 108 is connected to the base of the first triode 104, and the base of the third triode 108 is connected to the emitter of the third triode 108, connected in the form of a diode; the collector of the fourth triode 110 is connected to the base and collector of the second triode 106, and the base and emitter of the fourth triode 110 are connected together, connected in the form of a diode; the base and emitter of the fourth triode 110 are connected together with the base and emitter of the third triode 108.
[0069] In this embodiment, the working power supply of the ORing FET control circuit is the auxiliary power supply ORing_Vcc, which is connected to the collector of the first transistor 104 through the first resistor 112; the auxiliary power supply ORing_Vcc is connected to the base and emitter of the fourth transistor 110 through the second resistor 114, and the second resistor 114 is connected to the base and emitter of the third diode 108. When the ORing FET control circuit is working, the opening and closing of the field effect tube 102 is determined by the difference between the output voltage 120 of the power module and the output bus voltage 122.
[0070] When the output voltage 120 of the power module is lower than the bus voltage 122, the body diode of the field effect tube 102 is reverse biased. Since the voltage of the output bus is higher than the voltage of the power module at this time, the second transistor 106 and the fourth transistor 110 connected in the form of a diode are also reverse biased. At this time, the current flowing into the base and emitter of the third transistor 108 increases, thereby increasing the current flowing into the base of the first transistor 104; the collector current of the first transistor 104 increases and the collector voltage decreases, which pulls down the gate voltage of the field effect tube 102, and the field effect tube 102 is in a cut-off state, preventing the current of the output bus from flowing back into the power module.
[0071] When the power module voltage 120 is higher than the bus voltage 122, the body diode of the field effect tube 102 is forward biased. At this time, the second transistor 106 and the fourth transistor 110 connected in the form of a diode are also forward biased, and the current flowing through the second transistor 106 and the fourth transistor 110 increases; the current flowing into the base of the third transistor 108 decreases, resulting in a decrease in the collector current of the third transistor 108, which in turn causes the collector current of the first transistor 104 to decrease and the collector voltage to increase. When the collector voltage of the first transistor 104 increases, the gate voltage of the field effect tube 102 increases accordingly. When the gate turn-on voltage is reached, the field effect tube 102 is turned on, allowing current to flow from the power module to the output bus.
[0072] In this embodiment, the base-collector voltage of the fourth transistor 110 and the base-emitter voltage of the second transistor 106 can better match the base-collector voltage of the third transistor 108 and the base-emitter voltage of the first transistor 104, and the ORing FET control circuit can obtain a lower threshold voltage and more sensitive control.
[0073] In the ORing FET control circuit provided in this embodiment, when the second triode 106 adopts a diode connection mode, the base and collector of the second triode 106 are short-circuited together; when the fourth triode 110 adopts a diode connection mode, the base and emitter of the fourth triode 110 are short-circuited together. In other embodiments provided in this application, the second triode 106 can also short-circuit the base and emitter together to form a diode connection mode, and the fourth triode 110 can also short-circuit the base and collector together to form a diode connection mode.
[0074] In addition, the present application also provides a power supply system, referring to Figure 4 The power supply system includes a power supply module 100, an output bus 202 and an ORing FET control circuit 200 provided in any one of the above embodiments.
[0075] In this embodiment, as an example, the power supply system includes at least one power supply module 100, which is connected to the output bus 202 through the above-mentioned ORing Fet control circuit 200, the output 120 of the power supply module 100 is connected to the input end of the corresponding ORing Fet control circuit 200, and the output end 122 of the ORing Fet control circuit 200 is connected to the output bus 202.
[0076] When the entire power system is operating normally, the voltage at the output 120 of each power module 100 is always slightly higher than the voltage at the input 122 of the output bus 202. Therefore, the field effect transistor in the corresponding ORing Fet control circuit 200 is in an on state, allowing the current of the power module 100 to flow to the output bus 202.
[0077] When one of the power modules 100 fails, the voltage at the output 120 of the corresponding power module 100 will be lower than the voltage at the input 122 of the output bus 202. At this time, the field effect transistor 102 in the corresponding ORing Fet control circuit is in the off state, preventing the current on the output bus from flowing back into the power module. Therefore, the problem of affecting the entire power system due to a single power failure in the power system can be effectively avoided.
[0078] Those skilled in the art will understand that Figure 4 The structure shown in the figure does not constitute a limitation on the power supply system, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.
[0079] The power supply system proposed in this embodiment and the ORing FET control circuit proposed in the above embodiments belong to the same inventive concept. The technical details not fully described in this embodiment can be referred to any of the above embodiments, and this embodiment has the same beneficial effects as the above embodiments of the ORing FET control circuit.
[0080] It should be noted that the technical solutions of the various embodiments of the embodiments of the present application can be combined with each other, but it must be based on the fact that they can be implemented by technical personnel in this field. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the embodiments of the present application.
[0081] The above are only optional embodiments of the embodiments of the present application, and do not limit the patent scope of the embodiments of the present application. Any equivalent structure or equivalent process transformation made using the description and drawings of the embodiments of the present application, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the embodiments of the present application.
Claims
1. An ORing FET control circuit, It is characterized in that The ORing FET control circuit is connected between the power module and the output bus, and the ORing FET control circuit includes: A field effect tube, wherein the source of the field effect tube is connected to the power module, and the drain of the field effect tube is connected to the output bus; A first triode, wherein the emitter of the first triode is connected to the source of the field effect tube, and the collector of the first triode is connected to the gate of the field effect tube; A second triode, wherein a first end of the second triode is connected to the drain of the field effect tube, and a base and a second end of the second triode are short-circuited; a third triode, wherein the collector of the third triode is connected to the base of the first triode, and the base and emitter of the third triode are short-circuited; A fourth triode, wherein the first end of the fourth triode is connected to the base and emitter of the second triode, the base and the second end of the fourth triode are short-circuited and connected to the base and emitter of the third triode.
2. The ORing FET control circuit as claimed in claim 1, It is characterized in that When the source voltage and the drain voltage of the field effect transistor are equal, the first bias voltage is equal to the second bias voltage; wherein the first bias voltage is the voltage between the base of the third transistor and the emitter of the first transistor, and the second bias voltage is the voltage between the base of the fourth transistor and the first end of the second transistor.
3. The ORing FET control circuit as claimed in claim 1, It is characterized in that The collector of the first transistor is connected to the first bias current, the base of the fourth transistor is connected to the second bias current, and the gate voltage of the field effect transistor is determined according to the flow direction of the first bias current and the second bias current.
4. The ORing FET control circuit as claimed in claim 3, It is characterized in that When the source voltage of the field effect transistor is less than the drain voltage, the second transistor and the fourth transistor are reverse biased, so that the second bias current flowing into the base of the third transistor increases, the current flowing into the base of the first transistor increases, the first bias current increases, the collector voltage of the first transistor decreases, and the gate voltage of the field effect transistor is pulled down.
5. The ORing FET control circuit as claimed in claim 3, It is characterized in that When the source voltage of the field effect transistor is greater than the drain voltage, the second transistor and the fourth transistor are forward biased, so that the second bias current flowing into the base of the third transistor is reduced, the current flowing into the base of the first transistor is reduced, the first bias current is reduced, the collector voltage of the first transistor is increased, and the gate voltage of the field effect transistor is pulled up.
6. The ORing FET control circuit as claimed in claim 1, It is characterized in that The first transistor and the second transistor are arranged in a first package, and the third transistor and the fourth transistor are arranged in a second package.
7. The ORing FET control circuit as claimed in claim 6, It is characterized in that The first package and the second package are DFN2020-6 packages.
8. The ORing FET control circuit as claimed in claim 1, It is characterized in that The first end of the second triode is a collector, the second end of the second triode is an emitter, the first end of the fourth triode is an emitter, and the second end of the fourth triode is a collector.
9. The ORing FET control circuit as claimed in claim 1, It is characterized in that The first end of the second triode is an emitter, the second end of the second triode is a collector, the first end of the fourth triode is a collector, and the second end of the fourth triode is an emitter.
10. The ORing FET control circuit as claimed in claim 1, It is characterized in that The ORing FET control circuit further includes: a first resistor, one end of which is connected to the collector of the first transistor; a second resistor, one end of which is connected to the base of the fourth transistor; An auxiliary power supply, the auxiliary power supply is connected to the other end of the first resistor and the other end of the second resistor, and the auxiliary power supply is used to power the field effect transistor, the first transistor, the second transistor, the third transistor and the fourth transistor.
11. A power supply system, It is characterized in that The power supply system comprises: a power supply module, an output bus and an ORing FET control circuit as claimed in any one of claims 1 to 10, wherein the power supply module is connected to the output bus via the ORing FET control circuit.