Clock detection circuit without external reference

Abstract

The invention discloses a clock detection circuit without external reference, which is characterized by comprising a logic control module, a detection module and a phase inverter, a control signal VCtrl is input to the phase inverter, the phase inverter outputs a signal VCtrlN, a signal Clock to be detected and the output of the phase inverter are input to the logic control module, the logic control module outputs a signal VC1 corresponding to the signal Clock and a signal VC2 corresponding to the signal VCtrlN, and the signals VC1 and VC2 are output to the detection module; and the detection module outputs a signal VOUT. The clock detection circuit does not need to be externally connected with a reference clock, the number of transistors in the circuit is small, and design is easier.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a clock detection circuit without an external reference. Background Art

[0002] At present, chips with clocks usually require detection circuits to provide feedback signals to the system. For example, in an RTC (Real Time Clock) chip, its internal crystal oscillator generates a 32.768KHz clock. The chip system needs a flag signal to ensure the normal operation of the circuit, but there is no additional reference clock inside the chip. Therefore, most existing clock detection circuits require a reference clock to detect the clock to be tested, and there are certain requirements for the reference clock frequency, and the detection circuit is relatively complex. Summary of the invention

[0003] Purpose of the invention: In order to solve the problems existing in the above-mentioned prior art, the present invention provides a clock detection circuit without external reference.

[0004] Technical solution: The present invention discloses a clock detection circuit without external reference, including: a logic control module, a detection module and an inverter; a control signal V Ctrl Input to the inverter, the inverter output signal V Ctrl_N , the measured signal Clock and the output of the inverter are input to the logic control module, and the logic control module performs a logic operation on the input signal and outputs a signal V corresponding to the signal Clock. C1 and signal V Ctrl_N The corresponding signal V C2 , and the signal V C1 and V C2 Output to the detection module; the detection module outputs a signal V OUT .

[0005] Furthermore, the detection module includes first to sixth MOS tubes and first and second capacitors, the source of the first MOS tube is connected to the power supply voltage VDD, and the gate is connected to the signal V C1 The drain is connected to the source of the second MOS tube and one end of the first capacitor, the other end of the first capacitor is grounded, and the gate of the second MOS tube is connected to the signal V C2 , the drain of the second MOS tube is connected to the drain of the fifth MOS tube, the drain of the sixth MOS tube, the gate of the fourth MOS tube and one end of the second capacitor, the gate of the fifth MOS tube is connected to the output end of the inverter, the source of the fifth MOS tube is connected to one end of the first current source, the other end of the first current source, the other end of the second capacitor, the source of the sixth MOS tube and the source of the fourth MOS tube are grounded, and the gate of the sixth MOS tube is connected to the control signal V CtrlThe drain of the fourth MOS tube is connected to the drain of the third MOS tube as the output end of the detection module, and the gate of the third MOS tube is connected to the control signal V Ctrl , the source of the third MOS tube is connected to one end of the second current source, and the other end of the second current source is connected to the power supply voltage VDD.

[0006] Furthermore, the first, second and third MOS tubes are POS tubes, and the fifth, fourth and sixth MOS tubes are NOS tubes.

[0007] Beneficial effects: The main advantages of the clock detection circuit without an external reference clock of the present invention are that it simplifies the circuit design and improves the stability of the system. First, the circuit of the present invention does not rely on an external reference clock signal, eliminates the need for an external clock source, reduces the complexity and cost of peripheral circuits, and its internal clock signal can be used as the basis for clock detection, which makes the system design more compact and suitable for space-constrained or cost-sensitive application scenarios; secondly, the design without an external reference clock enhances the system's adaptability. Since there is no need to rely on external signals, the circuit can be adjusted and optimized according to the internal clock dynamics, improving the system's adaptability to different working environments. In addition, this circuit reduces the interference and instability that may be caused by an external clock source, thereby improving the system's anti-interference ability and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a main block diagram of a clock detection circuit without external reference designed by the present invention;

[0009] Figure 2 It is a structural diagram of a clock detection circuit without external reference designed by the present invention;

[0010] Figure 3 This is the simulation diagram of the detection module when Clock has a clock pulse;

[0011] Figure 4 This is the simulation diagram of the detection module when there is no clock pulse in Clock. DETAILED DESCRIPTION

[0012] The accompanying drawings, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0013] like Figure 1 As shown, a clock detection circuit without external reference designed by the present invention includes a logic control module, a detection module, and an inverter module; the signal to be tested is recorded as Clock, and the control signal is recorded as V Ctrl ; The input terminal of the inverter module is connected to V Ctrl The output of the inverter is VCtrl_N The input of the logic control module is respectively connected to Clock and V Ctrl_N The logic control module performs logic operations on the input signal (if the clock detection circuit is turned off, the input signal can be made zero through logic control). The output of the logic control module is recorded as V C1 and V C2 ; The input of the detection module is respectively connected to V C1 and V C2 connected, the output of the detection module is recorded as V OUT .

[0014] like Figure 2 As shown, the detection module designed in the present invention includes a PMOS transistor PM1, a PMOS transistor PM2, a PMOS transistor PM3, an NMOS transistor NM1, an NMOS transistor NM2, an NMOS transistor NM3, a capacitor C1 and a capacitor C2.

[0015] The source of PM1 and one end of the current source I2 are connected to AVDD; the gate of PM1 is connected to the output V C1 The drain of PM1 is connected to the source of PM2 and the upper plate of capacitor C1; the gate of PM2 is connected to the output of the logic control V C2 The drain of PM2 is connected to the drain of NM1, the upper plate of C2, the drain of NM2, and the gate of NM3; the gate of NM1 is connected to the output V Ctrl_N The source of NM1 is connected to one end of the current source I1; the gate of NM2 is connected to V Ctrl The drain of NM3 is connected to the drain of PM3; the other end of I1, the lower plate of C1, the lower plate of C2, the source of NM2, the source of NM3 are connected to AVSS; the gate of PM3 is connected to V Ctrl The source of PM3 is connected to the other end of the current source I2.

[0016] When the control signal V Ctrl When V Ctrl_N is 0, PM1 and PM2 are turned off, NM1 is turned off, PM3 is turned off, NM2 is turned on, capacitor C2 is discharged to the ground, and the clock detection circuit is turned off; when the control signal V Ctrl When V Ctrl_N is 1, PM1 and PM2 are turned on, NM1 is turned on, PM3 is turned on, and NM2 is turned off. The clock detection circuit works normally. In the normal working mode of the clock detection circuit, when Clock has no clock output, the output V C1 With V C2 is 1, PM1 and PM2 are turned off, and the VOUT output flag is 1; when Clock has clock output, the output V C1 With VC2 It is a pair of anti-phase signals, outputting 0 and 1 alternately. C1 is 0, V C2 When it is 1, PM1 is turned on, PM2 is turned off, VDD charges capacitor C1, and when V C1 =1, V C2 When it is 0, PM1 is turned off, PM2 is turned on, capacitor C1 is used as a power source to charge capacitor C2, and the potential of capacitor C2 gradually increases to turn on NM3, V OUT Output flag bit 0.

[0017] like Figure 3 As shown in the simulation diagram of the clock detection circuit without external reference designed by the present invention, when the output Clock has a clock pulse, the output V OUT is 0V.

[0018] like Figure 4 As shown in the simulation diagram of the clock detection circuit without external reference designed by the present invention, when the output Clock has no clock pulse, the output V OUT is 1.8V.

[0019] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

Claims

1. A clock detection circuit without external reference, characterized in that: include: Logic control module, detection module and inverter; The control signal V Ctrl Input to the inverter, the inverter output signal V Ctrl_N , the measured signal Clock and the output of the inverter are input to the logic control module, and the logic control module performs a logic operation on the input signal and outputs a signal V corresponding to the signal Clock. C1 and signal V Ctrl_N The corresponding signal V C2 , and the signal V C1 and V C2 Output to the detection module; the detection module outputs a signal V OUT .

2. A clock detection circuit without external reference according to claim 1, characterized in that: The detection module includes first to sixth MOS tubes and first and second capacitors. The source of the first MOS tube is connected to the power supply voltage VDD, and the gate is connected to the signal V C1 The drain is connected to the source of the second MOS tube and one end of the first capacitor, the other end of the first capacitor is grounded, and the gate of the second MOS tube is connected to the signal V C2 , the drain of the second MOS tube is connected to the drain of the fifth MOS tube, the drain of the sixth MOS tube, the gate of the fourth MOS tube and one end of the second capacitor, the gate of the fifth MOS tube is connected to the output end of the inverter, the source of the fifth MOS tube is connected to one end of the first current source, the other end of the first current source, the other end of the second capacitor, the source of the sixth MOS tube and the source of the fourth MOS tube are grounded, and the gate of the sixth MOS tube is connected to the control signal V Ctrl The drain of the fourth MOS tube is connected to the drain of the third MOS tube as the output end of the detection module, and the gate of the third MOS tube is connected to the control signal V Ctrl , the source of the third MOS tube is connected to one end of the second current source, and the other end of the second current source is connected to the power supply voltage VDD.

3. A clock detection circuit without external reference according to claim 2, characterized in that: The first, second and third MOS tubes are POS tubes, and the fifth, fourth and sixth MOS tubes are NOS tubes.

Images