VCO-based continuous time pipeline ADC

Abstract

The invention relates to a VCO-based continuous time pipeline ADC. Compared with other ADC architectures, the VCO ADC consumes less power and occupies a small area. However, when the VCO ADCs are implemented separately, the bandwidth and performance of the VCO ADCs may be limited. To address these issues, a VCO ADC is implemented as a back end stage in a VCO-based continuous time (CT) pipeline ADC, where the VCO-based CT pipeline ADC has a CT residue producing front end. Optionally, the VCO ADC backend may perform phase interpolation to improve its bandwidth. The pipeline architecture greatly improves the performance of the rear end of the VCO ADC, and the whole VCO-based CT pipeline ADC is simpler than a traditional continuous time pipeline ADC.

Description

[0001] This application is a divisional application of the application filed on May 22, 2020, with application number 202010439313.2 and invention name “VCO-based continuous-time pipeline ADC”. Technical Field

[0002] The present disclosure relates generally to analog-to-digital converters (ADCs), and more particularly to voltage controlled oscillator (VCO) based continuous time (CT) pipeline ADCs. Background Art

[0003] In many electronic applications, analog input signals are converted into digital output signals (e.g., for further digital signal processing). For example, in a precision measurement system, an electronic device is provided with one or more sensors for measurement, and these sensors can generate analog signals. The analog signal is then provided as input to an ADC to generate a digital output signal for further processing. In another example, an antenna generates an analog signal based on electromagnetic waves that carry information / signals in the air. The analog signal generated by the antenna is then provided as input to an ADC to generate a digital output signal for further processing.

[0004] ADCs can be found in many places, such as broadband communication systems, audio systems, receiver systems, etc. ADCs can convert analog electrical signals representing real phenomena, such as light, sound, temperature, or pressure, for data processing. ADCs have a wide range of applications, including communications, energy, healthcare, instrumentation and measurement, motor and power control, industrial automation, and aerospace / defense. Designing ADCs is a difficult task because each application may have different requirements in terms of speed, performance, power consumption, cost, and size. As the number of applications requiring ADCs grows, the demand for accurate and reliable conversion performance also increases.

[0005] An ADC is an electronic device that converts a continuous physical quantity carried by an analog signal into a digital number representing the magnitude of that quantity (or into a digital signal carrying that digital quantity). This conversion involves quantization of the analog input signal, and therefore introduces a small amount of error. Typically, quantization is performed by periodically sampling the analog input signal. The result is a series of digital values ​​(i.e., a digital signal) that has converted the CT and continuous amplitude analog input signal into a discrete time and discrete amplitude digital signal. An ADC can be defined by the following application requirements: its bandwidth (the frequency range of the analog signal that can be correctly converted to a digital signal) and its resolution (the number of discrete levels that the maximum analog signal can be divided into and represented by a digital signal). ADCs also have various specifications used to quantify the dynamic performance of the ADC, including signal-to-noise ratio (SINAD), effective number of bits (ENOB), signal-to-noise ratio (SNR), signal-to-noise ratio (SQNR), noise spectral density (NSD), total harmonic distortion (THD), total harmonic distortion plus noise (THD+N), and spurious-free dynamic range (SFDR). ADCs have many different designs that can be selected based on application requirements and performance specifications. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] To provide a more complete understanding of the present disclosure and its features and advantages, reference is made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts, and wherein:

[0007] Figure 1 is an illustrative system diagram of a VCO-based CT pipeline ADC with a CT residual generation front end and a CT VCO ADC back end according to some embodiments of the present disclosure;

[0008] Figure 2 An exemplary implementation of a VCO-based CT pipeline ADC with a CT residual generation front end and a CT VCO ADC back end according to some embodiments of the present disclosure is shown;

[0009] Figure 3 An exemplary digital signal reconstruction filter and a scheme for programming the digital signal reconstruction filter according to some embodiments of the present disclosure are shown;

[0010] Figure 4 An exemplary implementation of a VCO-based CT pipeline ADC with a CT residual generation front end and a CT VCO ADC back end according to some embodiments of the present disclosure is shown;

[0011] Figure 5-10 Various implementations of CT delay lines according to some embodiments of the present disclosure are shown;

[0012] Fig.11shows an exemplary implementation of a CT residual generation front end with digital-to-analog converter pulse shaping according to some embodiments of the present disclosure;

[0013] Fig.12 A nonlinear calibration filter and a scheme for programming the nonlinear calibration filter according to some embodiments of the present disclosure are shown;

[0014] Fig.13 An exemplary implementation of a CT VCO ADC back end with two pseudo differential signal paths and a replica signal path according to some embodiments of the present disclosure is shown;

[0015] Fig.14 An exemplary implementation of a CT VCO ADC back end with two pairs of pseudo differential signal paths according to some embodiments of the present disclosure is shown;

[0016] Fig.15 An exemplary phase interpolating ring oscillator according to some embodiments of the present disclosure is shown;

[0017] Fig.16 An exemplary implementation of a VCO-based CT pipeline ADC with a CT residue generation front end and an oversampled CT VCO ADC back end according to some embodiments of the present disclosure is shown;

[0018] Fig.17 shows an exemplary implementation of a high-order CT VCO ADC back end according to some embodiments of the present disclosure;

[0019] Fig.18 An exemplary implementation of a VCO-based CT pipeline ADC with a reconfigurable CT residual generation front end and a CTVCO ADC back end according to some embodiments of the present disclosure is shown;

[0020] Fig.19 is a flow chart illustrating a method for pipelined analog-to-digital conversion according to some embodiments of the present disclosure;

[0021] Fig. 20 shows various implementations of CT delay lines according to some embodiments of the present disclosure; and

[0022] Fig.21 An exemplary implementation of a CT delay line according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0023] Overview

[0024] Compared with other ADC architectures, VCO ADC consumes relatively less power and occupies less area. However, when VCO ADC is implemented alone, the bandwidth and performance of VCO ADC can be limited. To address these issues, VCO ADC is implemented as a back-end stage in a VCO-based continuous time (CT) pipeline ADC, where the VCO-based CT pipeline ADC has a CT residual generation front end. Optionally, the VCO ADC back end can perform phase interpolation to improve its bandwidth. The pipeline architecture greatly improves the performance of the VCO ADC back end, and the overall VCO-based CT pipeline ADC is simpler than the traditional continuous time pipeline ADC. In addition, implementing a continuous time pipeline ADC is not a trivial task. For example, a unique digital signal reconstruction filter is implemented and programmed to combine the digital signals of the continuous time residual generation front end and the VCO ADC back end and generate the final digital output.

[0025] Limitations of VCOADC

[0026] VCO ADCs are (mostly digital) CT ADCs. A VCO ADC consists in series of: a ring oscillator, a phase-to-digital converter, and a differentiator. The analog input signal drives the ring oscillator, and the differentiator outputs a digital signal, which is a quantized version of the analog input signal.

[0027] The ring oscillator may include a voltage-controlled ring oscillator. For example, the ring oscillator may be implemented with an odd number of inverters connected in a ring. The switching delay of each inverter depends on the input voltage of the ring oscillator. The ring oscillator may generate phase information of the analog input signal to the VCOADC. In some cases, the voltage-controlled ring oscillator is implemented by using a voltage-to-current converter followed by a current-controlled ring oscillator. The voltage-to-current converter converts the analog input voltage signal into a current signal. The current signal then drives the current-controlled ring oscillator. The current-controlled ring oscillator may include an odd number of current-deficient inverters in a ring.

[0028] The output of the inverter having phase information of the analog input signal to the VCO ADC can be observed to derive the voltage of the analog input signal. Specifically, the voltage of the analog input signal can be extracted based on how the phase changes from one cycle to another. The phase-to-digital converter can sample and quantize the phase of the VCO (e.g., the phase of the analog input signal to the VCO ADC). For example, the phase-to-digital converter may include: a ring sampler for sampling the output of the inverter (e.g., observing the transitions of the inverter); and a phase decoder for decoding or mapping the output of the ring sampler into a phase number. The phase decoder generates a digital phase signal representing the phase of the VCO. The digital phase signal is provided to a (digital) differentiator, which may have a transfer function 1-z -1 The differentiator differentiates the digital phase signal and outputs a digital signal that is a quantized version of the analog input signal to the VCO ADC.

[0029] Due to its simple circuit design, the VCO ADC has the characteristics of low power consumption and compact area. The ring oscillator is the analog circuit of the VCO ADC, and the other components following the ring oscillator are digital blocks. The final circuit of the VCO ADC is very compact because many analog circuits commonly found in other ADCs, such as flash ADCs, digital-to-analog converters (DACs), and amplifiers, are not present in the VCO ADC. Instead, the VCO ADC only requires a ring oscillator, which can be implemented with simple small complementary metal oxide semiconductor (CMOS) inverters. The digital blocks implemented in the CMOS process can be very compact, especially when the VCO ADC is implemented in smaller process nodes.

[0030] A VCO ADC can be considered a type of CT ADC because the analog input signal to the VCO ADC drives a ring oscillator that has only a CT circuit. In other words, the analog input signal to the VCO ADC is not sampled by a sampler, i.e., the ring oscillator does not have a switched capacitor circuit that samples the input signal onto one or more capacitors.

[0031] Since the analog input signal of the VCO ADC is derived as a voltage using differential, the VCO ADC has first-order noise shaping. This means that a high-resolution VCO ADC can be achieved at or near DC (DC stands for direct current, where the signal frequency is zero). However, since it is difficult to observe the signal at the sampling frequency, the resolution is limited to the sampling frequency of the VCO ADC.

[0032] Moreover, even if the circuit in the ring oscillator is ideal, the ring oscillator has inherent system nonlinearity. Specifically, converting the analog input signal to frequency to obtain phase information is a very nonlinear process and will compromise the linearity of the entire VCO ADC. Therefore, digital nonlinear correction is implemented to address the nonlinearity issue. However, even with digital nonlinear correction, limitations on NSD, SNR, and SQNR can still be achieved for the VCO ADC.

[0033] Therefore, VCO ADCs are usually suitable for applications with (1) up to limited frequency (e.g., 1MHz bandwidth), (2) NSD > -150dBFS / Hz, and / or (3) HD2 (second-order harmonic) or HD3 (third-order harmonic) > -80dBFS. Many high-speed, wideband applications cannot use VCO ADCs.

[0034] Limitations of CT Pipeline ADCs

[0035] The CT pipeline ADC has N cascaded stages. For stage 1 to stage N-1, each stage has a coarse ADC to generate a digital output signal and a circuit to generate an amplified residual signal for processing by the next stage (the residual signal is the amplified difference between the analog input signal of the stage and the reconstructed analog input signal of the stage). The N stage has an ADC, such as a flash ADC including a set of comparators, to generate the final digital output signal. The digital output signals of all stages are combined by a digital signal reconstruction filter to generate the final digital output signal. The stage has a CT circuit and does not include a sampler (e.g., a switched capacitor circuit).

[0036] When a large number of cascaded stages are implemented, such as N>2, the CT pipeline ADC can achieve low noise (e.g., NSD<-160dBFS / Hz) and low distortion. Usually, 3 or more stages are implemented to achieve the target performance. However, when the continuous-time pipeline ADC has a large number of cascaded stages, the circuit takes up a lot of silicon area and consumes a lot of power. In addition, the large number of cascaded stages may result in a complex digital signal reconstruction filter if perfect signal reconstruction is to be achieved. For N stages in the CT pipeline ADC, N-1 finite impulse response (FIR) filters are usually implemented in the digital signal reconstruction filter. Therefore, the more stages the CT pipeline ADC has, the more FIR filters are required in the digital signal reconstruction filter.

[0037] VCO-Based CT Pipeline ADC

[0038] The limitations of VCO ADCs and CT pipeline ADCs with many cascaded stages can be alleviated when a CT pipeline ADC is implemented using a CT residue generation front end and a CT VCO ADC back end (referred to herein as a VCO-based CT pipeline ADC). The VCO-based CT pipeline ADC is different from the CT pipeline ADC in that the back end of the VCO-based CT pipeline ADC is not implemented using a flash ADC or a successive approximation register ADC. The VCO-based CT pipeline ADC realizes the unexpected benefits of the CT residue generation front end and the CT VCO ADC back end, which are not available in the VCO ADC or the CT pipeline ADC. In addition, unique challenges arise when the CT residue generation front end is used in conjunction with the CT VCO ADC back end.

[0039] Figure 1 1 is an illustrative system diagram of a VCO-based CT pipeline ADC 100 having a CT residue generation front end and a CT VCO ADC back end according to some embodiments of the present disclosure. The VCO-based CT pipeline ADC 100 includes: a CT residue generation front end 102, a CT VCO ADC back end 104, and a digital signal reconstruction filter 108. The CT residue generation front end 102 quantizes or digitizes the analog input signal v in And generate a first digital signal D 1 and the amplified residual signal v a_res The CT VCO ADC backend 104 quantizes or digitizes the amplified residual signal and generates a second digital signal D VCOADC The digital signal reconstruction filter 108 performs a reconstruction of the first digital signal D 1 and the second digital signal D VCOADC Filtering is performed to produce the final digital signal D OUT .

[0040] Optionally, the CT VCO ADC backend 104 includes a digital nonlinearity correction block 106 to correct the nonlinearity of the CT VCO ADC backend 104 (or more specifically, the VCO ADC 210). The digital nonlinearity correction block 106 outputs the corrected output as the second digital signal D VCOADC Provided to the digital signal reconstruction filter 108.

[0041] First, limitations such as nonlinearity and noise of the CT VCO ADC backend 104 are mitigated by the gain or amplification implemented in the CT residual generation frontend 102. Specifically, by suppressing the gain of the CT residual generation frontend 102, the NSD of the CT VCO ADC backend 104 is suppressed. Note that the CT residual generation frontend 102 generates a residual signal and amplifies the residual signal v a_resThe residual signal v is provided to the CT VCO ADC back end 104 to eliminate the basic components of the large signal. As a result, the amplified residual signal v is processed by the CT VCO ADC back end 104. a_res The introduced distortion is limited or reduced. Therefore, the VCO-based CT pipeline ADC 100 can be designed so that the NSD of the CT residual generation front end 102 dominates the overall NSD. This means that the VCO-based CT pipeline ADC 100 can achieve the same NSD as the CT pipeline ADC, and the poor NSD of the VCO ADC itself will not become a limiting factor in the design of the VCO-based CT pipeline ADC 100.

[0042] Secondly, using the CT VCO ADC back end 104, which has a higher resolution compared to the N stages of the CT pipeline ADC, means that the number of stages and design complexity of the VCO-based CT pipeline ADC 100 can be reduced while still being able to achieve the same resolution as the CT pipeline ADC. As a result, the limitations associated with a CT pipeline ADC with many stages, such as area overhead, complexity of the digital signal reconstruction filter, and higher power consumption, are mitigated by implementing a VCO-based CT pipeline ADC 100 that has fewer pipeline stages to achieve the same target resolution and has a simpler circuit due to the smaller and simpler circuit design of the CT VCO ADC back end 104. In short, the VCO-based CT pipeline ADC 100 can have lower power, smaller silicon area, and simpler digital signal processing (i.e., processed in the digital signal reconstruction filter) than a CT pipeline ADC with the same target resolution.

[0043] Third, the CT VCO ADC backend 104 provides a sinusoidal response, while the Flash ADC at the end of the CT pipeline ADC does not have a sinusoidal response. The sinusoidal response of the CT VCO ADC backend 104 can provide additional anti-aliasing advantages.

[0044] The VCO-based pipeline ADC 100 and other embodiments herein have additional benefits compared to other ADC architectures, which will be described in more detail herein.

[0045] Figure 2An exemplary implementation of a VCO-based CT pipeline ADC 200 with a CT residual generation front end 102 and a CT VCO ADC back end 104 is shown according to some embodiments of the present disclosure. The CT residual generation front end 102 may include a quantizer 202, a DAC 204, a delay circuit 206, a node 280, and a residue amplifier 208. The CT VCO ADC back end 104 may include a VCO ADC 210. The VCO ADC 210 may optionally include a digital nonlinearity correction block 106. The digital signal reconstruction filter 108 may include a first filter 212, a second filter 214, and a node 218.

[0046] Quantizer 202 receives an analog input signal v in , and generates a first digital signal D by performing analog-to-digital conversion 1 Quantizer 202 may be an ADC, such as a flash ADC including a set of comparators, to convert the analog input signal v in The first digital signal D is compared with a plurality of reference voltages. 1 is provided to the digital signal reconstruction filter 108 .

[0047] DAC 204 receives the first digital signal D 1 , and generates a first reconstructed analog signal at the output of DAC 204 by performing digital-to-analog conversion. DAC 204 converts the first digital signal D 1 Generate a first reconstructed analog signal to reconstruct the analog input signal v in The DAC 204 may be a current mode DAC that generates a current signal, or a voltage mode DAC that generates a voltage signal.

[0048] The delay circuit 206 delays the first analog input signal (eg, the analog input signal v in ) is delayed to the quantizer 202 and generates a first delayed analog input signal. The response of the delay circuit 206 preferably matches the response of the signal path having the quantizer 202 and the DAC 204. Figure 4-10 Details and illustrative examples of delay circuit 206 are provided in and 20-21, and descriptions of Figure 4-10 and paragraphs 20-21.

[0049] Node 280 may perform a subtraction / differentiation to output a residual signal representing the difference between the first delayed analog input signal from delay circuit 206 and the first reconstructed analog signal from DAC 204. Ideally, the first residual signal represents the quantization error of quantizer 202. Node 280 may perform a voltage mode subtraction or a current mode subtraction.

[0050] The residue amplifier 208 amplifies the residue signal from the node 280 and generates an amplified residue signal v a_res The residual amplifier 208 may apply a gain greater than 1 to the first residual signal generated at the node 280. In some cases, the residual amplifier 208 is a filter having a filter response, for example, the residual amplifier 208 may have a dynamic characteristic. This means that the amplified residual signal v a_res The residual signal may be a filtered residual signal. In some cases, the applied gain may not be identical or consistent in frequency. Therefore, residual amplifier 208 performs a filtering function (except applying gain to increase the first residual signal generated by node 280). In some embodiments, residual amplifier 208 has a low-pass response. In some embodiments, residual amplifier 208 has a high-pass response. In some embodiments, residual amplifier 208 has a band-pass response. In some embodiments, residual amplifier 208 has a first-order response. In some embodiments, residual amplifier 208 has a second-order or higher-order response.

[0051] VCO ADC 210 receives and processes the amplified residual signal v a_res The VCO ADC 210 can quantize the amplified residual signal v a_res The (optional) digital nonlinearity correction block 106 can correct the nonlinearity of the VCO ADC 210. The digital nonlinearity correction block 106 outputs the corrected output as the second digital signal D VCOADC Provided to the digital signal reconstruction filter 108.

[0052] The first filter 212 (shown as G) of the digital signal reconstruction filter 108 1 ) can be used for the first digital signal D 1 The second filter 214 (shown as G) of the digital signal reconstruction filter 108 2 ) can be used for the second digital signal D VCOADC Node 218 can combine the outputs of the first filter 212 and the second filter 214 to generate a digital signal D OUT .exist Figure 3 In and in the description Figure 3 Details and illustrative examples of the digital signal reconstruction filter 108 are provided in the section .

[0053] Digital signal reconstruction filter

[0054] The digital signal reconstruction filter 108 is unique to the VCO-based CT pipeline ADC. Moreover, the digital signal reconstruction filter 108 is not trivial because the implementation and behavior of the CT circuit in the VCO-based CT pipeline ADC complicates the digital signal reconstruction. The behavior or response of the CT circuit is hidden.

[0055] One of the technical tasks of the digital signal reconstruction filter 108 is to remove the quantization noise introduced by the CT residual generation front end 102, in particular the quantization noise introduced by the quantizer 202. When the digital signal reconstruction filter 108 is properly programmed, the quantization noise introduced into the CT residual generation front end 102 can be reduced in the final digital signal D OUT Eliminate. Assume:

[0056] The circuit in the CT residue generation front end 102 that generates the residue signal (before amplification by the residue amplifier 208) has a signal transfer function STF CTRES , Noise Transfer Function NTF CTRES and quantization noise q CTRES ,

[0057] The residue amplifier 208 amplifies the residue signal to generate an amplified residue signal having a signal transfer function STF RA ,

[0058] The CT VCO ADC backend 104 has a signal transfer function STF VCOADC , Noise Transfer Function NTF VCOADC and quantization noise q VCOADC ,

[0059] The transfer function of the first filter 212 is G 1 ,

[0060] The transfer function of the second filter 214 is G 2 .

[0061] Figure 2 The characteristics of the signal processing in the digital signal reconstruction filter 108 are as follows:

[0062] D OUT =D 1 ·G 1 -D VCOADC ·G 2 (Equation 1)

[0063] In addition, D 1 and D VCOADC The above transfer function is characterized as follows:

[0064] D 1 =v in ·STF CTRES +q CTRES ·NTF CTRES (Equation 2)

[0065] D VCOADC =q CTRES ·STFRA ·STF VcOADC +q VCOADC ·NTF VCOADC (Equation 3)

[0066] Plugging equations 2 and 3 into equation 1 yields:

[0067] D OUT = {v in ·STF CTRES +q CTRES ·NTF CTRES}·G 1

[0068] -{q CTRES ·STF RA ·STF VCOADC +q VCOADC ·NTF VCOADC}·G 2

[0069] =v in ·STF CTRES ·G 1 +q CTRES ·NTF CTRES ·G 1

[0070] -q CTRES ·STF RA ·STF VCOADc ·G 2 +q VCOADC ·NTF VCOADC ·G 2 (Equation 4)

[0071] Note that in the following case, the noise q CTRES The term (introduced by the CT residual generation front end 102) can be cancelled (or brought to zero):

[0072] q CTRES ·NTF CTRES ·G 1 =q CTRES ·STF RA ·STF VCOADC ·G 2 (Equation 5)

[0073] Rewriting equation 5 yields:

[0074]

[0075] This means that if the first filter 212 (i.e., the transfer function G 1 ) and the second filter 214 (ie, the transfer function G2 ) corresponds to the signal transfer function STF of the residual amplifier that generates the amplified residual signal in (1) RA , (2) the signal transfer function SfF at the back end of the VCO ADC VCOADC , and (3) the noise transfer function NTF of the CT residue generation front end 102 CTRES , with quantization noise q CTRES will be canceled in the final digital output D OUT . Specifically, if the ratio satisfies Equation 6, the term with quantization noise q CTRES will be canceled and will not appear in the final digital output D OUT .

[0076] In the present disclosure, "the ratio corresponds to {multiple functions}" means that X has a correspondence, match, or association with one or more of {multiple functions}. The correspondence may not be exact. The correspondence can be an approximation. In some cases, the ratio can be composed of one or more of the following in a certain form or in a suitable combination: {multiple functions}.

[0077] Therefore, according to Equation 6, the design of the digital signal reconstruction filter 108 sets a constraint on the ratio: G 1 / G 2, however, the design does not specify the specific responses of the first filter and the second filter (i.e., G 1 and G 2 ). There are several possible solutions for G 1 and G 2 that will satisfy Equation 6.

[0078] In some cases, G 1 = STF RA · STF VCOADC , G 2 = NTF CTRES .

[0079] In some cases, G 1 = NTF CTRES , G 1 = NTF CTRES / STF RA · STF VCOADC .

[0080] Note that due to the structure of the CT residue generation front end 102, there is no noise shaping in the CT residue generation front end 102. Therefore, NTF CTREE = 1, or the noise transfer function NTF of the CT residue generation front end 102 CTRESThe noise transfer function NTF of the CT residual generation front end 102 may be approximately 1 (eg, CTRES has a flat frequency response). Therefore, Equation 6 becomes:

[0081]

[0082] In some cases, G 1 =STF RA ·STF VCOADC , G 2 =1.

[0083] In some cases, G 1 =1, G 2 =1 / STFR A ·STF VCOADC .

[0084] This means that if the first filter 212 (i.e., the transfer function G 1 ) and the second filter 214 (ie, the transfer function G 2 ) corresponds to the signal transfer function STF of the residual amplifier that produces the amplified residual signal (1). RA , (2) Signal transfer function STF of VCO ADC backend VCOADC .

[0085] Another technical task is that the digital signal reconstruction filter 108 can ensure that the first digital signal D 1 Not the final digital output D OUT This means that the digital signal reconstruction filter 108 can reconstruct the analog input signal v in Based on the digital signal (the first digital signal D 1 and the second digital signal D VCOADC ) forms the final digital signal D of the final converter OUT , the final digital signal D OUT Accurately represents the analog input signal v in way.

[0086] In some embodiments, the digital signal reconstruction filter 108 can make the first digital signal D 1 Towards the final digital output D OUT When the results from the equal and opposite signal paths are added together, the digital signal reconstruction filter 108 can ensure that the final digital output D OUT The first digital signal D is canceled out. 1 Contribution. With transfer function G 1 The first filter 212 is a first digital signal D 1 Output D to the final numberOUT A first signal path is provided. Having a transfer function G 2 The second filter 214 is the first digital signal D 1 Towards the final digital output D OUT Specifically, the second and reverse signal path includes the DAC 204, the residual amplifier 208, the CT VCO ADC back end 104 and the second filter 214. Assume that the first digital signal D 1 and the second digital signal D VCOADC The relevant transfer function is characterized by G 1 / G 2 , then the second and opposite signal path has a significant impact on the first digital signal D 1 To the final digital output D OUT The transfer function is G 1 / G 2 and -G 1 (the negative sign comes from the subtraction in node 218), that is, {G 1 / G 2}·-G 2 =-G 1 This means that the transfer function of the first signal path is equal and opposite to the transfer function of the second and opposite signal path, i.e. G 1 Equal to and equal to -G 1 Therefore, after the outputs of the first filter 212 and the second filter 214 are combined at the node 218, the first digital signal D 1 The contribution of is canceled and removed from the final digital output D OUT In other words, the first digital signal D 1 The final digital output D of the reconstruction OUT No contribution. It can be understood that, with the first digital signal D 1 and the second digital signal D VCOADC The relevant transfer function is characterized by G 1 / G 2 , for example, when G 1 =STF VCOADC ·STF RA and G 2 =1. The first digital signal D 1 and the second digital signal D VCOADC The signal path is connected through the DAC 204, the residual amplifier 208 and the CT VCOADC back end 104. 1 and the second digital signal D VCOADC The relevant transfer function can be expressed as the signal transfer function STF of the residual amplifier 208 RAand the signal transfer function STF of the CT VCO ADC backend 104 VCOADC to represent a combination of .

[0087] In fact, the first filter 212 (having a transfer function G 1 ) and a second filter 214 (having a transfer function G 2 ) is a digital filter programmed with a digital approximation of the actual transfer function. For a VCO-based CT pipeline ADC, determining the digital version of the transfer function is not an easy task because the transfer function of the CT circuit is hidden and may not be well characterized. In addition, if the digital version of the actual transfer function does not exactly match the actual version of the transfer function, quantization noise leakage occurs:

[0088] D OUT = {u in ·STF CTRES +q CTRES ·NTF CTRES}·G 1

[0089] -{q CTRES ·STF RA ·STF VCOADC +q VCOADC ·NTF VCOADC}·G 2

[0090] =v in ·STF CTRES DSTF VCOADC DSTF RA

[0091] +q CTRES ·NTF CTRES DSTF VCOADC DSTF RA

[0092] -q CTRES ·STF RA ·STF VCOADC DNTF CTRES

[0093] +q VCOADC ·NTF VCOADC DNTF CTRES (Equation 8)

[0094] Note that if DSTF VCOADC ≠STF VCOADC DSTF RA ≠STF RA and DNTF CTRES ≠NTFCTRES , then the CT residual generates the quantization noise q of the front end 102 CTRES The terms will not be cancelled.

[0095] Figure 3 An exemplary digital signal reconstruction filter 108 and a scheme for programming the digital signal reconstruction filter 108 according to some embodiments of the present disclosure are shown. The technical task of programming the first filter 212 (and / or the second filter 214) is to determine a digital filter that can effectively process the first digital signal D in the digital domain. 1 and the second digital signal D VCOADC In the example shown, the first filter 212 (ie, the transfer function G 1 ) may correspond to the residual amplifier 208 (DSTF RA ) of the digital version of the signal transfer function and the CT VCO ADC back end 104 (DSTF VCOADC ) is a digital version of the signal transfer function:

[0096] G 1 =DSTF RA DSTF VCOADC (Equation 9)

[0097] The second filter 214 (i.e., the transfer function G 2 ) may correspond to the CT residual generation front end 102 (DNTF CTRES ) is a digital version of the noise transfer function:

[0098] G 2 =DNTF CTRES ≈1 (Equation 10)

[0099] As seen in Equation 9, the signal transfer function of the VCO-based CT pipeline ADC 300 is not always well defined and may vary over time during operation or from one integrated circuit to another. In order to determine the digital version of the signal transfer function of the residual amplifier and the digital version of the signal transfer function of the CT VCO ADC back end 104, i.e., the DSTF RA and DSTF VCOADC , and a known signal or jitter may be injected at the input of the residual amplifier 208. The known signal or jitter may be injected in the digital domain from the second digital signal D VCOADC Information about the signal transfer function can be extracted by observing how a known signal is affected by the signal path.

[0100] For example, the known signal or jitter can be a maximum length linear feedback shift register (LFSR) sequence whose cross-correlation approximates the impulse response. The injected maximum length LFSR sequence and the second digital signal D can be performed in the background. VCOADC to estimate the signal transfer function of the residual amplifier 208 and the signal transfer function of the CT VCO ADC back end 104 and obtain the DSTF RA and DSTF VCOADC .

[0101] The cross-correlation used in this paper refers to a measure of the similarity between a pair of signals:

[0102]

[0103] L represents the lag, and n is the time index. Therefore, the cross-correlation is the accumulation of the signal product in time, which is equivalent to the convolution of x[n] and y[-n], or the product where k is the frequency. Cross correlation is the sliding dot product or sliding inner product of two digital signals.

[0104] One bit of jitter generated by a maximum length LFSR sequence may be injected into the input of the residue amplifier 208. Figure 3 , a dithered LFSR may be injected into the DAC 204 (e.g., by adding dither to the output of the DAC 204, or by modifying the input bits of the DAC 204 based on the dither so that dither is added to the output of the DAC 204). The dithered LFSR may be generated in the digital domain from, for example, the second digital signal D VCOADC Delete it.

[0105] The CT pipeline ADC 300 further includes a correlator 302 for correlating the jitter and the second digital signal D VCOADC Cross-correlation is performed to extract (1) the signal transfer function of the residue amplifier 208 that produces the amplified residue signal, and (2) the signal transfer function of the CT VCO ADC back end 104. Specifically, the result of the cross-correlation of the correlator 302 can produce an estimate or approximation of the signal transfer function of the residue amplifier 208 and the CT VCO ADC back end 104, i.e., the DSTF RA DSTF VCOADC . The estimate / approximation corresponds to the DSTF VCOADC DSTF RA , which can be used to program the first filter 212 and / or the second filter 214. The estimate / approximation includes information for programming the coefficients of the taps of the FIR filter in the digital signal reconstruction filter 108.

[0106] Notice, Figure 3The digital signal reconstruction filter 108 in can be implemented by only a single FIR filter (for example, when one of the first filter 212 and the second filter 214 has a response of 1). This means that the digital signal reconstruction filter 108 can be implemented efficiently. For example, one of the first filter 212 and the second filter 214 can be a 7-tap FIR filter.

[0107] By considering the signal transfer function (eg, sinusoidal response) of the CT VCO ADC backend 104 in the digital signal reconstruction filter 108, it is possible to obtain the final digital output D OUT Eliminate a lot of distortion in the

[0108] Other types of signals may be used as known signals or jitters, and other mechanisms may be implemented (depending on the type of signal used) to extract the signal transfer function. For example, a pseudo-random signal, such as a pseudo-random 1-bit sequence, may be used as a known signal or jitter. The known signal or jitter may be white noise over a certain frequency range, such as one or more Nyquist zones of a converter. The known signal may include a tone that is swept over a series of frequencies, such as one or more Nyquist zones of a converter. Preferably, the known signal or jitter has energy or information content over a certain frequency range (e.g., a broadband signal). Using a known signal with broadband energy or information content can ensure that the signal transfer function over the frequency range of interest can be extracted. In some cases, the behavior of the signal path may be more critical at lower frequencies, and therefore, the known signal or jitter may have more energy or information content at lower frequencies in the frequency range of interest, so that the extracted signal transfer function has more information about the behavior of the low-frequency signal path.

[0109] Cross-correlation represents one exemplary signal transfer function extraction scheme. Other extraction schemes appropriate for the particular type of known signal being injected can be used to extract the signal transfer function of interest. For example, if the known signal includes tones swept over a range of frequencies, the signal transfer function of interest can be formed using amplitude and phase information corresponding to the various frequencies extracted from the digital outputs produced by the tones at the various frequencies.

[0110] Delay circuit matches signal path with quantizer and DAC

[0111] The residual signal at the input of the residue amplifier 208 represents the analog input signal v in and the reconstructed analog input signal from DAC 204. To ensure that the residual signal generated at node 280 accurately represents the analog input signal v in The difference between the analog input signal v and the reconstructed analog output signal at the output of DAC 204, in At least the delay with the analog input signal vin The time it takes to propagate and be processed by the quantizer 202 and the DAC 204 is the same. Therefore, Figure 2 and 3 The delay circuit 206 delays the analog input signal v in (the input of quantizer 202), and produces a delayed analog input signal. This delay will match the propagation delay of the signal path with quantizer 202 and DAC 204.

[0112] In addition to matching the delay, the delay circuit 206 preferably also matches the response (eg, frequency response) of the signal path having the inputs of the quantizer 202 and the DAC 204 from the analog input signal v in Forming a signal path. For example, the delay circuit 206 can match the amplitude and / or phase of the signal path. In order to achieve matching of amplitude, phase and / or any other desired response characteristics, various analog / CT circuits can be used to implement the delay circuit 206. Figure 4 An exemplary implementation of a VCO-based CT pipeline ADC 400 according to some embodiments of the present disclosure is shown, having a CT residual generation front end 102 and a CT VCO ADC back end 104. The delay circuit 206 in the CT residual generation front end 102 includes a resistor-capacitor lattice circuit.

[0113] Figure 5-10 Various exemplary implementations of delay circuit 206 are shown. Figure 5 A delay circuit implemented based on resistors and transmission lines (eg, conductors) is shown. Figure 6 A delay circuit comprising a resistor-capacitor grid is shown, such as Figure 4 shown. Figure 7 and 8 Variations of the resistor-capacitor lattice circuit are shown. Fig. 9 A delay circuit comprising an inductor-capacitor lattice is shown. Fig.10 A delay circuit comprising a cascaded inductor-capacitor lattice is shown. Different circuit implementations of the delay circuit may achieve different (filtering) responses (i.e., the amplitude and phase may vary depending on the circuit and the values ​​of the circuit components). The specific implementation of the delay circuit 206 may depend on the implementation of the signal path with the quantizer 202 and the DAC 204, and the desired matching level between the delay circuit 206 and the signal path. In some cases, the amplitude matching between the delay circuit 206 and the signal path with the quantizer 202 and the DAC 204 is provided by implementing the delay circuit 206 with a low-pass filtering response.

[0114] Fig. 20Various implementations of the CT delay line according to some embodiments of the present disclosure are shown. The construction and design of the delay circuit 206 can be modular, and portions of the delay circuit 206 can be selected to optimize the matching of the delay circuit 206 with the signal path having the quantizer 202 and the DAC 204. Specifically, portions of the delay circuit 206 can be selected for factors such as filter response, optimal phase matching, and optimal amplitude matching. The delay circuit 206 can include X subcircuits or X subcircuits 2002 connected in series. 1 , 2002 2 ,...2002 X cascade. By selecting or choosing a suitable analog filter for the subcircuit, the delay circuit 206 can achieve a specific filtering response. Each subcircuit can be implemented in different ways, as shown in the figure. In a first example, the analog filter of a given subcircuit can include a resistor in each differential signal path, as shown in analog filter 2004. In a second example, the analog filter of a given subcircuit can include an inductor in each differential signal path, as shown in analog filter 2006. In a third example, the analog filter for a given subcircuit can include a resistor-capacitor grid, as seen in analog filter 2008. In a fourth example, as shown in analog filter 2010 of a given subcircuit, it can include an inductor-capacitor grid. In a fifth example, as seen in analog filter 2012, the analog filter can include a grounded capacitor on each differential signal path. In a sixth example, as seen in analog filter 2014, the analog filter can include a capacitor coupled across the differential signal path.

[0115] Fig.21 An exemplary implementation of a CT delay line 2100 according to some embodiments of the present disclosure is shown. Fig.21 The implementation shown includes cascaded or serially connected subcircuits 2102, 2104, 2106, 2108, 2110, and 2012. Specifically, subcircuits 2102, 2106, and 2110 may be configured to be connected in series. Fig. 20 The analog filter 2004 shown is implemented. Subcircuit 2102 can be implemented using Fig. 20 The analog filter 2008 shown is implemented. Subcircuit 2108 can be implemented using Fig. 20 The analog filter 2014 shown in FIG. Fig.21 The choice of analog filters shown can provide better phase matching and amplitude matching.

[0116] Matching the delay circuit 206 to the signal path with the quantizer 202 and the DAC 204 may mean that the VCO-based CT pipeline ADC may be used in wideband applications, particularly when the delay circuit 206 may achieve a desired response (eg, group delay) over a wide frequency range.

[0117] Benefits of generating CT residual front end

[0118] The CT residual generation front end 102, specifically the delay circuit 206 and the quantizer 202, has continuous time circuits and no sampler. Without a sampler, the CT residual generation front end 102 does not suffer from the aliasing problems typically associated with an ADC front end with a sampler. The signal chain with the VCO-based CT pipeline ADC 100 can have a much simpler anti-aliasing filter, or the anti-aliasing filter can be eliminated entirely. As a result, the components of the signal chain can be more easily integrated together in the signal chain and promote a higher level of integration in the signal chain.

[0119] In addition, the CT residual generation front end 102, specifically, the delay circuit 206 and the quantizer 202, has a resistive input structure. The resistive input structure can provide a resistive input impedance. Advantageously, the resistive input structure can reduce the peak drive current and can also reduce the power consumption of the circuit driving the VCO-based CT pipeline ADC.

[0120] Residual Amplifier Design

[0121] Reference Figure 4 , the residual amplifier 208 in the example has a second order frequency response, which is provided by the two cascaded amplifiers and the feedback signal path. More generally, the residual amplifier 208 can be implemented to have a desired frequency response to provide features such as anti-aliasing. In some embodiments, the residual amplifier 208 can have a low pass filter response. In some embodiments, the residual amplifier 208 can have a band pass filter response. In some embodiments, the residual amplifier 208 can have a first order frequency response. In some embodiments, the residual amplifier 208 can have a second order or higher order frequency response. In some embodiments, the residual amplifier 208 can be implemented to have a desired frequency response to provide features such as anti-aliasing ... be implemented to have a first order frequency response. In some embodiments, the residual amplifier 208 can be implemented to have a second order or higher order frequency response. In some embodiments, the residual amplifier 208 can be implemented to have a second order or higher order frequency response at the sampling frequency f s There is a notch nearby, which can provide additional anti-aliasing.

[0122] DAC Pulse Shaping

[0123] One challenge in the CT residual generation front end 102 is that the DAC 204 may have a strong image in the output spectrum. A strong image may cause the residual signal to have a high amplitude. To address this problem, a specific transfer function may be selected and implemented in the signal path involving the delay circuit 206, and (2) the first digital signal D 1 Upsampling is performed and the upsampled signal is processed through a discrete-time transfer function to minimize the residual signal.

[0124] Fig.11 2 shows an exemplary implementation of a CT residual generation front end 102 with D / A converter pulse shaping according to some embodiments of the present disclosure. The CT residual generation front end 102 has a signal path with a delay circuit 206. The continuous time transfer function of the signal path may be C(s). The quantizer 202 is f ck The first digital signal D is generated at a rate 1 The first digital signal D 1 is upsampled L times by upsampling block 1102. L is the upsampling factor of upsampling block 1102. Therefore, the output of upsampling block 1102 has a rate of L·f ck The upsampling block 1102 may interpolate the first digital signal D by inserting (L-1) zeros between every two samples. 1 The output of upsampling block 1102 is filtered by digital filter 1104 having a discrete time transfer function F(z). The output of digital filter 1104 is L·f ck The DAC 204 is driven at a rate (the rate of the quantizer 202 multiplied by the upsampling factor of the upsampling block 1102) and converted to analog form. The DAC 204 generates a reconstructed analog signal based on the output of the digital filter 1104. Node 280 can subtract the delayed analog input signal from the delay circuit 206 from the reconstructed analog input signal from the DAC 204 to produce a residual signal. By properly selecting and implementing C(s) and F(z), the residual signal generated at the node 280 can be minimized to minimize the in-band quantization error of most or all of the quantizers 202. For a given C(s), F(z) (i.e., the digital filter 1104) can be programmed accordingly to minimize the residual signal. For example, F(z) can be programmed to have a discrete time transfer function that can reduce or suppress images in the output spectrum of the DAC204. For a given F(z), C(s) can be implemented (e.g., by implementing an appropriate delay circuit 206) to minimize the residual signal.

[0125] Digital Nonlinearity Calibration in CT VCO ADC Backend

[0126] The nonlinearity of the VCO ADC 210 may be corrected by the digital nonlinearity correction block 106. To correct the nonlinearity, the CT VCO ADC back end 104 extracts the nonlinearity, determines coefficients that may correct the nonlinearity, and programs the digital nonlinearity correction block 106 to correct the nonlinearity of the VCO ADC 210. The calibration process may occur in the background, and the coefficients may be updated periodically or aperiodically to provide an adaptive calibration.

[0127] Fig.12 A digital nonlinear calibration block 106 and a scheme for programming the digital nonlinear calibration block 106 according to some embodiments of the present disclosure are shown. The CT VCO ADC back end 104 includes a replica VCO ADC 1202 to process a known signal. The replica VCO ADC 1202 includes the same signal path (and circuit) as the VCO ADC 210. However, the replica VCO ADC 1202 does not have a digital nonlinear calibration block. The replica VCO ADC 1202 receives a known signal generated by a signal generator 1204 and converts the known signal (e.g., a known analog signal) into a digital output. In addition, the CT VCO ADC back end 104 includes a calibration unit 1206 to derive coefficients of the digital nonlinear correction block 106 based on the digital output of the replica VCO ADC 1202 and the known signal.

[0128] The replica VCO ADC 1202 may receive a zero differential input voltage (e.g., a constant mid-range input signal), and the signal generator 1204 may be a DAC (receiving a known signal sequence) to inject the known signal into the replica VCO ADC 1202. The known signal may include a calibration sequence that may be used to extract nonlinearities of the VCO ADC 210.

[0129] In some embodiments, the calibration sequence may include the sum of independent, zero-mean, pseudo-random sequences. The digital output of the VCO ADC 210 may be correlated with the pseudo-random sequence to extract the nonlinearity of the system. In some embodiments, the calibration sequence includes the sum of three pseudo-random sequences: k 1 [n]+k 2 [n]+k 3 [n], and the digital output of VCO ADC 210 is related to k 1 [n], k 1 [n]·k 2 [n], and k 1 [n]·k 2 [n]·k 3[n]Correlated (alone). The correlated results generate coefficients that can be used to correct second-order, third-order, and other higher-order non-linearities. The calibration unit 1206 can use the coefficients to calculate the corrected digital output values into the look-up table of the digital non-linearity calibration block 106, where the look-up table maps the possible values of the digital output of the VCO ADC 210 to the respective corrected digital output values.

[0130] In some embodiments, the calibration unit 1206 can determine the measured VCO center frequency so that the VCO center frequency of the VCO ADC 210 can be adjusted accordingly.

[0131] Pseudo-differential signal paths in the VCO ADC

[0132] Calibration using the replica VCO ADC 1202 can be limited because the calibration depends on the degree of matching between the replica VCO ADC 1202 and the VCO ADC 210. If the calibration using the replica VCO ADC 1202 is not sufficient to address even-order non-linearities (e.g., second-order non-linearity), the VCO ADC 210 can be implemented in a pseudo-differential manner to suppress even-order non-linearities (at the cost of greater area and power consumption).

[0133] Fig.13 An exemplary implementation of the CT VCO ADC backend 104 with two pseudo-differential signal paths and a replica signal path is shown in accordance with some embodiments of the present disclosure. Specifically, the VCO ADC 210 has two pseudo-differential signal paths, and the replica VCO ADC 1202 has a replica signal path.

[0134] The two pseudo-differential signal paths share a (same) first voltage-current converter 1302, where the first voltage-current converter 1302 receives the amplified residual signal v from the CT residue generation front-end 102 a_res . The amplified residual signal v a_res1304 to process the positive signal from the first voltage-to-current converter 1302. The first ring oscillator 1304 of the first pseudo differential signal path is followed by a ring sampler and phase decoder, shown as DFF 1306. The DFF 1306 is followed by a differentiator 1308. The differentiator 1308 is followed by a digital non-linear calibration block 1310. The second pseudo differential signal path has a second ring oscillator 1312 to process the negative signal from the first voltage-to-current converter 1302. The second ring oscillator 1312 of the second pseudo differential signal path is followed by a ring sampler and phase decoder, shown as DFF 1314. The DFF 1314 is followed by a differentiator 1316. The differentiator 1316 is followed by a digital non-linear calibration block 1318. The outputs of the first pseudo differential signal path and the second pseudo differential signal path (e.g., the outputs of the digital nonlinearity calibration block 1310 and the digital nonlinearity calibration block 1318) are combined at a first node 1320. Specifically, the output of the first pseudo differential signal path is subtracted from the output of the second pseudo differential signal path to form the final output of the VCO ADC 210. Subtraction or differentiation can suppress even-order nonlinearity because the components common to the two pseudo differential signal paths will be cancelled.

[0135] The replica VCO ADC 1202 with replica signal path has the same / identical circuitry as the pseudo differential signal path (the replica signal path does not have the digital nonlinear calibration module). The replica VCO ADC 1202 has a voltage-to-current converter 1322 that receives a differential zero input. The signal generator 1204 can inject a (current) signal into the output of the voltage-to-current converter 1322. The replica signal path includes a ring oscillator 1324, a DFF 1326, and a differentiator 1328. The output of the differentiator 1328 is provided to the calibration unit 1206 to perform calibration on the output of the voltage-to-current converter 1322. Fig.12 The calibration operation is described.

[0136] Quantization noise can significantly degrade the performance of the CT VCO ADC backend 104. The performance degradation is particularly severe for signals with low amplitudes (spurious tones associated with the input signal). Dithering the input signal evenly distributed over a frequency range unrelated to the input signal with a white sequence can spread the tones into the noise floor and improve the distortion associated with the input signal. However, injecting dither into the VCO ADC degrades the SNR of the signal band because the dither is not affected by the noise transfer function of the VCO ADC. To address the degradation of the signal band SNR, a self-cancelling dithering scheme is used. Dither is added to the input of one pair of pseudo-differential signal paths, and the same dither is subtracted from the input of the other pair of pseudo-differential signal paths. The outputs of the pseudo-differential signal path pairs are added. The undesirable components introduced by the dither have the same amplitude and opposite polarity. When the outputs of the paired pseudo-differential signal paths are added, the undesirable components introduced by the dither are eliminated, the signal components increase in amplitude, and the noise components increase in power. Therefore, the SNR is significantly improved by the self-dithering scheme.

[0137] Fig.14 An exemplary implementation of a CT VCO ADC back end 104 with two pairs of pseudo differential signal paths according to some embodiments of the present disclosure is shown. The first pair of pseudo differential signal paths follows the first voltage-to-current converter 1302. The first pseudo differential signal path and the second pseudo differential signal path process the positive signal from the voltage-to-current converter 1302 and the negative signal from the voltage-to-current converter 1302, respectively. The outputs of the first pseudo differential signal path and the second pseudo differential signal path are phase-differencing at a node 1320. The second pair of pseudo differential signal paths follows the second voltage-to-current converter 1402. The second voltage-to-current converter 1402 receives the amplified residual signal v from the CT residual generation front end 102. a_res. The third pseudo differential signal path has a third ring oscillator 1404 to process the positive signal from the second voltage-to-current converter 1402. The third ring oscillator 1404 of the third pseudo differential signal path is followed by a ring sampler and phase decoder, shown as DFF 1406. The DFF 1406 is followed by a differentiator 1408. The differentiator 1408 is followed by a digital non-linear calibration block 1410. The fourth pseudo differential signal path has a fourth ring oscillator 1412 to process the negative signal from the second voltage-to-current converter 1402. The fourth ring oscillator 1412 of the fourth pseudo differential signal path is followed by a ring sampler and phase decoder, shown as DFF 1414. The DFF 1414 is followed by a differentiator 1416. The differentiator 1416 is followed by a digital non-linear calibration block 1418. The outputs of the third pseudo differential signal path and the fourth pseudo differential signal path (e.g., the outputs of the digital nonlinear calibration block 1410 and the digital nonlinear calibration block 1418) are combined at the second node 1420. Specifically, the output of the third pseudo differential signal path is subtracted from the output of the fourth pseudo differential signal path. Subtraction or differentiation can suppress even-order nonlinearity because the components common to the two pseudo differential signal paths will be cancelled.

[0138] The output of the first node 1320 and the output of the second node 1420 are combined by the third node 1422. Specifically, the outputs of the first pair of pseudo differential signal paths and the second pair of pseudo differential signal paths are added at the third node 1422. In order to inject self-canceling jitter, the VCO ADC 210 also includes a first circuit 1440 to inject jitter having a first polarity into the first pseudo differential signal path and the second pseudo differential signal path, and a second circuit 1450 to inject jitter having a second polarity opposite to the first polarity into the third pseudo differential signal path and the fourth pseudo differential signal path. The first circuit system 1440 can be a signal generator (e.g., a DAC that receives a jitter sequence and outputs jitter having a first polarity) to add jitter to the input of the first pair of pseudo differential signal paths. The second circuit 1450 can be a signal generator (e.g., a DAC that receives the same jitter sequence but outputs jitter having a second polarity) to remove the same jitter at the input of the second pair of pseudo differential signal paths.

[0139] Phase interpolation in VCO ADCs increases bandwidth

[0140] The SQNR over the signal bandwidth of the VCO ADC increases with increasing quantization levels and oversampling ratio. The number of quantization levels of the VCO ADC is determined by the minimum delay through each delay element. To reduce the minimum delay and improve the SQNR, the ring oscillator can be modified to include two interpolated ring oscillators, for example, two ring oscillators that are injection locked together or two phase-shifted ring oscillators. Fig.15An exemplary phase interpolation ring oscillator according to some embodiments of the present disclosure is shown. The ring oscillator in the VCO ADC signal path may include a first injection locked ring oscillator 1502 and a second injection locked ring oscillator 1504. In the example shown, the first injection locked ring oscillator 1502 has 7 delay elements and the second injection locked ring oscillator 1504 has 7 delay elements. The first injection locked ring oscillator 1502 and the second injection locked ring oscillator 1504 are orthogonally coupled together through a resistor network 1506 to lock the first injection locked ring oscillator 1502 and the second injection locked ring oscillator 1504 90° out of phase with each other. The result is a phase interpolation ring oscillator with 14 delay elements, with a minimum delay of half. Therefore, the SQNR and bandwidth are significantly improved. The CT VCO ADC back end 104 with a high bandwidth, phase interpolation can benefit the overall wideband response of the VCO-based pipeline ADC. Locking the VCO ADC to a different sampling rate that is higher than the sampling rate of the CT residual generation front end

[0141] The architecture of the VCO-based CT pipeline ADC allows different sampling rates for the CT residual generation front end 102 and the VCO ADC back end 104. The oversampling rate and sampling rate of the VCO ADC will affect the SQNR of the VCO ADC. To further improve the SQNR, the CT VCO ADC back end 104 can be clocked at twice or more (e.g., 2x, 4x, 6x, 8x, etc.) clock frequency, or tuned / locked to twice or more (e.g., 2x, 4x, 6x, 8x, etc.) clock frequency relative to the clock frequency driving the CT residual generation front end 102. Fig.16 1 shows an exemplary implementation of a VCO-based CT pipeline ADC 1600 having a CT residual generation front end 102 and an oversampling VCO ADC back end 104 according to some embodiments of the present disclosure. The CT residual generation front end 102 is composed of a first clock frequency f ck For example, the quantizer 202 is driven by a first clock signal of f ck to drive. If DAC pulse shaping is implemented (such as Fig.11 As shown), DAC 204 can be composed of f ck or ck The CT VCOADC backend 104 is driven by a second clock signal having a second clock frequency K·f ckis K times the first clock frequency, where K is at least 2 or an integer multiple of 2. When the CT VCO ADC back end 104 is driven by a higher second clock frequency, the CT VCO ADC back end 104 includes a decimation filter 1602 to reduce the sampling rate to match the sampling rate of the CT residual generation front end 102; and an anti-aliasing filter (e.g., a low pass filter) to remove unwanted images in the output spectrum. Tuning / locking to a clock frequency of twice or higher (e.g., 2x, 4x, 6x, 8x, etc.) can improve the linearity of the CT VCO ADC back end 104. In addition, integer multiples of the clock frequency can maximize the phase detection range of the CT VCO ADC back end 104.

[0142] Higher order CT VCO ADC backend

[0143] In some embodiments, the CT VCO ADC back end 104 may be modified to implement a higher order structure to extend the noise shaping advantages of the CT VCO ADC back end 104 . Fig.17 An exemplary implementation of a higher order CT VCO ADC back end 104 according to some embodiments of the present disclosure is shown. Specifically, the CT VCO ADC implements third order noise shaping. The CT VCO ADC back end 104 includes multiple oscillators (three oscillators in this example) and one or more feedback paths to implement multi-order noise shaping. In the example shown, the CT VCO ADC back end 104 includes a first VCO 1702, an up-down counter 1704, a digitally controlled oscillator (DCO) 1706, an up-down counter 1708, a DCO 1710, and a sampling register 1714. The second digital output D generated by the sampling register 1714 is VCOADC is provided to the up / down counter 1704, the up / down counter 1708 and the up / down counter 1712 as feedback. In addition, the second digital output D generated by the sampling register 1714 is VCOADC is provided to node 1716 as feedback with a gain of g. As shown in the figure, the second digital output D VCOADC Overall feedback to selected locations enables high order noise shaping.

[0144] Modularity and reconfigurability of VCO-based CT pipeline ADC

[0145] The VCO-based CT pipeline ADC can be implemented without feedback. This is in contrast to the delta-sigma ADC or successive approximation register ADC that has a feedback path. In other words, the CT residual generation front end 102 and the CT VCO ADC back end 104 only have a feedforward path. There is no overall feedback from the output of the CT VCO ADC back end 104 back to the input of the CT residual generation front end 102. This architecture has multiple benefits. No feedback means that signal processing including signal latency is more practical and easier. Signal processing includes digital signal processing of the digital signals of the CT residual generation front end 102 and the CT VCO ADC back end 104. Signal processing commonly used with VCO ADCs can include digital nonlinear correction and over-range correction. In addition, the feedback path can greatly change the stability and transfer function of the ADC. In some cases, the feedback path limits the bandwidth of the ADC. Likewise, the absence of a feedback path can guarantee the stability of the VCO-based CT pipeline ADC.

[0146] The absence of feedback also means that the VCO-based CT pipeline ADC is modular. An ADC architecture with a feedback path cannot be easily modified without a major redesign of the ADC. Modularity also allows the VCO-based CT pipeline ADC to be reconfigured. Fig.18 1 shows an exemplary implementation of a VCO-based CT pipeline ADC 1800 with a reconfigurable CT residual generation front end 102 and a CT VCO ADC back end 104 according to some embodiments of the present disclosure. The CT residual generation front end 102 is cascaded followed by the CT VCO ADC back end 104. The CT residual generation front end 102 generates an amplified residual signal v a_res The CT residual generation front end 102 may include N cascaded CT residual generation stages 1801 1 , …, 1802 N CT residual generation front end 102 for analog input signal v in Quantize and generate a digital signal D 1 , ...D N and the amplified residual signal v a_res Each CT residual generation stage may include a quantizer, a DAC, a delay circuit, a node, and a residual amplifier. Each quantizer in the CT residual generation stage generates a respective digital signal D 1 , ...D N Each residue amplifier in the CT residue generation stage generates a respective amplified residue signal. The CT VCO ADC back end 104 quantizes the amplified residue signal v a_res And generate a digital signal D VCOADC The digital signal reconstruction filter 108 processes the digital signal D from the residual generation stage.1 , ...D N and the second digital signal D VCOADC Filter and generate the final digital signal D OUT . You can refer to the previous Figure 3 The digital signal reconstruction filter 108 is programmed in the manner described (with some differences).

[0147] Since the CT residue in the cascade generates stages 18011, ... 1802 N There are no feedback paths within or between the CT residual generation stages, and there is no overall feedback from the CT VCO ADC back end 104 to the CT residual generation front end 102, so the number of cascaded CT residual generation stages and the parameters of each cascaded CT residual generation stage can be easily modified. For example, circuit designers can change the number of cascaded CT residual generation stages and the parameters of each cascaded CT residual generation stage based on target performance indicators such as power consumption, noise, distortion, silicon area, and digital signal processing complexity. In other words, various stages can be easily added or deleted to achieve certain target performance indicators. Through impedance scaling, increasing the number of cascaded CT residual generation stages can provide better anti-aliasing, better SNR, and better NSD.

[0148] In addition, modularity allows on-chip reconfiguration. This means that the integrated circuit can include N residue generation stages in the CT residue generation front end 102, and switches or switch networks (transistors) can be provided to the inputs and / or outputs of the N residue generation stages to configure or reconfigure the signal chain in the CT residue generation front end 102 and cascade change the residue generation stages 18011, ..., 1802. N The number of cascaded quantized analog input signals v in and generates an amplified residual signal v a_res Configurable / controllable / programmable routing inside and / or outside a silicon die or integrated circuit package where a VCO-based CT pipeline ADC 1800 can be used to configure or reconfigure a residue generation stage 1801 1 ,…1802 N The number of residual production levels 18011, ... 1802 N Used to quantize the analog input signal v in and generates an amplified residual signal v a_res Controller 1804 may control circuitry that may control the number of residue generation stages used and, therefore, reconfigure the architecture of VCO-based CT pipeline ADC 1800. In some embodiments, controller 1804 may reconfigure the connections of the residue generation stages to change the number of residues used to generate the amplified residue signal v a_resThe cascaded CT residual generation stages 18011, ... 1802 N .

[0149] Pipeline analog-to-digital conversion method

[0150] Fig.19 is a flow chart illustrating a method for pipeline analog-to-digital conversion according to some embodiments of the present disclosure. At 1902, a CT front end (eg, CT residual generation front end 102) generates a signal representing an analog input signal (eg, v in ) of the first digital signal (e.g., D 1 ), and a residual signal representing the difference between a delayed version of the analog input signal and a reconstructed analog signal generated from the first digital signal. At 1904, the residual amplifier amplifies the residual signal to generate an amplified residual signal (e.g., v a_res At 1906, the VCOADC backend (eg, the CT VCOADC backend 104) samples the phase of the amplified residual signal and generates a second digital signal (eg, D VCOADC ). At 1908, a digital signal reconstruction filter (eg, digital signal reconstruction filter 108) filters the first digital signal and the second digital signal. At 1910, the digital signal reconstruction filter combines the filtered versions of the first digital signal and the second digital signal to generate a final digital output.

[0151] In some embodiments, the method further includes delaying the analog input signal by a delay circuit (e.g., delay circuit 206). The response of the delay circuit matches the response of the signal path having the quantizer and the digital-to-analog converter. Examples of such embodiments are Figure 2 , 4 -10 and 20-21.

[0152] In some embodiments, the method further includes injecting jitter at the input of the residue amplifier (e.g. Figure 3 The method may further include extracting a signal transfer function of the residual amplifier and a signal transfer function of a VCO ADC back end based on the jitter and the second digital signal. The method may further include programming a first filter for filtering the first digital signal and / or a second filter for filtering the second digital signal based on the signal transfer function of the residual amplifier that amplifies the residual signal and the signal transfer function of the VCO ADC back end. Figure 3 An example of such an embodiment is shown in .

[0153] In some embodiments, the method further includes: driving the CT front end with a first clock signal having a first clock frequency; and driving the VCO ADC back end with a second clock signal having a second clock frequency that is at least twice the first clock frequency. The method may further include: decimating the digital output of the VCO ADC back end; and filtering the decimated version of the digital output of the VCO ADC back end through an anti-aliasing filter to generate a second digital signal. Examples of such embodiments are described in Fig.16 Shown in.

[0154] In some embodiments, the method may further include adjusting the number of residue generation stages used in the continuous-time front end to generate the amplified residue signal. Examples of such embodiments are described in Fig.18 Shown in.

[0155] example

[0156] Example 1 is a pipeline analog-to-digital converter (ADC), comprising: a continuous-time residual generation front end, used to quantize an analog input signal and generate a first digital signal and an amplified residual signal; a voltage-controlled oscillator (VCO) ADC back end, used to quantize the amplified residual signal and generate a second digital signal; and a digital signal reconstruction filter, used to filter the first digital signal and the second digital signal and generate a final digital signal.

[0157] In Example 2, the pipeline ADC of Example 1 may optionally include a continuous-time residual generation front end, including: a quantizer for generating the first digital signal; a digital-to-analog converter for receiving the first digital signal and generating a first reconstructed analog signal; and a delay circuit for delaying the first analog input signal to the quantizer and generating a first delayed analog input signal, wherein a response of the delay circuit matches a response of a signal path having the quantizer and the digital-to-analog converter.

[0158] In Example 3, the pipeline ADC of Example 2 may optionally include: the delay circuit matches the amplitude and phase of the signal path.

[0159] In Example 4, the pipeline ADC of any of Examples 1-3 can optionally include: the delay circuit includes a resistor-capacitor grid.

[0160] In Example 5, the pipeline ADC of any of Examples 1-4 can optionally include: the delay circuit includes one or more inductor-capacitor grids.

[0161] In Example 6, the pipeline ADC of any one of Examples 2-5 may optionally include: the continuous-time residual generation front end further includes: a node for outputting a first residual signal representing a difference between the first delayed analog input signal and the first reconstructed analog signal.

[0162] In Example 7, the pipeline ADC of any one of Examples 1-6 may optionally include: the continuous-time residual generation front end includes: a residue amplifier for amplifying the residue signal and generating an amplified residue signal.

[0163] In Example 8, the pipeline ADC of Example 7 can optionally include: the residue amplifier includes a frequency response having a second order or higher order.

[0164] In Example 9, the pipeline ADC of any one of Examples 1-8 may optionally include: the digital signal reconstruction filter includes: a first filter for filtering the first digital signal; a second filter for filtering the second digital signal; and a node for combining the outputs of the first filter and the second filter to generate the final digital signal.

[0165] In Example 10, the pipeline ADC of Example 9 may optionally include: a ratio of the first filter and the second filter corresponds to: (1) a signal transfer function of a residue amplifier that generates the amplified residue signal; and (2) a signal transfer function of a VCO ADC back end.

[0166] In Example 11, the pipeline ADC of Example 9 or 10 may optionally include: a ratio of the first filter and the second filter corresponding to: (1) a signal transfer function of a residual amplifier that generates the amplified residual signal; (2) a signal transfer function of a VCOADC back end; and (3) a noise transfer function of a CT residual generating front end.

[0167] In Example 12, the pipeline ADC of any one of Examples 1-11 may optionally include: a continuous-time residual generation front end including: a residue amplifier for amplifying a residue signal and generating an amplified residue signal; and a circuit for injecting dither at an input of the residue amplifier; and the pipeline ADC further includes: a circuit for correlating the dither and the second digital signal to extract: (1) a signal transfer function of the residue amplifier generating the amplified residue signal; and (2) a signal transfer function of a VCO ADC back end.

[0168] In Example 13, the pipeline ADC of any one of Examples 1-12 may optionally include: a continuous-time residual generation front end including: a quantizer for generating the first digital signal; an upsampling block for upsampling the first digital signal; a filter for filtering the output of the upsampling block; and a digital-to-analog converter for receiving the output of the filter and generating a first reconstructed analog signal.

[0169] In Example 14, the pipeline ADC of Example 13 may optionally include: the quantizer operates at a first rate; the digital-to-analog converter operates at a second rate; and the second rate is the first rate multiplied by an upsampling factor of the upsampling block.

[0170] In Example 15, the pipeline ADC of any one of Examples 1-14 may optionally include: the VCO ADC back end includes: a digital nonlinearity correction module for correcting nonlinearity of the VCO ADC back end.

[0171] In Example 16, the pipeline ADC of Example 15 may optionally include: the VCO ADC back end includes: a replica VCO ADC for processing the known signal; and a calibration unit for deriving coefficients of a digital nonlinear correction filter based on a digital output of the replica VCO ADC and the known signal.

[0172] In Example 17, the pipeline ADC of any one of Examples 1-16 may optionally include: the VCO ADC back end includes: (1) a first voltage-to-current converter for receiving the amplified residual signal; (2) a first signal path having a first ring oscillator to process the positive signal from the first voltage-to-current converter; (3) a second signal path having a second ring oscillator to process the negative signal from the first voltage-to-current converter; and (4) a first node for combining the outputs of the first signal path and the second signal path.

[0173] In Example 18, the pipeline ADC of Example 17 may optionally include: the VCO ADC back end also includes: (5) a second voltage-to-current converter for receiving the amplified residual signal; (6) a third signal path having a third ring oscillator to process the positive signal from the second voltage-to-current converter; (7) a fourth signal path having a fourth ring oscillator to process the negative signal from the second voltage-to-current converter; and (8) a second node for combining the outputs of the third signal path and the fourth signal path; and (9) a third node for combining the outputs of the first node and the second node.

[0174] In Example 19, the pipeline ADC of Example 18 may optionally include: the VCO ADC back end also includes: (10) a first circuit for injecting dither having a first polarity into the first signal path and the second signal path, and (11) a second circuit for injecting dither having a second polarity opposite to the first polarity into the third signal path and the fourth signal path.

[0175] In Example 20, the pipeline ADC of any one of Examples 1-19 can optionally include: the VCO ADC back end includes two injection locked ring oscillators.

[0176] In Example 21, the pipeline ADC of any one of Examples 1-20 may optionally include: the continuous-time residual generation front end is driven by a first clock signal having a first clock frequency; and the VCO ADC back end is driven by a second clock signal having a second clock frequency at least twice the first clock frequency.

[0177] In Example 22, the pipeline ADC of any of Examples 1-21 can optionally include: the VCO ADC includes a decimation filter and an anti-aliasing filter.

[0178] In Example 23, the pipeline ADC of any of Examples 1-22 can optionally include: the VCO ADC back end includes multiple oscillators and one or more feedback paths to implement multi-order noise shaping.

[0179] In Example 24, the pipeline ADC of any one of Examples 1-23 may optionally include: the continuous-time residual generation front end includes cascaded continuous-time residual generation stages.

[0180] In Example 25, the pipeline ADC of any of Examples 1-24 can optionally include: a number of residue generation stages for quantizing the analog input signal and generating the amplified residue signal can be configured by the controller.

[0181] In Example 26, the pipeline ADC of any one of Examples 1-25 can optionally include: the VCO ADC back end includes a series of: a ring oscillator, a phase digital converter, and a differentiator.

[0182] Example 27, a method for pipeline analog-to-digital conversion, comprising: generating, through a continuous-time front end, a first digital signal representing an analog input signal, and a residual signal representing the difference between a delayed version of the analog input signal and a reconstructed analog signal generated from the first digital signal; amplifying the residual signal to generate an amplified residual signal; sampling the phase of the amplified residual signal through a voltage-controlled oscillator (VCO) analog-to-digital converter (ADC) back end; generating a second digital signal based on the phase of the amplified residual signal through a VCO ADC back end; filtering the first digital signal and the second digital signal; and combining the filtered versions of the first digital signal and the second digital signal to generate a final digital output.

[0183] In Example 28, the method of Example 27 can optionally include delaying the analog input signal by a delay circuit, wherein a response of the delay circuit matches a response of a signal path having a quantizer and a digital-to-analog converter.

[0184] In Example 29, the method of Example 27 or 28 may optionally include injecting dither at an input of a residue amplifier that amplifies the residue signal.

[0185] In Example 30, the method of Example 29 may optionally include extracting a signal transfer function of the residual amplifier and a signal transfer function of a VCO ADC back end based on the dither and the second digital signal.

[0186] In Example 31, the method of any one of Examples 27-30 may optionally include programming a first filter for filtering the first digital signal and / or a second filter for filtering the second digital signal based on a signal transfer function of a residual amplifier that amplifies the residual signal and a signal transfer function of a VCO ADC back end.

[0187] In Example 32, the method of any one of Examples 27-31 can optionally include: driving the continuous time front end using a first clock signal having a first clock frequency; and driving the VCO ADC back end using a second clock signal having a second clock frequency at least twice the first clock frequency.

[0188] In Example 33, the method of Example 32 may optionally include: decimating a digital output of the VCO ADC back end; and filtering the decimated version of the digital output of the VCO ADC back end through an anti-aliasing filter to generate a second digital signal.

[0189] In Example 34, the method of any one of Examples 27-33 may optionally include adjusting a number of residual generation stages used in a continuous-time front end to generate the amplified residual signal.

[0190] Example 35 is a modular pipeline ADC, comprising: a continuous-time residual generation front end for generating an amplified residual signal, wherein the continuous-time residual generation front end includes a plurality of cascaded residual generation stages; a voltage-controlled oscillator (VCO) ADC back end for quantizing the amplified residual signal and generating a second digital signal; and a digital signal filter for filtering the digital signal from the residual generation stage and the second digital signal, and generating a final digital signal.

[0191] In Example 36, the modular pipeline ADC of Example 35 may optionally include: the continuous-time residual generation front end is used to quantize the analog input signal and generate a plurality of digital signals and an amplified residual signal.

[0192] In Example 37, the modular pipeline ADC of Example 35 or 36 may optionally include: a controller for reconfiguring connections for the residue generation stages to change the number of residue generation stages used to generate the amplified residue signal.

[0193] Example A is a device comprising means for implementing and / or performing the methods of any of Examples 27-34 and / or any of the functions described herein.

[0194] Other implementation notes, variations, and applications

[0195] The current architecture of the VCO-based CT pipeline ADC is particularly well suited for high-speed, high-precision applications. Applications that can greatly benefit from this architecture include: instrumentation, test, spectrum analyzers, military use, radar, wired or wireless communications, mobile phones (especially as standards continue to push for higher speed communications), and base stations.

[0196] In some embodiments, the VCO-based CT pipeline ADC can be implemented by an on-chip microprocessor (i.e., the ADC is on-chip, executing instructions / firmware provided to the on-chip microprocessor) and / or dedicated on-chip digital hardware to perform digital signal processing functions. In various other embodiments, the digital filter or digital function can be implemented in one or more silicon cores in an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), and other semiconductor architectures.

[0197] All specifications, dimensions, and relationships (e.g., number of processors, logical operations, etc.) outlined herein are provided for purposes of example and instruction only. This information may be changed considerably without departing from the spirit of the present disclosure or the scope of the appended claims. These specifications apply only to one non-limiting example, and therefore, they should be interpreted as such. In the foregoing description, example embodiments have been described with reference to specific processors and / or component arrangements. Various modifications and changes may be made to these embodiments without departing from the scope of the present disclosure, the appended claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

[0198] Note that, with the numerous examples provided herein, interactions can be described based on two, three, four or more electronic components. However, this is done only for the purpose of clarity and example. It should be understood that the system can be combined in any suitable manner. Along similar design alternatives, any components, modules and elements shown in the drawings can be combined in various possible configurations, all of which are obviously within the broad scope of this specification. In some cases, it may be easier to describe one or more functions of a given set of processes with reference to only a limited number of electrical components. It should be understood that the circuits of the drawings and their teachings are easy to expand and can accommodate a large number of components, as well as more complex / complex arrangements and configurations. Therefore, the examples provided should not limit the scope or inhibit the broad teachings of electronic circuits that may potentially be applied to countless other architectures.

[0199] Note that in this specification, references to various features (e.g., elements, structures, modules, components, steps, operations, features, etc.) included in “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc.) are intended to indicate that any such features are included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment.

[0200] Functions related to pipelined analog-to-digital conversion, such as Fig.19 The processes shown only illustrate some possible functions that may be performed internally or internally by the circuits shown in the drawings or circuits coupled to the systems shown in the drawings (e.g., digital circuits or on-chip microprocessors). Some of these operations may be deleted or removed where appropriate, or may be substantially modified or changed without departing from the scope of the present disclosure. In addition, the timing of these operations may be greatly changed. For purposes of example and discussion, the above-mentioned operational flows are provided. The embodiments described herein provide great flexibility because any suitable arrangement, timing, configuration, and timing mechanism may be provided without departing from the teachings of the present disclosure.

[0201] Numerous other changes, substitutions, variations, alterations, and modifications may be determined by those skilled in the art, and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications that fall within the scope of the claims appended to the present disclosure. Note that all optional features of the above-described apparatus may also be implemented with respect to the methods or processes described herein, and that the details in the examples may be used anywhere in one or more embodiments.

Claims

1. A pipeline analog-to-digital converter ADC, include: The first level includes: A continuous time delay circuit for receiving an analog input; a quantizer for receiving the analog input; a digital-to-analog converter, for receiving an output of the quantizer; a node for receiving an output of the continuous time delay circuit and an output of the digital-to-analog converter; and a residue amplifier coupled to the node; and A second stage, for receiving an output of the residue amplifier, the second stage comprising: Ring oscillator; A ring sampler, for receiving the output of the ring oscillator; a phase decoder for receiving an output of the ring sampler; and A differentiator is used to receive the output of the phase decoder.

2. The pipeline ADC according to claim 1, further comprising: include: The first digital filter is used to receive the digital output of the first stage.

3. The pipeline ADC according to claim 1, further comprising: include: The second digital filter is used to receive the digital output of the second stage.

4. The pipeline ADC of claim 1, wherein the continuous time delay circuit comprises at least one of: a resistor-capacitor grid, and one or more inductor-capacitor grids.

5. The pipeline ADC according to claim 1, further comprising: include: Additional levels include: an additional continuous time delay circuit for receiving an additional analog input; a further quantizer for receiving said further analog input; a further digital-to-analog converter for receiving an output of the further quantizer; a further node for receiving an output of the further continuous time delay circuit and an output of the further digital to analog converter; and A further residue amplifier is coupled to the node to output the analog input.

6. The pipeline ADC according to claim 1, further comprising: include: Signal generator; a replica ring oscillator for receiving the output of the signal generator; a replica ring sampler, for receiving an output of the replica ring oscillator; a replica phase decoder for receiving an output of the replica ring sampler; and A replica differentiator is configured to receive an output of the replica phase decoder.

7. The pipeline ADC according to claim 6, further comprising: include: A calibration unit is configured to receive the output of the replica differentiator.

8. The pipeline ADC according to claim 7, further comprising: include: Lookup table for receiving values ​​from the calibration unit.

9. The pipeline ADC according to claim 1, further comprising: include: A voltage-to-current converter between the residue amplifier and the ring oscillator.

10. The pipeline ADC according to claim 9, further comprising: include: another ring oscillator for receiving the negative output of the voltage-to-current converter; a further ring sampler for receiving the output of the further ring oscillator; a further phase decoder for receiving an output of said further ring sampler; a further differentiator for receiving an output of the further phase decoder; and A differential node is used to receive the output of the differentiator and the output of the further differentiator.

11. The pipeline ADC of claim 1 , wherein the ring oscillator receives dither having a first polarity.

12. The pipeline ADC according to claim 11, further comprising: include: Another ring oscillator is used to receive the dither having a second polarity opposite to the first polarity.

13. The pipeline ADC of claim 1, wherein the ring oscillator comprises a first injection locked ring oscillator, a second injection locked ring oscillator, and a resistor network coupling the first injection locked ring oscillator and the second injection locked ring oscillator together.

14. The pipeline ADC of claim 1 , wherein the second stage is driven at a clock frequency higher than the clock frequency of the first stage, and the second stage further include: Decimation filter; and Anti-aliasing filter.

15. A method for pipeline analog-to-digital conversion, include: quantizing an analog input signal by a continuous-time quantizer to produce a first digital output; generating a reconstructed analog input signal based on the first digital output; delaying the analog input signal through a continuous time delay circuit to generate a delayed analog input signal; generating a residual signal based on the reconstructed analog input signal and the delayed analog input signal; filtering the residual signal to generate a filtered residual signal; sampling phase information of the filtered residual signal; and The phase information is decoded to produce a second digital output representing a filtered residual signal.

16. The method for pipeline analog-to-digital conversion according to claim 15, further comprising: include: filtering the first digital output to produce a first filtered version of a first digital output; filtering the second digital output to produce a second filtered version of the second digital output; and A first filtered version of the first digital output and a second filtered version of the second digital output are combined.

17. The method for pipeline analog-to-digital conversion according to claim 15, further comprising: include: clocking a continuous-time quantizer at a first clock frequency; and The phase information is sampled at a second clock frequency, where the second clock frequency is an integer multiple of the first clock frequency.

18. The method for pipeline analog-to-digital conversion according to claim 17, further comprising: include: extracting a second digital output; and Remove the unwanted image in a decimated version of the second digital output.

19. A pipeline analog-to-digital converter ADC, include: A continuous-time CT residual generation front end is used to receive an analog input signal and generate an amplified residual signal, wherein the CT residual generation front end includes at least two cascaded CT residual generation stages, wherein each CT residual generation stage includes a CT quantizer, a digital-to-analog converter, CT delay circuit and residual amplifier; A voltage controlled oscillator (VCO) ADC back end for receiving and quantizing the remaining signal after amplification; and A digital signal reconstruction filter is used to filter the digital output from the CT residue generation stage and the VCO ADC back end and generate a final digital signal representing the analog input signal.

20. The pipeline ADC of claim 19, wherein the CT residual generation front end does not include any feedback path that feeds any of the digital outputs to the CT residual generation front end.

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