Vertical GaN HEMT (High Electron Mobility Transistor) adopting gradient component ScAIN insertion layer and preparation method of vertical GaN HEMT

Abstract

The invention relates to a vertical GaN HEMT (High Electron Mobility Transistor) adopting a gradient component ScAlN insertion layer and a preparation method of the vertical GaN HEMT. The vertical GaN HEMT comprises a GaN buffer layer arranged on a first surface of a substrate; the first current blocking layer region and the second current blocking layer region are respectively arranged on the edges of the two sides of the buffer layer; the source electrode is arranged on the partial surface of the first current blocking layer area; the GaN layer, the gradient component ScAlN insertion layer, the gradient AlGaN barrier layer and the cap layer are arranged on the buffer layer in a stacked mode, the grid electrode is arranged on the cap layer, and the drain electrode is arranged on the second surface of the substrate; according to the device, on the basis of a vertical HEMT device structure, the GaN channel layer, the gradient component ScAlN insertion layer and the gradient AlGaN barrier layer are stacked, so that the electron mobility and electron concentration distribution of the device are optimized, the linearity of the device is improved, and especially the performance in a high-power environment is improved.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics technology, and in particular to a vertical GaN HEMT using a gradient composition ScAlN insertion layer and a preparation method thereof. Background Art

[0002] As the demand for wireless communication technology continues to grow, the performance requirements of radio frequency (RF) devices are becoming more stringent. High electron mobility transistors (HEMT) are widely used in wireless communication, radar, satellite communication and other fields due to their excellent high frequency and high power characteristics. In particular, gallium nitride (GaN) materials have become the preferred material in RF applications due to their excellent characteristics such as wide bandgap, high breakdown voltage and high electron mobility.

[0003] However, despite the excellent performance of GaN HEMT devices in the RF field, they still face some bottleneck problems in high-frequency applications. The current technology mainly faces the following challenges: improving transconductance and linearity while maintaining low channel resistance. Especially in power amplifiers and switching devices, the improvement of linearity is crucial to signal quality and efficiency.

[0004] In order to solve these problems, in recent years, researchers have used gradient AlGaN barrier layers to optimize the electrical performance of GaN HEMTs. The gradient AlGaN layer adjusts the Al composition, optimizes the electric field distribution, reduces the electric field mutation, alleviates the interface charge accumulation, and reduces the electric field strength between the source and drain, thereby improving the stability and breakdown voltage (BV) of the device. However, although the gradient AlGaN barrier layer can effectively adjust the electric field distribution and improve the DC characteristics of the device, there is still room for further optimization of electron mobility and electron concentration.

[0005] As a highly polarizable material, ScAlN can significantly improve the mobility of electron gas. Compared with traditional AlGaN, ScAlN has a stronger polarization effect, which can reduce electron concentration and electron scattering, thereby effectively improving the electron speed and mobility of the device. However, when optimizing electron mobility, the traditional single-component ScAlN insertion layer often cannot take into account the uniform distribution of electron concentration, which may cause local electric field concentration or uneven electron concentration when the device is working at high power. Summary of the invention

[0006] The present invention provides a vertical GaN HEMT using a gradient composition ScAlN insertion layer and a preparation method thereof, aiming to optimize the power performance, electric field distribution and linearity of the device.

[0007] The present invention provides a vertical GaN structure using a gradient composition ScAlN insertion layer. HEMT, comprising: a substrate having a first surface and a second surface arranged opposite to each other; a GaN buffer layer arranged on the first surface of the substrate; a first current blocking layer region and a second current blocking layer region respectively arranged at the edges of both sides of the buffer layer, extending along the surface of the buffer layer to a certain depth in the buffer layer; a source electrode arranged on a part of the surface of the first current blocking layer region; a GaN layer arranged on the buffer layer, a gradient component ScAlN insertion layer with an Sc component of 10% to 30% arranged on the GaN layer, the Sc component increasing in sequence at equal intervals along the direction from the substrate to the buffer layer, a gradient AlGaN barrier layer arranged on the gradient component ScAlN insertion layer, the Al component gradually changing from 40% to 10% along the direction from the substrate to the buffer layer, a cap layer arranged on the gradient AlGaN barrier layer, a gate arranged on the cap layer, the end faces of the GaN layer, the gradient component ScAlN insertion layer and the gradient AlGaN barrier layer connected to the source electrode; a passivation layer arranged on the gradient AlGaN barrier layer, located between the source electrode and the cap layer; and a drain electrode arranged on the second surface of the substrate. The gradient component ScAlN insertion layer uses the gradient Sc component to more finely control the distribution of the two-dimensional electron gas, more effectively reduce electron scattering, and improve electron mobility. Especially when working in a high-power environment, it significantly improves the linearity of the device and reduces signal distortion, making it suitable for high-power amplifiers and switching devices; the introduction of the gradient AlGaN barrier layer mainly focuses on optimizing the electric field distribution and breakdown voltage by adjusting the Al component. The gradient component ScAlN insertion layer is set between the GaN layer and the gradient AlGaN barrier layer to form a PN junction. The vertical HEMT device mainly withstands the withstand voltage through the PN junction inside the device, effectively reducing the buffer layer leakage problem, so that the GaN area near the gate will not form a high field area, avoiding the breakdown caused by the gate electric field concentration effect, and reducing the specific on-resistance, thereby improving the performance of the device. This setting not only improves the DC characteristics of the device, especially the performance in a high-power environment, but also solves the bottleneck problem of the existing GaN HEMT device in terms of linearity.

[0008] Furthermore, the thickness of the gradient component ScAlN insertion layer is 2 to 6 nm. Furthermore, along the direction of the substrate pointing to the GaN buffer layer, the Sc components are 16%, 18%, 20%, and 22% in sequence, and the thickness of a single Sc component is 1 nm. The setting of the ScAlN insertion layer optimizes the electron mobility and electron concentration distribution, significantly improving the RF performance of the device, especially its excellent performance at high frequencies.

[0009] Furthermore, the Al component of the gradient AlGaN barrier layer gradually changes from 40% to 10% along the direction from the substrate to the GaN buffer layer. The configuration of the gradient AlGaN barrier layer optimizes the DC characteristics of the device, reduces the channel resistance, and improves the working stability of the device.

[0010] Furthermore, the thickness of the graded AlGaN barrier layer is 10-20 nm.

[0011] Furthermore, the current blocking layer is p-type GaN, the thickness of which is 0.5-1.5 μm, and the doping concentration of which is 1e17-1e19.

[0012] Furthermore, the cap layer is p-type GaN, and its thickness is 20-100 nm.

[0013] Furthermore, the substrate is a Si substrate, and an AlN nucleation layer is provided between the Si substrate and the GaN buffer layer, and the thickness of the AlN nucleation layer is 200nm to 400nm.

[0014] Furthermore, the thickness of the GaN buffer layer is 2-8 μm.

[0015] In one aspect, the present invention also provides a method for preparing a vertical GaN HEMT using a gradient composition ScAlN insertion layer, comprising the following steps:

[0016] An AlN nucleation layer and a GaN buffer layer stacked on the AlN nucleation layer are epitaxially grown on the first surface of the Si substrate by using a metal organic chemical vapor deposition process;

[0017] A first p-type GaN current blocking layer region and a second p-type GaN current blocking layer region are respectively formed along the surface of both side edges of the GaN buffer layer to a certain depth in the GaN buffer layer;

[0018] Epitaxially growing a GaN layer, a gradient composition ScAlN insertion layer, a graded AlGaN barrier layer and a p-type GaN cap layer in sequence on the GaN buffer layer;

[0019] Etching along the surface of the p-type GaN cap layer to the surface of the first p-type GaN current blocking layer region to form a source opening;

[0020] Depositing metal in the source opening to form a source;

[0021] Etching along the surface of the p-type GaN cap layer to the surface of the graded AlGaN barrier layer to form a passivation layer opening between the source electrode and the cap layer, and then depositing a passivation layer material in the passivation layer opening;

[0022] Depositing metal on the p-type GaN cap layer to form a gate;

[0023] A metal is deposited on the second surface of the Si substrate to form a drain.

[0024] Furthermore, the first p-type GaN current blocking layer region and the second p-type GaN current blocking layer region are formed by an ion implantation process.

[0025] Compared with the prior art, the vertical GaN HEMT device of the present invention is more suitable for applications in high-voltage and high-power environments. Based on the structure of the vertical HEMT device, the present invention adopts an AlGaN barrier layer with a gradient Al component, and sets a gradient component ScAlN insertion layer with a gradient Sc component between the GaN channel layer and the gradient AlGaN barrier layer. The Sc component increases in a gradient in the direction from the substrate to the buffer layer, optimizes the electron mobility and electron concentration distribution, and adjusts the electric field distribution, so that the device performs well in a high-power environment. Compared with traditional devices, it has a flatter transconductance and maintains good linearity. The device of the present invention is more suitable for applications in high-voltage and high-power environments. The PN junction formed between the GaN channel layer, the gradient component ScAlN insertion layer and the gradient AlGaN barrier layer in the vertical HEMT device withstands the withstand voltage, effectively reducing the problem of buffer layer leakage, so that the GaN region near the gate does not form a high field region, avoiding breakdown caused by the gate electric field concentration effect, and reducing the specific on-resistance. This setting improves the DC characteristics of the device, especially in a high-power environment, the linearity is well improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of the structure of a vertical GaN HEMT device according to an embodiment of the present invention.

[0027] Figure 2 FIG. 1 is a transconductance diagram of a vertical GaN HEMT device according to an embodiment of the present invention and a conventional vertical GaN HEMT device.

[0028] Figure 3 1 is a first-order graph of transconductance of a vertical GaN HEMT device according to an embodiment of the present invention and a conventional vertical GaN HEMT device.

[0029] Figure 4 1 is a second-order graph of transconductance of a vertical GaN HEMT device according to an embodiment of the present invention and a conventional vertical GaN HEMT device.

[0030] Figure 5 1 is an output characteristic diagram of a vertical GaN HEMT device according to an embodiment of the present invention and a conventional vertical GaN HEMT device. DETAILED DESCRIPTION

[0031] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings of the present invention. The described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention. The experimental methods described in the following embodiments are all conventional methods unless otherwise specified; the reagents and materials, unless otherwise specified, can be obtained from public commercial channels.

[0032] Spatially relative terms such as "below," "beneath," "below," "above," "upper," etc. are used in this specification to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures.

[0033] In addition, the use of terms such as "first", "second", etc. to describe various elements, layers, regions, sections, etc. is not intended to be limiting. The use of "having", "containing", "including", "comprising", etc. is open-ended, indicating the presence of the stated elements or features, but does not exclude additional elements or features. Unless the context clearly states otherwise.

[0034] like Figure 1 As shown, an embodiment of the present invention provides a vertical GaN HEMT using a gradient composition ScAlN insertion layer, which includes a substrate 2. In a preferred embodiment, the substrate 2 is a Si substrate. In other embodiments, the substrate may also be other suitable substrates, which are not specifically limited here. The substrate 2 has a first surface and a second surface that are arranged opposite to each other, and an AlN nucleation layer 3 is arranged on the first surface, and the thickness of the AlN nucleation layer is 200nm to 400nm. A GaN buffer layer 4 is arranged on the AlN nucleation layer 3, and the thickness of the GaN buffer layer is 2 to 8 microns.

[0035] The p-type GaN current blocking layer regions are arranged at both sides of the GaN buffer layer. Figure 1As shown, the p-type GaN current blocking layer region includes a first current blocking layer region 51 and a second current blocking layer region 52, and the first and second current blocking layer regions extend along the surface of the GaN buffer layer to a certain depth in the buffer layer. Specifically, the thickness of the first and second current blocking layer regions is 0.5μm to 1.5μm, and the doping concentration thereof is 1e17 to 1e19. In a preferred embodiment, the thickness of the first current blocking layer region 51 is equal to the thickness of the second current blocking layer region 52; in other embodiments, the thicknesses of the two current blocking layer regions may also be unequal. In a preferred embodiment, the current blocking layer region is formed by an ion implantation process. In other embodiments, the regions on both sides of the buffer layer are etched to form an opening in the current blocking layer region, and then a p-type GaN layer is epitaxially grown in the opening to form the first current blocking layer region 51 and the second current blocking layer region 52.

[0036] The GaN channel layer 6 is disposed on the buffer layer 4, with a thickness of 10nm to 20nm, and covers a portion of the first current blocking layer region 51 and the second current blocking layer region 52. The gradient component ScAlN insertion layer 7 is disposed on the GaN layer 6, with a thickness of 2 to 6nm, and a Sc component of 10% to 30%, and the Sc component increases gradually along the direction from the substrate to the buffer layer; in a preferred embodiment, the Sc component along the direction from the substrate to the buffer layer is 16%, 18%, 20%, and 22% in sequence, and the thickness of each Sc component is 1nm.

[0037] The gradient AlGaN layer 8 is arranged on the gradient composition ScAlN insertion layer 7, and its thickness is 10-20nm, the Al composition is 40%-10%, and the Al composition gradually decreases from 40% to 10% along the direction of the substrate pointing to the buffer layer. The gradient composition ScAlN insertion layer is arranged between the GaN channel layer and the gradient AlGaN layer, so as to optimize the electron mobility and electron concentration distribution.

[0038] The cap layer 9 is disposed on the graded AlGaN layer 8, and its thickness is 2nm-5nm. The cap layer is p-type GaN, and its doping concentration is 1e17-1e19.

[0039] The gate 11 is arranged on the cap layer 9. The source groove extends along the surface of the cap layer to a part of the surface of the first current blocking layer region, and the source 10 is arranged in the source groove; the ends of the GaN channel layer 6, the gradient composition ScAlN insertion layer 7 and the gradient AlGaN layer 8 are connected to the source 10, and a passivation layer 12 is arranged between the source 10 and the cap layer 9, and the passivation layer 12 isolates the source and the gate.

[0040] The drain electrode 1 is disposed on the second surface of the substrate 2 .

[0041] An embodiment of the present invention provides a method for preparing the vertical GaN HEMT, comprising the following steps:

[0042] First, a thin layer of Al was grown on a Si substrate using a metal organic chemical vapor deposition (MOCVD) process. Specifically, the Si substrate was placed in a reaction chamber and heated to 940°C. 2 The substrate was heated for 10 min in a molten-salt atmosphere to remove the oxide film on the surface of the substrate, and then the temperature was raised to 1060 °C and TMAl was passed for 12 s.

[0043] Then, an AlN nucleation layer is grown on the thin Al layer. During the growth process, TMA is continuously introduced, and NH 3 The pulsed introduction method is adopted, that is, NH is introduced within the T1 time. 3 , in T 2 NH 3 The flow rate of TMA was 13 sccm, and NH 3 The flow rate is 800 sccm, the T1 time is 12 s, the T2 time is 6 s, the growth thickness is 160 nm, and the AlN nucleation layer growth is completed.

[0044] The GaN buffer layer is then grown epitaxially on the AlN nucleation layer. The growth temperature is 920°C, the pressure is 40 Torr, and the N 2 The flow rate is 500sccm, NH 3 The flow rate of is 5000sccm, the flow rate of TMGa is 220sccm, and the growth thickness of the buffer layer is 2μm~8μm.

[0045] Then, a mask layer is prepared on the buffer layer, and the first current blocking layer pattern and the second current blocking layer pattern are formed by etching. The above-mentioned epitaxial growth process is continued to epitaxially grow p-type GaN in the first current blocking layer pattern and the second current blocking layer pattern region, and the first current blocking layer region and the second current blocking layer region are formed on the edges of both sides of the buffer layer. The growth temperature is 920°C, the pressure is 40Torr, the nitrogen flow rate is 5000sccm, the ammonia flow rate is 5000sccm, and the TMGa flow rate is 220sccm. The etching process adopts ICP etching, and the coil power and platen power of the system are set to 50W and 15W respectively.

[0046] In another embodiment, an ion implantation process is used to form the first current blocking layer region and the second current blocking layer region on both side edges of the buffer layer.

[0047] Then, the MOCVD process was continued to grow a 10nm to 20nm thick GaN layer as a channel layer on the buffer layer and the current blocking layer. The growth temperature was 920℃, the pressure was 40Torr, and the N 2 The flow rate is 500sccm, NH3 The flow rate of is 5000sccm and the flow rate of TMGa is 220sccm.

[0048] A gradient composition ScAlN insertion layer was grown on the GaN channel layer. The growth temperature was set to 1100°C and the total growth thickness was 4 nm. 2 As carrier gas, a continuous supply of Cp 3 ScAlN deposition was performed by changing Cp 3 The flow rate of Sc is used to obtain a gradient composition ScAlN insertion layer. The composition of Sc is 16%, 18%, 20%, and 22% in the direction from the substrate to the upper side of the buffer layer, and the thickness of each Sc component is 1 nm.

[0049] Then, a graded AlGaN barrier layer was grown on the graded composition ScAlN insertion layer using MOCVD process, and N 2 NH 3 , TMGa and TMA, the growth thickness of the gradient AlGaN layer is 15nm, and the flow rate of TMA is gradually reduced, that is, an AlGaN layer with a molar content of Al element gradually changing from 40% to 10% from bottom to top (from the substrate to the buffer layer) is obtained.

[0050] The MOCVD process is continued to be used to epitaxially grow a GaN cap layer with a thickness of 60 nm on the graded AlGaN barrier layer. The growth temperature is 920°C, the pressure is 40 Torr, the nitrogen flow rate is 5000 sccm, the ammonia flow rate is 5000 sccm, and the TMGa flow rate is 220 sccm.

[0051] Next, the surface of the cap layer is etched to the surface of the first current blocking layer region to form a source window, which exposes part of the surface of the first current blocking layer region. Subsequently, a Ti / Al / Ni / Au metal combination is deposited using an electron beam evaporation process. The vacuum degree is less than 1.8×10 -3 Pa, power range is 200~1000W, evaporation rate is The epitaxial wafer was then immersed in an acetone solution for 20 minutes, then ultrasonically cleaned, rinsed with ultrapure water and dried with nitrogen to achieve metal stripping. Subsequently, an ohmic contact annealing was performed at 850°C in a nitrogen atmosphere for 30 seconds to form a source electrode.

[0052] Then the cap layer is etched to form a groove with a width of 2 μm and a thickness of 200 nm between the source and the gate. Then SiN is deposited in the groove as a passivation layer by plasma enhanced chemical vapor deposition at a deposition temperature of 300°C, and high temperature ICP etching is used to remove the passivation layer on the surface of the cap layer.

[0053] Then, the gate window is formed on the cap layer by spin coating photoresist, soft baking, exposure and development, and then Ti / Al / Ni / Au metal combination is deposited by electron beam evaporation. The vacuum degree is less than 1.8×10 -3 Pa, power range is 200~1000W, evaporation rate is After evaporation, the epitaxial wafer was immersed in an acetone solution for 20 minutes, then ultrasonically cleaned, rinsed with ultrapure water and dried with nitrogen to finally obtain the gate.

[0054] The epitaxial wafer is then turned over, the drain area is photolithographically formed on the second surface of the substrate, a drain window is etched, and then a Ti / Al / Ni / Au metal combination is deposited using an electron beam evaporator, Ti / Al / Ni / Au is deposited, and a drain is formed by stripping and annealing.

[0055] Finally, the surface of the epitaxial wafer on which the source, drain and gate have been formed is photolithographically processed to obtain a thickened electrode pattern, and the electrode is thickened by electron beam evaporation to complete the process. Figure 1 The device shown was fabricated.

[0056] Figures 2 to 5 The conventional vertical GaN HEMT device involved in this application is Figure 1 Based on the device structure shown in FIG. 1 , there is no ScAlN insertion layer, and the Al composition of the AlGaN layer is fixed. Figure 2 , 3 4, it can be seen that the transconductance of the device of the present invention is flatter and has better linearity than that of the traditional device. Figure 5 It can be seen that the device of the present invention has a larger output current and is more suitable for applications under high voltage and high power.

[0057] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A vertical GaN HEMT using a gradient composition ScAlN insertion layer, characterized in that: include, A substrate having a first surface and a second surface disposed opposite to each other; A GaN buffer layer disposed on the first surface of the substrate; A first current blocking layer region and a second current blocking layer region are respectively arranged at the edges of both sides of the buffer layer, and extend along the surface of the buffer layer to a certain depth in the buffer layer; A GaN channel layer, a gradient component ScAlN insertion layer, a gradient AlGaN barrier layer and a cap layer are sequentially stacked on the buffer layer, wherein the Sc component of the gradient component ScAlN insertion layer is 10% to 30%, and the Sc component increases in equal intervals in a direction from the substrate to the buffer layer, and the Al component of the gradient AlGaN barrier layer gradually changes from 40% to 10% in a direction from the substrate to the buffer layer; The gate is arranged on the cap layer; A source electrode groove is arranged along a portion of the surface of the cap layer to the first current blocking layer region, and the source electrode is arranged in the source electrode groove; The passivation layer is arranged on the surface of the graded AlGaN barrier layer and is located between the source and the gate; The drain is disposed on the second surface of the substrate.

2. The vertical GaN HEMT device according to claim 1, characterized in that: The thickness of the gradient composition ScAlN insertion layer is 2-6 nm.

3. The vertical GaN HEMT device according to claim 2, characterized in that: Along the direction from the substrate to the GaN buffer layer, the Sc components are 16%, 18%, 20%, and 22% in sequence, and the thickness corresponding to a single Sc component is 1 nm.

4. The vertical GaN HEMT device according to any one of claims 1 to 3, characterized in that: The thickness of the graded AlGaN barrier layer is 10-20 nm.

5. The vertical GaN HEMT device according to claim 4, characterized in that: The current blocking layer is p-type GaN, the thickness thereof is 0.5-1.5 μm, and the doping concentration thereof is 1e17-1e19.

6. The vertical GaN HEMT device according to claim 5, characterized in that: The cap layer is p-type GaN, the thickness of which is 20-100 nm, and the doping concentration of which is 1e17-1e19.

7. The vertical GaN HEMT device according to claim 4 or 5, characterized in that: The substrate is a Si substrate.

8. The vertical GaN HEMT device according to claim 7, characterized in that: An AlN nucleation layer is also arranged between the Si substrate and the GaN buffer layer.

9. A method for preparing a vertical GaN HEMT using a gradient composition ScAlN insertion layer, characterized in that: The following steps are involved: An AlN nucleation layer and a GaN buffer layer stacked on the AlN nucleation layer are epitaxially grown on the first surface of the Si substrate by using a metal organic chemical vapor deposition process; A first p-type GaN current blocking layer region and a second p-type GaN current blocking layer region are respectively formed along the surface of both side edges of the GaN buffer layer to a certain depth in the GaN buffer layer; Epitaxially growing a GaN layer, a gradient composition ScAlN insertion layer, a graded AlGaN barrier layer and a p-type GaN cap layer in sequence on the GaN buffer layer; Etching along the surface of the p-type GaN cap layer to the surface of the first p-type GaN current blocking layer region to form a source opening; Depositing metal in the source opening to form a source; Etching along the surface of the p-type GaN cap layer to the surface of the graded AlGaN barrier layer to form a passivation layer opening between the source electrode and the cap layer, and then depositing a passivation layer material in the passivation layer opening; Depositing metal on the p-type GaN cap layer to form a gate; A metal is deposited on the second surface of the Si substrate to form a drain.

10. The preparation method according to claim 9, characterized in that: The first p-type GaN current blocking layer region and the second p-type GaN current blocking layer region are formed by an ion implantation process.

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