Novel silicon carbide-based wide bandgap semiconductor power device

Abstract

The invention relates to the field of semiconductor materials, in particular to a novel silicon carbide-based wide bandgap semiconductor power device, which is innovated aiming at the problems of high defect density, poor process compatibility and the like of the existing silicon carbide device. According to the invention, material growth, device structure, manufacturing process, performance regulation and control and application multi-dimensional attack is realized, PVT and LPE methods are improved to improve crystal quality, the structure is optimized to reduce electric leakage, high-voltage application is adapted, the process is innovated to improve efficiency and yield, a composite system is expanded, and intelligent planning is integrated. The product has wide application prospects in multiple fields, and the comprehensive performance is remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of information management systems, and particularly to a novel silicon carbide-based wide bandgap semiconductor power device. Background Art

[0002] With the rapid development of power electronics technology towards high voltage, high current, high frequency and miniaturization, traditional silicon-based power devices are approaching their physical limits and are difficult to meet the stringent requirements. Silicon carbide-based wide bandgap semiconductors have great application potential in the fields of new energy vehicles, smart grids, aerospace, etc. due to their wide bandgap, high breakdown electric field and other characteristics. However, the actual manufacturing is full of difficulties. The growth of silicon carbide crystals is prone to introduce defects such as microtubes and dislocations, which seriously affect the electrical properties; and it is not compatible with traditional silicon processes. The development cost of new manufacturing processes is high and the cycle is long, restricting their large-scale commercialization, and innovation breakthroughs are urgently needed. Summary of the Invention

[0003] The present invention provides a novel silicon carbide-based wide bandgap semiconductor power device. The device uses silicon carbide crystals grown by an improved physical vapor transport (PVT) method, which includes: maintaining the temperature of the silicon carbide powder source at 2300 - 2500 °C, introducing titanium-containing organic compound titanium tetrachloride (TiCl 4 ) as a dopant, controlling the doping concentration at 1×10 15 -1×10 17 cm -3 , and optimizing the temperature gradient in the growth chamber to maintain the axial temperature gradient at 10 - 20 °C / cm and control the radial temperature gradient at 5 - 10 °C / cm.

[0004] Furthermore, it also includes a silicon carbide epitaxial layer grown by an innovative liquid phase epitaxy (LPE) method. The innovative LPE method is: selecting gallium-containing metal organic compound trimethylgallium (TMGa), silicon source and carbon source to jointly form a precursor solution, and performing epitaxial growth at 1600 - 1800 °C, adding yttrium-containing organic compound yttrium tris(2,2,6,6-tetramethyl-3,5-heptanedionate) (La(TMHD) 3 ), accounting for 0.01% - 0.05% of the total solution mass.

[0005] Furthermore, the device has an optimized trench gate structure. The trench depth is controlled at 0.5 - 1.5 μm, the trench width is maintained at 0.1 - 0.3 μm, and a trapezoidal trench profile is adopted, wider at the top and narrower at the bottom, with an angle between 60 - 80°, and a hafnium oxide (HfO 2 ) layer with a thickness of about 2 - 5 nm is deposited on the bottom and side walls of the trench.

[0006] Further, the device is a vertical structure silicon carbide power device, which includes: a buffer layer, a drift layer, and an active layer grown sequentially on the basis of a silicon carbide substrate. The buffer layer is made of nitrogen-doped silicon carbide with a thickness of 0.1 - 0.3 μm, the drift layer has a thickness of 5 - 10 μm, and the active layer has a thickness of 0.2 - 0.5 μm.

[0007] Further, the method for the novel silicon carbide-based wide bandgap semiconductor power device includes an upgrade step of the lithography process. Extreme ultraviolet lithography (EUV) technology is adopted, combined with a high-precision photoresist, and the lithography resolution reaches 10 - 20 nm. The exposure dose is between 50 - 100 mJ / cm 2 ², and the development time is precisely controlled within 30 - 60 seconds.

[0008] Further, it also includes an optimization step of the high-temperature annealing process. Pulsed high-temperature annealing is used, the peak annealing temperature is set at 1800 - 2000 °C, the pulse width is 1 - 5 seconds, the interval time is 5 - 10 seconds, and it is repeated 3 - 5 times.

[0009] Further, for the new energy vehicle motor drive system with the novel silicon carbide-based wide bandgap semiconductor power device, by utilizing the high switching frequency and low on-state loss characteristics of the device, the motor drive efficiency is improved, energy loss is reduced, the vehicle cruising range is extended, and the volume and weight of the motor control system are reduced.

[0010] Further, for the intelligent power grid high-voltage DC transmission application system with the novel silicon carbide-based wide bandgap semiconductor power device, relying on the high voltage withstand and high-power processing capabilities of the device, the power loss and heat dissipation requirements of the converter station are reduced, and the stability and reliability of the power transmission system are improved.

[0011] Further, for a composite wide bandgap semiconductor system, silicon carbide is compounded with gallium nitride (GaN), and the compounding ratio is between 1:1 - 3:1. It is formed by heteroepitaxy or bonding technology. By leveraging the high electron mobility of GaN and the high breakdown electric field of silicon carbide, it has both fast switching and high voltage withstand capabilities.

[0012] Further, for the intelligent process planning software used to manufacture the novel silicon carbide-based wide bandgap semiconductor power device, by inputting key parameters such as target electrical performance indicators, cost budget, production scale, etc., it automatically generates a detailed process flow covering material formulation, process route, and parameter setting, and continuously iteratively optimizes in combination with machine learning to improve the yield and manufacturing efficiency of the device.

[0013] Beneficial effects:

[0014] Improved electrical performance: Through coordinated optimization of materials and structures, the device breakdown voltage is 20%-40% higher than that of traditional silicon carbide power devices, the on-resistance is reduced by 30%-50%, and the switching speed is significantly faster. Thanks to precise crystal growth control, defects are reduced and carrier transmission is smoother; optimized grooves and vertical structures strengthen electric field distribution and carrier confinement, allowing the device to work stably at higher frequencies and higher powers.

[0015] Excellent crystal quality: The improved PVT and LPE growth methods have achieved remarkable results, reducing the defect density of silicon carbide crystals by 50%-70%, and greatly improving the flatness and uniformity of the epitaxial layer. The doping elements are precisely introduced to adsorb impurities and stabilize the structure, and the reasonable temperature gradient ensures uniform growth, laying a solid foundation for high-performance devices and reducing the discrete electrical performance and reliability risks caused by crystal defects. Stability is as solid as a rock: With the optimized process and composite system, the device can run continuously for 1000 hours under high temperature of 200℃ and high voltage of 10kV, and the performance retention rate is still greater than 90%. Pulsed high-temperature annealing activates doping and controls defects. The composite system integrates the advantages of different materials, relieves thermal and electrical stresses, ensures long-term stable operation, and reduces maintenance costs and system failure risks. Efficient and high-quality manufacturing: The upgrade of manufacturing processes has led to a 30%-50% increase in production efficiency, a 20%-30% increase in the yield rate of large-area preparation, and good batch consistency. Advanced photolithography ensures the formation of fine structures, and intelligent process planning accurately generates processes based on parameters. With the help of machine learning iteration, process defects can be avoided efficiently, and high-quality devices can be stably produced, which meets the requirements of large-scale industrial production. Diversified application expansion: In the field of new energy vehicles, high switching frequency and low conduction loss characteristics help improve the efficiency of motor drives, extend battery life, and reduce size; in smart grid applications, high withstand voltage and high power capabilities reduce converter station losses and enhance power transmission stability. It has been successfully implemented in multiple fields, opening up emerging markets, and meeting the diverse needs of energy transformation and high-end equipment for power devices.

[0016] Composite system efficiency enhancement: After compounding with gallium nitride and other materials, the electrical performance is improved by 10%-20%, unlocking ultra-high frequency and ultra-high power scenarios. It integrates the advantages of different wide bandgap semiconductors, makes up for the shortcomings of a single material, broadens the scope of application of devices, and generates technical solutions for more challenging applications.

[0017] Intelligent control empowerment: Intelligent process planning software combines machine learning to continuously optimize processes and steadily increase the yield rate. Dynamic response to process fluctuations and precise control of parameters allow device manufacturing to move from experience-based to data-driven intelligence, accelerating technology iteration and cost reduction.

[0018] Worry-free low-temperature performance: Containing ethylene glycol additives and process optimization, the electrical performance degradation at -40°C is less than 15%, ensuring application in extreme environments. Ethylene glycol improves the low-temperature toughness of the material, maintains the stability of the crystal and device structure, enables the device to stably supply energy in cold conditions, and expands the application boundaries.

[0019] Self-healing and durable: Incorporating organic small molecules containing disulfide bonds endows the device with self-healing ability. Once microcracks appear inside, the disulfide bonds function under heat or light to repair the cracks, interrupt the process of performance degradation, extend the service life of the device, and improve the cost performance during the usage period.

[0020] Miniature and customizable: Relying on MEMS technology, miniaturized device customization is achieved to meet the stringent requirements of implantable medical applications and micro sensors. By precisely controlling the molds and parameters, power devices with small sizes and adapted to special scenarios are shaped, filling the gap in power supply in the microscopic field. Detailed implementation methods

[0021] Example 1:

[0022] Growth of silicon carbide crystals by PVT method and efficiency enhancement test

[0023] 1. Experimental preparation

[0024] 1. Select high-purity silicon carbide powder as the source material and place it in a graphite crucible of a physical vapor transport (PVT) growth device. Prepare titanium-containing organic compound titanium tetrachloride (TiCl 4 ), accurately configure the dopant solution to ensure that the doping concentration can be precisely controlled at 1×10 15 cm -3 .

[0025] 2. Calibrate the temperature sensor and heating device in the growth chamber to ensure that the temperature control accuracy is within the range of ±1°C, preparing for precise control of the temperature gradient.

[0026] 2. Growth process

[0027] 1. Turn on the device and slowly increase the temperature to gradually raise the temperature of the silicon carbide powder source to 2300°C. At the same time, through a precise gas delivery system, introduce the TiCl 4 dopant into the growth chamber at a constant and controllable rate.

[0028] 2. Fine-tune the heating power to maintain an axial temperature gradient of 10°C / cm and a radial temperature gradient of 5°C / cm. During the entire growth cycle (about 50 hours), continuously monitor the crystal growth rate, record data every hour, and observe that the initial growth rate is relatively slow, about 0.1 mm / h, and the later growth rate stabilizes at 0.2 - 0.3 mm / h as the temperature and doping environment stabilize.

[0029] 3. Efficiency enhancement test

[0030] 1. Control group setting: Set up a group without adding TiCl 4A control group doped with dopants and using a traditional temperature gradient (30 °C / cm axially and 15 °C / cm radially). The growth experiments of the two groups started simultaneously, and other basic conditions were kept the same.

[0031] 2. Crystal quality detection: After the growth was completed, the X-ray diffractometer (XRD) was used to analyze the structural integrity of the crystal. It was found that the full width at half maximum of the diffraction peak of the crystal in the experimental group was 30% narrower than that in the control group, indicating that the crystal defect density was significantly reduced; then, the number of surface microtubes was observed through an optical microscope. There were only 5 - 10 microtubes per square centimeter in the experimental group, while it was as high as 50 - 80 in the control group, fully confirming that this method has a significant effect on improving the crystal quality.

[0032] 3. Preliminary electrical property measurement: A simple diode structure was fabricated from the small pieces of the cut crystal, and the breakdown voltage was measured. The average breakdown voltage of the experimental group reached 1800 V, while that of the control group was only 1200 V, initially showing the positive effect of this growth method on the electrical properties of subsequent devices.

[0033] Example 2

[0034] Growth of epitaxial layer by LPE method and efficiency enhancement experiment

[0035] 1. Experimental preparation

[0036] 1. Accurately weigh gallium-containing metal organic compound trimethylgallium (TMGa), silicon source, and carbon source in proportion, and prepare a precursor solution in a glove box protected by inert gas. Then add yttrium-containing organic compound yttrium tris(2,2,6,6-tetramethyl-3,5-heptanedionate) (La(TMHD) 3 ) accounting for 0.01% of the total solution mass, and stir well.

[0037] 2. The silicon carbide substrate was strictly cleaned and pretreated to remove surface impurities and oxide layers to ensure a clean growth interface for the epitaxial layer.

[0038] 2. Growth process

[0039] 1. The substrate was placed in a high-temperature reaction furnace, heated to 1600 °C, and the precursor solution was injected at a constant speed to start the growth of the epitaxial layer. During the growth, the reflection high-energy electron diffraction (RHEED) was used to monitor the growth state of the epitaxial layer in real time, and the solution flow rate was adjusted timely according to the change of diffraction fringes to ensure that the growth rate was stable at 0.5 - 1 μm / min.

[0040] 2. The temperature, pressure and other parameters in the furnace were monitored throughout the process. The total growth time was set to 3 hours, and finally an epitaxial layer with a thickness of about 1.5 - 3 μm was obtained.

[0041] 3. Efficiency enhancement experiment

[0042] 1. Comparative sample: Prepare a group without La(TMHD)3 And a conventional epitaxial layer sample without TMGa regulation was used as a comparison.

[0043] 2. Flatness detection: The surface of the epitaxial layer was scanned using an atomic force microscope (AFM). The RMS value of the surface roughness of the experimental group was 0.5 - 1 nm, while that of the control group reached 3 - 5 nm, clearly indicating that the introduction of gallium and yttrium elements greatly improved the flatness of the epitaxial layer.

[0044] 3. Stacking fault analysis: The microstructure of the epitaxial layer was observed using a transmission electron microscope (TEM), and the stacking fault density was counted. The stacking fault density of the experimental group was reduced by 60% compared to the control group, strongly proving that this innovative method can reduce the defects of the epitaxial layer and improve the quality.

[0045] 4. Electrical property correlation test: MOSFET structure test devices were fabricated on the two groups of epitaxial layers, and the consistency of the threshold voltage was compared. The threshold voltage deviation of the experimental group was within ±3%, while that of the control group exceeded 10%, highlighting the improvement of the electrical property uniformity of the subsequent devices by this method.

[0046] Example 3:

[0047] Fabrication and efficiency enhancement test of trench gate devices

[0048] 1. Experimental preparation

[0049] 1. Select silicon carbide wafers grown by the optimized PVT method above and cut them into chip substrates of appropriate sizes. Prepare ultra-high purity hafnium oxide (HfO 2 ) target materials for subsequent deposition processes.

[0050] 2. Design a photolithography mask plate to accurately determine the shape and size of the trenches. The trench depth is set to 0.5 μm, the width is 0.1 μm, and the trapezoidal trench profile angle is designed to be 60°.

[0051] 2. Fabrication process

[0052] 1. Transfer the trench pattern to the chip surface using photolithography technology, and strictly control the exposure dose at 50 mJ / cm 2 , and the development time is 30 seconds. Subsequently, use reactive ion etching (RIE) technology to etch out the set trench structure.

[0053] 2. Deposit an HfO layer with a thickness of about 2 nm on the bottom and side walls of the trenches through atomic layer deposition (ALD) technology. During the deposition process, accurately control the precursor pulse time and purge time to ensure the uniformity and density of the film layer. 2 3. Efficiency enhancement test

[0054] 3. Efficiency enhancement test

[0055] 1. Comparative device: Fabricate a set of traditional trench-gate devices with a trench depth of 0.3 μm, a width of 0.2 μm, and without HfO 2 deposition as a comparison.

[0056] 2. Gate leakage test: Under the same bias conditions, measure the gate leakage current of the two sets of devices using a high-precision ammeter. The gate leakage current of the experimental group is at the order of 1×10 -12 A, and that of the comparison group reaches 1×10 -10 A, highlighting the role of optimizing the trench structure and HfO 2 deposition in reducing gate leakage.

[0057] 3. Switching performance evaluation: Build a high-frequency switch test circuit to test the switching speed of the devices. The rise time and fall time of the experimental group are 30% shorter than those of the comparison group, fully indicating that the structural optimization can improve the switching performance of the devices.

[0058] 4. Long-term stability monitoring: Place the two sets of devices in an environment of high temperature (150 °C) and high voltage (800 V), and test the electrical properties every 100 hours. After 500 hours, the performance retention rate of the experimental group is 95%, while that of the comparison group is only 80%, indicating that the devices fabricated by this process have better long-term stability.

[0059] Example 4:

[0060] Vertical structure device assembly and efficiency enhancement experiment

[0061] 1. Experimental preparation

[0062] 1. Prepare silicon carbide epitaxial layer materials with different doping types and concentrations for constructing the buffer layer, drift layer, and active layer. The buffer layer uses nitrogen-doped silicon carbide, and precisely control the doping concentration according to the process requirements. Prepare buffer layer materials with a thickness of 0.1 μm; the drift layer material has a thickness of 5 μm, and the active layer material has a thickness of 0.2 μm.

[0063] 2. Design the metallization electrode pattern and select appropriate metal evaporation materials, such as aluminum and titanium alloy, to ensure good ohmic contact performance.

[0064] 2. Assembly process

[0065] 1. On the silicon carbide substrate, precisely stack the buffer layer, drift layer, and active layer through process steps such as epitaxial growth, photolithography, etching, and metallization in sequence. After the growth of each layer is completed, conduct in-situ detection, and use secondary ion mass spectrometry (SIMS) to analyze the doping concentration distribution to ensure compliance with the design requirements.

[0066] 2. After the assembly of each layer is completed, high-temperature annealing treatment is carried out. Pulse high-temperature annealing is adopted. The peak annealing temperature is set at 1800°C, the pulse width is 1 second, the interval time is 5 seconds, and it is repeated 3 times to activate the doped atoms and optimize the electrical contact between the layers.

[0067] 3. Synergistic test

[0068] 1. Comparison structure: A set of vertical structure devices with imbalanced thickness ratios of buffer layer, drift layer, and active layer (buffer layer 0.05 μm, drift layer 3 μm, active layer 0.1 μm) and conventional annealing method were constructed.

[0069] 2. Withstand voltage test: Using professional high-voltage testing equipment, the voltage was gradually increased until the device broke down. The breakdown voltage of the experimental group reached 3500V, while that of the control group was only 2500V, which clearly demonstrated the effect of reasonable layer structure design on improving withstand voltage capability.

[0070] 3. Carrier transport analysis: The Hall effect test system was used to measure the carrier mobility of the active layers of the two groups of devices. The carrier mobility of the experimental group was 40% higher than that of the control group, indicating that optimizing the interlayer structure is conducive to efficient carrier transport.

[0071] 4. Long-term reliability assessment: The device was placed under high-power cycling conditions to simulate current and voltage fluctuations in actual applications. After running for 1,000 hours, the performance of the experimental group declined by 5%, while that of the control group declined by 15%, highlighting the high reliability of the device under this assembly process.

[0072] Embodiment 5:

[0073] Silicon carbide-GaN composite system and efficiency enhancement test

[0074] 1. Experimental Preparation

[0075] 1. Prepare high-quality silicon carbide and gallium nitride (GaN) materials, and use chemical vapor deposition (CVD) equipment as a composite preparation platform. Accurately adjust the reaction gas flow rate and set the ratio of silicon carbide and GaN source gas to initially control the composite ratio at 1:1.

[0076] 2. Design a special gas distribution device to ensure that the two materials are evenly mixed during the growth process to avoid local uneven composition.

[0077] 2. Composite process

[0078] 1. First, evacuate the reaction chamber to a low vacuum state, and then introduce inert gas as a protective gas. Gradually increase the temperature to the composite growth temperature, start the source gas supply of silicon carbide and GaN, and use in-situ spectral monitoring technology during the growth process to monitor the material growth rate and composition changes in real time, and fine-tune the gas flow rate based on feedback to ensure the quality of the composite layer.

[0079] 2. The total growth duration is about 8 hours to obtain a silicon carbide-GaN composite layer with a thickness of about 5-8 μm.

[0080] 3. Synergy test

[0081] 1. Comparative composite samples: Prepare a group of composite samples with a silicon carbide to GaN ratio of 2:1 without using an optimized gas distribution device.

[0082] 2. Comprehensive electrical performance test: Fabricate Schottky diode structure devices and test the forward conduction voltage, reverse breakdown voltage, and switching speed. The forward conduction voltage of the experimental group is reduced by 15%, the reverse breakdown voltage is increased by 20%, and the switching speed is increased by 25%. The improvement amplitude of each index in the control group is less than 10%, indicating the importance of precisely controlling the composite ratio and growth process.

[0083] 3. Thermal stability test: Place the two groups of devices on a high-temperature hot plate and gradually heat from room temperature to 300 °C. Test the electrical performance every 50 °C. The decline amplitude of the electrical performance of the experimental group at high temperature is 30% smaller than that of the control group, indicating that the optimized composite system has stronger thermal stability.

[0084] 4. Microstructural characterization: Observe the composite interface through high-resolution transmission electron microscopy (HRTEM). The interface of the experimental group is clear and flat, without obvious defects and lattice mismatch, while the control group has more lattice distortions, verifying the advantages of this process again.

[0085] Example 6:

[0086] Intelligent process planning and synergy test

[0087] 1. Experimental preparation

[0088] 1. Develop the basic framework of intelligent process planning software and input various process parameter ranges, material property databases, and key parameter templates such as target electrical performance indicators, cost budgets, and production scales for silicon carbide-based wide-bandgap semiconductor power devices.

[0089] 2. Collect process data from multiple previous batches, including the yield rate and electrical performance test results under different parameter settings, for the initial training of machine learning algorithms.

[0090] 2. Planning and production

[0091] 1. Input a set of typical target parameters, such as a breakdown voltage of 4000 V, a conduction resistance less than 10 mΩ, a cost budget of $50 per chip, and a production scale of 1000 chips per month. The software automatically generates a detailed process flow covering material formulations, process routes, and parameter settings.

[0092] 2. Carry out small-batch trial production (50 pieces) based on the generated process plan, set up multiple monitoring points on the production line, and feed back production data to the software in real time.

[0093] 3. Synergistic test

[0094] 1. Comparison with traditional process: A group of batches produced with traditional fixed process parameters were selected for comparison, and the batch also produced 50 pieces.

[0095] 2. Yield rate statistics: After completing production and preliminary electrical performance screening, the yield rate was counted. The yield rate of the experimental group reached 85%, while that of the control group was only 60%, highlighting the significant role of intelligent process planning in improving the yield rate.

[0096] 3. Cost-benefit analysis: A detailed calculation of the raw material loss, equipment operating time, and labor intervention costs in the two groups' production processes revealed that the cost of the experimental group was 20% lower than that of the control group, mainly due to the precise material formula and process route optimization.

[0097] Iterative optimization verification: The trial production data was fed back to the software for iterative optimization using machine learning, and 50 pieces were put into production again. The yield rate was further improved to 90%, proving the software's continuous optimization capabilities and laying the foundation for large-scale and efficient production.

Claims

1. A novel silicon carbide-based wide bandgap semiconductor power device, characterized in that: The device adopts a silicon carbide crystal grown by a physical vapor transport method. The method comprises: maintaining the temperature of a silicon carbide powder source at 2300-2500°C, introducing a titanium-containing organic compound titanium tetrachloride (TiCl4) as a dopant, and controlling the doping concentration at 1×10 15 -1×10 17 cm-3, and optimize the temperature gradient in the growth chamber so that the axial temperature gradient is maintained at 10-20℃ / cm and the radial temperature gradient is controlled at 5-10℃ / cm.

2. The novel silicon carbide-based wide bandgap semiconductor power device according to claim 1, characterized in that: It also includes a silicon carbide epitaxial layer grown by liquid phase epitaxy: a gallium-containing metal organic compound trimethylgallium (TMGa) is selected to form a precursor solution together with a silicon source and a carbon source, and epitaxial growth is carried out at 1600-1800°C, and an yttrium-containing organic compound tris(2,2,6,6-tetramethyl-3,5-heptanedione) yttrium is added, accounting for 0.01%-0.05% of the total solution mass.

3. The novel silicon carbide-based wide bandgap semiconductor power device according to claim 1 or 2, characterized in that: The device has a trench gate structure, the trench depth is controlled at 0.5-1.5 μm, the trench width is maintained at 0.1-0.3 μm, a trapezoidal trench profile is adopted, which is wide at the top and narrow at the bottom, and the angle is between 60-80 degrees. A hafnium oxide layer with a thickness of about 2-5 nm is deposited on the bottom and sidewalls of the trench.

4. The novel silicon carbide-based wide bandgap semiconductor power device according to claim 3, characterized in that: The device is a vertical structure silicon carbide power device, which comprises: a buffer layer, a drift layer, and an active layer grown in sequence based on a silicon carbide substrate, wherein the buffer layer is made of nitrogen-doped silicon carbide with a thickness of 0.1-0.3 μm, the drift layer has a thickness of 5-10 μm, and the active layer has a thickness of 0.2-0.5 μm.

5. A method for manufacturing the novel silicon carbide-based wide bandgap semiconductor power device according to claim 4, characterized in that: Including the lithography process upgrade steps, using extreme ultraviolet lithography technology, combined with high-precision photoresist, lithography resolution of 10-20nm, exposure dose of 50-100mJ / cm 2 The developing time is precisely controlled between 30 and 60 seconds.

6. The manufacturing method according to claim 5, characterized in that: It also includes a high temperature annealing process optimization step, using pulsed high temperature annealing, with the annealing temperature peak set at 1800-2000° C., a pulse width of 1-5 seconds, an interval time of 5-10 seconds, and repeated 3-5 times.

7. A new energy vehicle motor drive system using the novel silicon carbide-based wide bandgap semiconductor power device according to any one of claims 1 to 4, characterized in that: The high switching frequency and low conduction loss characteristics of the device are utilized to improve motor drive efficiency and reduce energy loss, thereby extending vehicle range and reducing the size and weight of the motor control system.

8. A smart grid high voltage direct current transmission application system using the novel silicon carbide based wide bandgap semiconductor power device according to any one of claims 1 to 4, characterized in that: With the high voltage resistance and high power handling capability of the device, Reduce the power loss and heat dissipation requirements of the converter station, and improve the stability and reliability of the transmission system.

9. A composite wide bandgap semiconductor system, characterized in that: Silicon carbide and gallium nitride are compounded in a ratio of 1:1-3:1 through heteroepitaxial growth or bonding technology. By leveraging the high electron mobility and high breakdown electric field advantages of silicon carbide, it has both fast switching and high voltage resistance performance.

10. An intelligent process planning software for manufacturing the novel silicon carbide-based wide bandgap semiconductor power device according to any one of claims 1 to 4, characterized in that: By inputting key parameters such as target electrical performance indicators, cost budget, production scale, etc., a detailed process flow covering material formula, process route, and parameter setting is automatically generated, and continuous iterative optimization is performed in combination with machine learning to improve the yield rate and manufacturing efficiency of the device.