Anti-aliasing down-sampling circuit, circuit module, chip and signal processing device

Abstract

The invention provides an anti-aliasing down-sampling circuit, a circuit module, a chip and a signal processing device. The anti-aliasing down-sampling circuit comprises a first multiplication accumulation module, at least one second multiplication accumulation module, a third multiplication accumulation module, a mode I counter and a latch register, the first input ends of the first to third multiply accumulation modules are connected together, the second input end of the first multiply accumulation module inputs data 0, the output end of the first multiply accumulation module is connected with the second input end of the second multiply accumulation module, and the output end of the second multiply accumulation module is connected with the second input end of the third multiply accumulation module; the output end of the third multiplication and accumulation module is connected with the latch register; the modular I counter is connected with control input ends of the first to third multiplication and accumulation modules and the latch register, and the first to third multiplication and accumulation modules perform multiplication and accumulation; the latch register outputs an I-time down-sampling result; and the number of the second multiplication accumulation modules is determined according to the order of the filter and the modulus value I of the modulus I counter.

Description

Technical Field

[0001] The present application relates to the field of digital signal processing, and particularly to an anti-aliasing decimation circuit, a circuit module, a chip, and a signal processing device. Background Art

[0002] In the field of digital signal processing, decimation, as a common technique for reducing the signal sampling rate, has important application value. However, direct decimation easily causes high-frequency components in the signal spectrum to fold into the low-frequency part, resulting in aliasing, which seriously affects the signal quality. To effectively solve this problem, an anti-aliasing filter is usually used before decimation to remove high-frequency components above the Nyquist frequency. Currently, the anti-aliasing filter usually adopts an FIR filter, which, as a non-recursive filter, has advantages such as linear phase and stability, and its output only depends on the input.

[0003] However, the existing decimation techniques have certain defects. In the decimation circuit, if the anti-aliasing filter and the decimation extraction circuit are implemented separately, a large amount of redundant operations will be generated. These redundant operations not only increase the processing complexity but also cause a significant increase in the power consumption of the decimation circuit, which is not conducive to the energy conservation and efficient operation of digital signal processing devices and limits their application in scenarios with strict power consumption requirements. Therefore, there is an urgent need for a new anti-aliasing decimation circuit to reduce redundant operations. Summary of the Invention

[0004] Based on the above situation, the main purpose of the present application is to provide an anti-aliasing decimation circuit, a circuit module, a chip, and a signal processing device to reduce redundant operations.

[0005] To achieve the above purpose, the technical solution adopted in the present application is as follows: An anti-aliasing decimation circuit includes: a first multiply-accumulate module, at least one second multiply-accumulate module, a third multiply-accumulate module, a I modulo counter, and a latch register; Among them, the first input ends of the first multiply-accumulate module, the second multiply-accumulate module, and the third multiply-accumulate module are connected together, the second input end of the first multiply-accumulate module inputs data 0, the output end of the first multiply-accumulate module is connected to the second input end of the second multiply-accumulate module, the output end of the second multiply-accumulate module is connected to the second input end of the third multiply-accumulate module, and the output end of the third multiply-accumulate module is connected to the latch register; The I modulo counter is connected to the control input ends of the first multiply-accumulate module, the second multiply-accumulate module, the third multiply-accumulate module, and the latch register, and the IThe value of the counting variable of the counter increases with the change of the clock cycle. Under the control of the value of the counting variable, the first multiply-accumulate module selects corresponding filter coefficients, and 0 or the accumulation result of the first multiply-accumulate module. The second multiply-accumulate module selects corresponding filter coefficients, and the output result of the first multiply-accumulate module or the accumulation result of the second multiply-accumulate module. The third multiply-accumulate module selects corresponding filter coefficients, and the output result of the second multiply-accumulate module or the accumulation result of the third multiply-accumulate module to perform multiplication and accumulation operations; According to the value of the counting variable, the latch register outputs I the decimated result; The number of the second multiply-accumulate modules is determined according to the filter order and the I modulo value of the counter I of the counter.

[0006] Optionally, according to the filter order M and the I modulo value of the counter I , the second multiply-accumulate modules are set to be pieces.

[0007] Optionally, the first input ends of the second multiply-accumulate modules are connected together, the second input ends are connected to the output ends of the adjacent first multiply-accumulate module or the output ends of the adjacent previous second multiply-accumulate module, and the output ends of the second multiply-accumulate modules are connected to the second input ends of the adjacent next second multiply-accumulate module or the input ends of the adjacent third multiply-accumulate module.

[0008] Optionally, the first multiply-accumulate module includes a first multiplier, a first adder, a first multiplexer and a first accumulation register. The filter coefficients and input data corresponding to the first multiply-accumulate module are input into the first multiplier for multiplication operations; The first multiplexer selects and outputs 0 or the output result of the first accumulation register under the control of the value of the counting variable of the I modulo counter. The first adder adds the output result of the first multiplier and the result selected and output by the first multiplexer; The first accumulation register stores the output result of the first adder, and uses the stored result as the input of the second multiply-accumulate module, and inputs the stored result into the first adder through the first multiplexer.

[0009] Optionally, the second multiply-accumulate module includes a second multiplier, a second adder, a second multiplexer, and a second accumulator register. The filter coefficients and input data corresponding to the second multiply-accumulate module are input to the second multiplier for multiplication operations; The second multiplexer selects and outputs the output result of the first accumulator register or the output result of the second accumulator register under the control of the value of the count variable of the modulo I counter. The second adder performs an addition operation on the output result of the second multiplier and the result selected and output by the second multiplexer; The second accumulator register stores the output result of the second adder, uses the stored result as the input of the third multiply-accumulate module, and inputs the stored result to the second adder through the second multiplexer.

[0010] Optionally, the third multiply-accumulate module includes a third multiplier, a third adder, a third multiplexer, and a third accumulator register. The filter coefficients and input data corresponding to the third multiply-accumulate module are input to the third multiplier for multiplication operations; The third multiplexer selects and outputs the output result of the second accumulator register or the output result of the third accumulator register under the control of the value of the count variable of the modulo I counter. The third adder performs an addition operation on the output result of the third multiplier and the result selected and output by the third multiplexer; The third accumulator register stores the output result of the third adder, inputs the stored result to the latch register for latching, and inputs the stored result to the third adder through the third multiplexer.

[0011] Optionally, according to the filter order M and the modulo I value of the modulo I counter, M +1 filter coefficients are written into coefficient tables, and each coefficient table contains I filter coefficients.

[0012] Optionally, when M +1 is not an integer multiple of I , some filter coefficients in the th coefficient table are padded with 0s.

[0013] Optionally, the value range of the count variable is 0 to I -1.

[0014] Optionally, when the value of the counting variable is 0: The first multiplexer selects and outputs 0. The first adder adds 0 to the output result of the first multiplier, and the output result of the first adder is stored in the first accumulative register. The second multiplexer selects and outputs the output result of the first accumulative register. The second adder adds the output result of the first accumulative register to the output result of the second multiplier, and the output result of the second adder is stored in the second accumulative register. The third multiplexer selects and outputs the output result of the second accumulative register. The third adder adds the output result of the second accumulative register to the output result of the third multiplier, and the output result of the third adder is stored in the third accumulative register. The output result of the third accumulative register is input to the latch register for latching.

[0015] Optionally, when the value of the counting variable is 1 to I -1: The first multiplexer selects and outputs the output result of the first accumulative register in the previous clock cycle. The first adder adds the output result of the first accumulative register in the previous clock cycle to the output result of the first multiplier, and the output result of the first adder is stored in the first accumulative register. The second multiplexer selects and outputs the output result of the second accumulative register in the previous clock cycle. The second adder adds the output result of the second accumulative register in the previous clock cycle to the output result of the second multiplier, and the output result of the second adder is stored in the second accumulative register. The third multiplexer selects and outputs the output result of the third accumulative register in the previous clock cycle. The third adder adds the output result of the third accumulative register in the previous clock cycle to the output result of the third multiplier, and the output result of the third adder is stored in the third accumulative register. The output result of the third accumulative register is input to the latch register for latching.

[0016] Optionally, when the value of the counting variable is I -1, the result stored in the third accumulative register is used as the I decimated result and is input to the latch register for latching.

[0017] The embodiment of the present application also provides a circuit module, including the anti-aliasing decimation circuit described in any one of the above.

[0018] The embodiment of the present application also provides a chip, including the anti-aliasing decimation circuit described in any one of the above.

[0019] The embodiment of the present application also provides a signal processing device, including the above circuit module or chip.

[0020] By setting the first multiply-accumulate module, at least one second multiply-accumulate module, a third multiply-accumulate module, a modulo I counter and a latch register, the multiplication operations and addition operations are evenly distributed within I clock cycles, and the multipliers and adders in the first multiply-accumulate module, the second multiply-accumulate module, and the third multiply-accumulate module are I reused for

[0021] times, which can eliminate redundant operations, save a large amount of computing time, enable calculations that originally required multiple clock cycles to be completed in a shorter time, and thus improve the operation speed of the entire circuit system. Redundant operations usually occupy logic resources such as multipliers and adders in the circuit. By eliminating redundant operations, these logic resources can be released, thereby improving resource utilization. Intermediate results generated by redundant operations usually need to be stored in registers. By eliminating redundant operations, storage resources can be saved.

[0022] The circuit module provided by the embodiment of the present application has excellent anti-aliasing performance and flexible downsampling ability. At the same time, it integrates other practical functions, which can meet the diverse requirements of different applications for signal processing.

[0023] Other beneficial effects of the present application will be described in the specific implementation manners through the introduction of specific technical features and technical solutions. Those skilled in the art should be able to understand the beneficial technical effects brought by the technical features and technical solutions through these introductions. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The preferred embodiments of the present application will be described below with reference to the accompanying drawings.

[0025] Figure 1 is the structural block diagram of the anti-aliasing downsampling module in the prior art; Figure 2 is Figure 1 the specific implementation structural block diagram of the anti-aliasing downsampling module in Figure 3 is the structural block diagram of the anti-aliasing downsampling circuit of a preferred embodiment of the present application.

[0026] In the figure: 10. First multiplication and accumulation module; 101. First multiplier; 102. First adder; 103. First multiplexer; 104. First accumulation register; 20. Second multiplication and accumulation module; 201. Second multiplier; 202. Second adder; 203. Second multiplexer; 204. Second accumulation register; 30. Third multiplication and accumulation module; 301. Third multiplier; 302. Third adder; 303. Third multiplexer; 304. Third accumulation register; 40. Modulo I counter; 50. Latch register. Detailed implementation manner

[0027] The following describes the present application based on embodiments, but the present application is not limited to these embodiments. In the following detailed description of the present application, some specific details are described in detail. In order to avoid obscuring the essence of the present application, well-known methods, processes, procedures, and components are not described in detail.

[0028] In addition, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only, and the drawings are not necessarily drawn to scale.

[0029] Unless the context clearly requires otherwise, the words such as "including", "comprising", etc. throughout the specification and claims should be interpreted in an inclusive sense rather than an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".

[0030] In the description of the present application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, in the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0031] In a digital signal processing system, sometimes it is necessary to reduce the sampling rate of a signal, that is, perform a downsampling operation. Before downsampling, it is necessary to use an anti-aliasing filter to filter the digital signal. This is because downsampling will change the spectrum of the signal. If the components with frequencies higher than half of the new sampling rate (i.e., the Nyquist frequency) are not filtered out in advance, aliasing will occur. For example, in video processing, when it is necessary to downsample a high-frame-rate video to a low-frame-rate video, the video signal is first processed by a digital anti-aliasing filter to remove high-frequency components, and then the downsampling operation is performed to avoid aliasing distortion in the picture.

[0032] Since FIR (Finite Impulse Response) filters can precisely control the frequency response and can achieve good low-pass characteristics by designing appropriate filter coefficients, FIR filters are often used as anti-aliasing filters.

[0033] As Figure 1 shown, the anti-aliasing downsampling module in the prior art mainly includes an anti-aliasing filter and I a downsampling decimator. The output end of the anti-aliasing filter is connected to the I input end of the downsampling decimator, I and the downsampling decimator is used to output the downsampled result. Assume that the anti-aliasing filter uses an Figure 2 -order FIR filter as M shown. The unit impulse response of this FIR filter is represented by , the input of the FIR filter is , and the output is .

[0034] Among them, M the unit impulse response of the -order FIR filter is expressed as: It has the condition of generalized linear phase characteristics, that is: , or .

[0035] The output of the FIR filter is: (2) In formula (2), h ( k ) represents the k -th coefficient of the FIR filter, x ( n − k ) represents the signal of the input signal x ( n ) delayed by k clock cycles.

[0036] I The downsampling decimator outputs 1 valid result I every clock cycles: (3) In formula (3), x ( rI − k ) represents the input signalx ( n )At discrete times rI − k whose value rI represents the current discrete time r represents the index of the decimated data

[0037] From Figure 2 and the expression of the output of the FIR filter it can be seen that in the existing anti-aliasing decimation module based on two discrete modules of the transposed FIR filter and the decimator, when using the FIR filter to remove high-frequency components, for each sample of the input signal, multiplication and addition operations are required, and M +1 multipliers and M adders are needed. When the order M of the filter is I relatively high, or the reduction multiple of the sampling rate is

[0038] relatively large, a large number of operations will be generated. In these operations, there is actually a certain degree of redundancy. For example, for some adjacent samples, their multiplication operations in the filtering process may have some identical coefficients. However, due to the traditional implementation method not being able to effectively optimize these redundant operations, each sample needs to perform a complete multiplication operation during the operation, which undoubtedly increases the number of multipliers used, and correspondingly, also increases the number of adders.

[0039] Decompose and transform Equation (3). Assume that M +1 is an integer multiple of I (if it is not an integer multiple, this condition can be met by padding zeros to the filter coefficients), that is, M +1 = KI , then the calculation of z ( r ) is divided into K steps, and each step performs I input data calculations. After each step is completed, the next step of data calculation will be transferred to.

[0040] Specifically, Equation (3) can be decomposed and transformed into:

[0041] Based on the above decomposition and transformation process, the number of multipliers can be reduced from M +1 to units, and the number of adders can be reduced from M units to units.

[0042] Based on the above theoretical analysis, the multiplication and addition operations can be evenly distributed within I clock cycles. By multiplexing the multipliers and adders I times, only multipliers and adders are required to implement the addition operation of M +1 multiplication results.

[0043] According to the above theoretical analysis results, the anti-aliasing downsampling circuit provided in the embodiments of the present application can be designed. The anti-aliasing downsampling circuit provided in the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0044] Figure 3 FIG. is a schematic structural diagram of an anti-aliasing downsampling circuit provided in an embodiment of the present application. As Figure 3 shown, the anti-aliasing downsampling circuit includes: a first multiplication accumulation module 10, at least one second multiplication accumulation module 20, a third multiplication accumulation module 30, a modulo I counter 40, and a latch register 50.

[0045] Among them, the first input terminals of the first multiplication accumulation module 10, the second multiplication accumulation module 20, and the third multiplication accumulation module 30 are connected together. The second input terminal of the first multiplication accumulation module 10 inputs data 0. The output terminal of the first multiplication accumulation module 10 is connected to the second input terminal of the second multiplication accumulation module 20. The output terminal of the second multiplication accumulation module 20 is connected to the second input terminal of the third multiplication accumulation module 30. The output terminal of the third multiplication accumulation module 30 is connected to the latch register 50.

[0046] The modulo I counter 40 is connected to the control input terminals of the first multiplication accumulation module 10, the second multiplication accumulation module 20, the third multiplication accumulation module 30, and the latch register 50. The modulo IThe value of the counting variable of the counter 40 increases with the change of the clock cycle. Under the control of the value of the counting variable, the first multiply-accumulate module 10 selects the corresponding filter coefficient and either 0 or the accumulate result of the first multiply-accumulate module 10, the second multiply-accumulate module 20 selects the corresponding filter coefficient and either the output result of the first multiply-accumulate module 10 or the accumulate result of the second multiply-accumulate module 20, and the third multiply-accumulate module 30 selects the corresponding filter coefficient and either the output result of the second multiply-accumulate module 20 or the accumulate result of the third multiply-accumulate module 30 to perform multiplication and accumulation operations.

[0047] According to the value of the counting variable, the latch register 50 outputs I the decimated result.

[0048] The number of the second multiply-accumulate modules 20 is determined according to the filter order and the I mod value of the counter 40 I determined.

[0049] It should be noted that the digital signal data to be processed can be input into the first multiply-accumulate module 10, the second multiply-accumulate module 20, and the third multiply-accumulate module 30 through the first input terminal of the first multiply-accumulate module 10, the first input terminal of the second multiply-accumulate module 20, and the first input terminal of the third multiply-accumulate module 30 to perform parallel multiplication and accumulation operations.

[0050] According to the I value of the counting variable of the modulo counter 40, the filter coefficients in the coefficient table corresponding to each preset multiply-accumulate module are selected, and the input digital signal data is multiplied by the filter coefficients in its corresponding coefficient table. Among them, the coefficient table can be a set of pre-set values, and these values are determined according to specific operation requirements. The multiplication operation is to multiply the input digital signal data by the corresponding filter coefficient in the coefficient table. For example, in digital signal processing, in order to filter or transform a signal, it is necessary to multiply the input signal data by the filter coefficient (stored in the coefficient table) to achieve a specific signal processing function. The result obtained from the multiplication operation is then subjected to an accumulation operation.

[0051] In the embodiment of the present application, according to the filter order M and the I mod value of the counter 40 I , the second multiply-accumulate module 20 is set to be pieces.

[0052] For example, when the filter order is 14 and the I mod value of the counter 40 IWhen it is 3 (that is, the anti-aliasing downsampling circuit can achieve 3-fold downsampling output), a first multiply-accumulate module 10, three second multiply-accumulate modules 20, and a third multiply-accumulate module 30 can be set.

[0053] In the embodiment of the present application, the first input ends of the second multiply-accumulate modules 20 are connected together, the second input ends are connected to the output end of the adjacent first multiply-accumulate module 10 or the output end of the adjacent previous second multiply-accumulate module 20, and the output ends of the second multiply-accumulate modules 20 are connected to the second input end of the adjacent subsequent second multiply-accumulate module 20 or the input end of the adjacent third multiply-accumulate module 30.

[0054] For example, when there is one first multiply-accumulate module 10, three second multiply-accumulate modules 20, and one third multiply-accumulate module 30, and the three second multiply-accumulate modules 20 are respectively represented by S 21 module, S 22 module, and S 23 module, when represented, the first input ends of the S 21 module, S 22 module, and S 23 module are all connected together with the first input ends of the first multiply-accumulate module 10 and the third multiply-accumulate module 30. The second input end of the S 21 module is connected to the output end of the first multiply-accumulate module 10. The second input end of the S 22 module is connected to the output end of the S 21 module. The second input end of the S 23 module is connected to the output end of the S 22 module. The second input end of the third multiply-accumulate module 30 is connected to the output end of the S 23 module.

[0055] In the embodiment of the present application, the first multiply-accumulate module 10 includes a first multiplier 101, a first adder 102, a first multiplexer (MUX) 103, and a first accumulation register 104. The filter coefficient and input data corresponding to the first multiply-accumulate module 10 are input into the first multiplier 101 for multiplication operation; The first multiplexer 103 selects and outputs 0 or the output result of the first accumulation register 104 under the control of the value of the counting variable of the modulo I counter 40. The first adder 102 adds the output result of the first multiplier 101 and the result selected and output by the first multiplexer 103; The first accumulation register 104 stores the output result of the first adder 102, uses the stored result as the input of the second multiply-accumulate module 20, and inputs the stored result into the first adder 102 through the first multiplexer 103.

[0056] Specifically, the first multiplier 101 receives the filter coefficient and input data corresponding to the first multiply-accumulate module 10 as inputs, and performs a multiplication operation on these two data. Among them, the filter coefficient can be a preset fixed value for filtering the input data. The input data is a real-time input signal to be processed. The first multiplexer 103 has two inputs, one is a fixed value 0, and the other is the output result of the first accumulation register 104; its output is controlled by the value of the count variable of the modulo I counter 40. When the count variable meets the preset condition, 0 is selected as the output; when the preset condition is not met, the output result of the first accumulation register 104 is selected as the output. For example, when the value of the count variable is 0, the first multiplexer 103 selects 0 as the output; when the value of the count variable is not 0, the first multiplexer 103 selects the output result of the first accumulation register 104 as the output.

[0057] The first adder 102 performs an addition operation on the output result of the first multiplier 101 and the result selected by the first multiplexer 103. If the first multiplexer 103 outputs 0, the output of the first adder 102 is equal to the output of the first multiplier 101; if the first multiplexer 103 outputs the output result of the first accumulation register 104, the output of the first adder 102 is the sum of the multiplication result output by the first multiplier 101 and the output result of the first accumulation register 104.

[0058] The first accumulation register 104 is used to store the output result of the first adder 102. In each clock cycle, the output result of the first adder 102 is written into the first accumulation register 104 to replace the previously stored result. At the same time, the first accumulation register 104 uses the stored result as the input of the second multiply-accumulate module 20 and feeds it back to the first adder 102 through the first multiplexer 103 for the next accumulation operation.

[0059] In the embodiment of the present application, the second multiply-accumulate module 20 includes a second multiplier 201, a second adder 202, a second multiplexer 203, and a second accumulation register 204. The filter coefficient and input data corresponding to the second multiply-accumulate module 20 are input into the second multiplier 201 for multiplication operation; The second multiplexer 203 is in the modulo IUnder the control of the value of the count variable of the counter 40, the output result of the first accumulator register 104 or the output result of the second accumulator register 204 is selectively output, and the second adder 202 performs an addition operation on the output result of the second multiplier 201 and the result selectively output by the second multiplexer 203; The second accumulator register 204 stores the output result of the second adder 202, and uses the stored result as the input of the third multiply-accumulate module 30, and inputs the stored result into the second adder 202 through the second multiplexer 203.

[0060] Specifically, the second multiplier 201 receives the filter coefficient and the input data corresponding to the second multiply-accumulate module 20 as inputs, and performs a multiplication operation on these two data. Among them, the filter coefficient can be a preset fixed value for filtering the input data. The input data is the signal to be processed input in real time. The second multiplexer 203 has two inputs, one is the output result of the first accumulator register 104, and the other is the output result of the second accumulator register 204; its output is modulo I controlled by the value of the count variable of the counter 40. When the count variable meets the preset condition, the output result of the first accumulator register 104 is selectively output; when the preset condition is not met, the output result of the second accumulator register 204 is selectively output. For example, when the value of the count variable is 0, the second multiplexer 203 selects the output result of the first accumulator register 104; when the value of the count variable is not 0, the second multiplexer 203 selects the output result of the second accumulator register 204.

[0061] The second adder 202 performs an addition operation on the output result of the second multiplier 201 and the result selectively output by the second multiplexer 203. If the second multiplexer 203 outputs the output result of the first accumulator register 104, the output of the second adder 202 is equal to the sum of the output result of the first accumulator register 104 and the multiplication result output by the second multiplier 201; if the second multiplexer 203 outputs the output result of the second accumulator register 204, the output of the second adder 202 is the sum of the multiplication result output by the second multiplier 201 and the output result of the second accumulator register 204.

[0062] The second accumulator register 204 is used to store the output result of the second adder 202. In each clock cycle, the output result of the second adder 202 is written into the second accumulator register 204 to replace the previously stored result. At the same time, the second accumulator register 204 uses the stored result as the input of the third multiply-accumulate module 30, and feeds it back to the second adder 202 through the second multiplexer 203 for the next accumulation operation.

[0063] In the embodiment of the present application, the third multiply-accumulate module 30 includes a third multiplier 301, a third adder 302, a third multiplexer 303, and a third accumulation register 304. The filter coefficients and input data corresponding to the third multiply-accumulate module 30 are input to the third multiplier 301 for multiplication operation; The third multiplexer 303 selects and outputs the output result of the second accumulation register 204 or the output result of the third accumulation register 304 under the control of the value of the count variable of the modulo I counter 40. The third adder 302 adds the output result of the third multiplier 301 and the result selected and output by the third multiplexer 303; The third accumulation register 304 stores the output result of the third adder 302, inputs the stored result into the latch register 50 for latching, and inputs the stored result into the third adder 302 through the third multiplexer 303.

[0064] Specifically, the third multiplier 301 receives the filter coefficients and input data corresponding to the third multiply-accumulate module 30 as inputs and multiplies these two data. Among them, the filter coefficients can be preset fixed values for filtering the input data. The input data is a real-time input signal to be processed. The third multiplexer 303 has two inputs, one is the output result of the second accumulation register 204, and the other is the output result of the third accumulation register 304; its output is controlled by the value of the count variable of the modulo I counter 40. When the count variable meets the preset condition, it selects and outputs the output result of the second accumulation register 204; when it does not meet the preset condition, it selects and outputs the output result of the third accumulation register 304. For example, when the value of the count variable is 0, the third multiplexer 303 selects and outputs the output result of the second accumulation register 204; when the value of the count variable is not 0, the third multiplexer 303 selects and outputs the output result of the third accumulation register 304.

[0065] The third adder 302 adds the output result of the third multiplier 301 and the result selected and output by the third multiplexer 303. If the third multiplexer 303 outputs the output result of the first accumulation register 104, the output of the third adder 302 is equal to the sum of the output result of the second accumulation register 204 and the multiplication result output by the third multiplier 301; if the third multiplexer 303 outputs the output result of the third accumulation register 304, the output of the third adder 302 is the sum of the multiplication result output by the third multiplier 301 and the output result of the third accumulation register 304.

[0066] The third accumulative register 304 is used to store the output result of the third adder 302. In each clock cycle, the output result of the third adder 302 is written into the third accumulative register 304, replacing the previously stored result. At the same time, the third accumulative register 304 uses the stored result as the input of the third multiply-accumulate module 30, and feeds it back to the third adder 302 through the third multiplexer 303 for the next accumulation operation.

[0067] In the embodiment of the present application, according to the filter order M and the modulus I of the modulus counter 40 I , M +1 filter coefficients are written into coefficient tables, and each coefficient table contains I filter coefficients. The filter coefficients in each coefficient table can be selected according to the value of the counting variable of the modulus I counter 40.

[0068] It should be noted that when M +1 is not I an integer multiple of , some filter coefficients in the

[0069] th coefficient table are filled with 0. M For example, when I is 14 and M is 3, there are 15 filter coefficients. These 15 filter coefficients can be written into 5 coefficient tables, and each coefficient table contains 3 filter coefficients, and each coefficient table corresponds to a multiply-accumulate module. When I is 13 and

[0070] is 3, there are 14 filter coefficients. These 14 filter coefficients can be written into 5 coefficient tables. The first to the fourth coefficient tables each contain 3 filter coefficients, the fifth coefficient table contains 2 filter coefficients, and the other filter coefficient in the fifth coefficient table can be filled with 0. I In the embodiment of the present application, the value range of the counting variable is 0 to I -1, that is, the value of the counting variable can be 0, 1, 2, 3, ……, I -1. When

[0071] is 3, the value of the counting variable can be 0, 1, 2. Each value of the counting variable corresponds to the corresponding filter coefficient. The first multiplexer 103 selects the output 0. The first adder 102 performs an addition operation on 0 and the output result of the first multiplier 101, and the output result of the first adder 102 is stored in the first accumulative register 104. The second multiplexer 203 selects the output result of the first accumulative register 104. The second adder 202 performs an addition operation on the output result of the first accumulative register 104 and the output result of the second multiplier 201, and the output result of the second adder 202 is stored in the second accumulative register 204. The third multiplexer 303 selects the output result of the second accumulative register 204. The third adder 302 performs an addition operation on the output result of the second accumulative register 204 and the output result of the third multiplier 301, and the output result of the third adder 302 is stored in the third accumulative register 304. The output result of the third accumulative register 304 is input into the latch register 50 for latching.

[0072] In the above embodiment, when the value of the count variable is from 1 to I -1: The first multiplexer 103 selects the output result of the first accumulative register 104 in the previous clock cycle. The first adder 102 performs an addition operation on the output result of the first accumulative register 104 in the previous clock cycle and the output result of the first multiplier 101, and the output result of the first adder 102 is stored in the first accumulative register 104. The second multiplexer 203 selects the output result of the second accumulative register 204 in the previous clock cycle. The second adder 202 performs an addition operation on the output result of the second accumulative register 204 in the previous clock cycle and the output result of the second multiplier 201, and the output result of the second adder 202 is stored in the second accumulative register 204. The third multiplexer 303 selects the output result of the third accumulative register 304 in the previous clock cycle. The third adder 302 performs an addition operation on the output result of the third accumulative register 304 in the previous clock cycle and the output result of the third multiplier 301, and the output result of the third adder 302 is stored in the third accumulative register 304. The output result of the third accumulative register 304 is input into the latch register 50 for latching.

[0073] In the above embodiment, when the value of the count variable is I -1, the result stored in the third accumulative register 304 (i.e., the output result of the third accumulative register 304 in the previous clock cycle) is used as the I decimation result and is input into the latch register 50 for latching. Under the control of the value of the count variable of the modulo I counter 40, the latch register 50 outputs the I decimation result in the corresponding clock cycle. When the value of the count variable is from 0 to IWhen it is -2, the latched value of the latch register 50 remains unchanged, and the output also remains unchanged.

[0074] It can be understood that in the actual circuit, the calculation result of the I -1st clock cycle. At the rising edge of the clock when the value of the counting variable is 0, I the decimated-by- factor result is latched and output by the latch register 50.

[0075] When the next clock cycle arrives, the value of the counting variable changes from I -1 back to 0.

[0076] Assume that the anti-aliasing decimation circuit provided in the embodiment of the present application outputs n in the th clock cycle. One data is input in each clock cycle, and M +1 is I times an integer multiple, that is, M +1 = KI . Among them, there is a first multiply-accumulate module, K -2 second multiply-accumulate modules, and a third multiply-accumulate module. The output results of the anti-aliasing decimation circuit in each clock cycle are described below.

[0077] The th clock cycle to the th clock cycle calculates , and it is calculated and completed in I clock cycles: (4) According to the data input order, I clock cycles are used to calculate multiplications of I and accumulate them together: In the 0th clock cycle, the product is calculated. The first multiplexer 103 selects and outputs 0, and the addition calculation result of the first adder 102 is stored in the accumulation register . Equivalently, in the first calculation, the product is directly stored in the accumulation register : , ; In the 1st clock cycle, the product is calculated. The first multiplexer 103 selects and outputs the value of the accumulation register , and the addition calculation result of the first adder 102 is stored in the accumulation register : , ; …… The I -1st clock cycle calculates the product , the first multiplexer 103 selects and outputs the value of the accumulation register , and the addition calculation result of the first adder 102 is stored in the accumulation register to obtain : , ; The th clock cycle to the th clock cycle calculates , and it is calculated and completed in I clock cycles: (5) In the order of data input, I clock cycles respectively calculate multiplications of I , and accumulate them to the accumulation register : The 0th clock cycle calculates the product , the second multiplexer 203 selects and outputs the value of the accumulation register , and at this time, the output result of the accumulation register is the result of I completed multiplications and accumulations , and the addition calculation result of the second adder 202 is stored in the accumulation register : , ; The 1st clock cycle calculates the product , the second multiplexer 203 selects and outputs the value of the accumulation register , and the addition calculation result of the second adder 202 is stored in the accumulation register : , ; …… The I -1st clock cycle calculates the product , the second multiplexer 203 selects and outputs the value of the accumulation register , and the addition calculation result of the second adder 202 is stored in the accumulation register to obtain : , ; …… The th to the n th clock cycle is used to calculate , and it takes I clock cycles to complete the calculation and output the final result : (6) According to the data input order, I clock cycles are used to calculate multiplications respectively and accumulate the results to the accumulation register I : : The product is calculated in the 0th clock cycle , and the K -1th multiplexer selects and outputs the value of the accumulation register . At this time, the value of the accumulation register is the result of I multiplications and accumulations that have been completed . The addition calculation result is stored in the accumulation register : , ; The product is calculated in the 1st clock cycle , and the K -1th multiplexer selects and outputs the value of the accumulation register . The addition calculation result is stored in the accumulation register : , ; …… The I -1th clock cycle is used to calculate the product , and the K th multiplexer selects and outputs the value of the accumulation register . The addition calculation result is stored in the accumulation register , and the result is obtained: , .

[0078] Every IThe input data is calculated and transferred to the next multiply-accumulate module for further operation. Each multiply-accumulate module includes an independent multiplier, adder, accumulation register, and coefficient table. After steps of operation, the final result is obtained and 1 decimated result is output.

[0079] It should be noted that Figure 3 is a structure similar to a pipeline. During the above Figure 3 -based calculation process, the outputs before and after are also being calculated. For example, during the calculation of the , the is also being calculated and stored in the accumulation register .

[0080] Taking the filter order of 14 and the need to implement 3-fold decimation output as an example (i.e., M is 14, I is 3), the structure and working principle of the anti-aliasing decimation circuit provided by the embodiments of the present application will be described.

[0081] Set 1 first multiply-accumulate module, 3 second multiply-accumulate modules, and 1 third multiply-accumulate module. Write 15 filter coefficients into 5 coefficient tables, with 3 filter coefficients in each coefficient table.

[0082] Modulo I counter 40 uses a modulo-3 counter, and the values of its counting variable are 0, 1, and 2. When the value of the counting variable is 0, the filter coefficients in the corresponding coefficient tables are respectively h (14), h (11), h (8), h (5), and h (2). When the value of the counting variable is 1, the filter coefficients in the corresponding coefficient tables are respectively h (13), h (10), h (7), h (4), and h (1). When the value of the counting variable is 2, the filter coefficients in the corresponding coefficient tables are respectively h (12), h (9), h (6), h (3), and h (0). The corresponding filter coefficients in different coefficient tables can be selected according to the value of the counting variable.

[0083] Assume the output is at the 15th clock cycle , then The operation content in each clock cycle is decomposed as follows: Calculate from the 1st clock cycle to the 3rd clock cycle , and it is calculated and completed in 3 clock cycles: .

[0084] According to the data input order, calculate the 3 multiplications in 3 clock cycles respectively and accumulate them together: Calculate the product in the 0th clock cycle , the first multiplexer 103 selects and outputs 0, and the addition calculation result of the first adder 102 is stored in the accumulator register , equivalently, in the 1st calculation, the product is directly stored in the accumulator register : , ; Calculate the product in the 1st clock cycle , the first multiplexer 103 selects and outputs the value of the accumulator register , and the addition calculation result of the first adder 102 is stored in the accumulator register : , ; Calculate the product in the 2nd clock cycle , the first multiplexer 103 selects and outputs the value of the accumulator register , and the addition calculation result of the first adder 102 is stored in the accumulator register , obtaining : , .

[0085] Calculate from the 4th clock cycle to the 6th clock cycle , and it is calculated and completed in 3 clock cycles: .

[0086] According to the data input order, calculate the 3 multiplications of in 3 clock cycles respectively, and accumulate them to the accumulator register : Calculate the product in the 0th clock cycle , the second multiplexer 203 selects and outputs the value of the accumulation register . At this time, the output result of the accumulation register is the result of having completed 3 multiplications and accumulations. , and the addition calculation result of the second adder 202 is stored in the accumulation register : , ; In the 1st clock cycle, the product is calculated. , the second multiplexer 203 selects and outputs the value of the accumulation register . The addition calculation result of the second adder 202 is stored in the accumulation register : , ; In the 2nd clock cycle, the product is calculated. , the second multiplexer 203 selects and outputs the value of the accumulation register . The addition calculation result of the second adder 202 is stored in the accumulation register , and the result is : , .

[0087] From the 7th clock cycle to the 9th clock cycle, the calculation is , and it is calculated and completed in 3 clock cycles: .

[0088] According to the data input order, 3 multiplications of are calculated respectively in 3 clock cycles and accumulated into the accumulation register : In the 0th clock cycle, the product is calculated . The 3rd multiplexer selects and outputs the value of the accumulation register . At this time, the value of the accumulation register is the result of having completed 3 multiplications and accumulations. . The addition calculation result is stored in the accumulation register : , ; In the 1st clock cycle, the product is calculated . The 3rd multiplexer selects and outputs the value of the accumulation register . The addition calculation result is stored in the accumulation register In: , ; Calculate the product in the 2nd clock cycle , the 3rd multiplexer selects the output accumulator register value, and the addition result is stored in the accumulator register , obtaining : , .

[0089] Calculate from the 10th clock cycle to the 12th clock cycle , and complete the calculation in 3 clock cycles: .

[0090] According to the data input order, calculate the 3 multiplications in 3 clock cycles respectively and accumulate them into the accumulator register : Calculate the product in the 0th clock cycle , the 4th multiplexer selects the output accumulator register value, and at this time the value of the accumulator register is the result of 3 multiplications and accumulations that have been completed , and the addition result is stored in the accumulator register in: , ; Calculate the product in the 1st clock cycle , the 4th multiplexer selects the output accumulator register value, and the addition result is stored in the accumulator register in: , ; Calculate the product in the 2nd clock cycle , the 4th multiplexer selects the output accumulator register value, and the addition result is stored in the accumulator register , obtaining : , .

[0091] Calculate from the 13th clock cycle to the 15th clock cycle , it is calculated and completed in 3 clock cycles, and the final result is output : .

[0092] Calculate separately in 3 clock cycles according to the data input order for 3 multiplications, and accumulate them to the accumulation register : Calculate the product in the 0th clock cycle , the 5th multiplexer selects and outputs the value of the accumulation register , at this time the value of the accumulation register is the result of 3 multiplications and accumulations that have been completed , the addition calculation result is stored in the accumulation register : , ; Calculate the product in the 1st clock cycle , the 5th multiplexer selects and outputs the value of the accumulation register , the addition calculation result is stored in the accumulation register : , ; Calculate the product in the 2nd clock cycle , the 5th multiplexer selects and outputs the value of the accumulation register , the addition calculation result is stored in the accumulation register , and get : , .

[0093] Assume that 15 filter coefficients are shown in Table 1, then the coefficients in the 5 coefficient tables are shown in Table 2

[0094] Table 1 Filter Coefficients

[0095] Table 2 Coefficient Table

[0096] When the input , the output by the theoretical anti-aliasing filter and the As shown in Table 3. Compared with the anti-aliasing downsampling module of the prior art, there is an additional latch register 50 at the output end of the anti-aliasing downsampling circuit provided in the embodiments of the present application. Therefore the output is later than one clock cycle.

[0097] Table 3 Output Table of Anti-aliasing Downsampling Circuit

[0098] The embodiments of the present application also provide a circuit module, including the above anti-aliasing downsampling circuit. The circuit module integrates the anti-aliasing downsampling circuit provided in the embodiments of the present application, and on this basis, function expansion and optimization can be carried out, aiming to provide an efficient and reliable signal preprocessing solution for various digital signal processing scenarios. The circuit module has excellent anti-aliasing performance and flexible downsampling ability, and at the same time integrates other practical functions, which can meet the diverse needs of different applications for signal processing.

[0099] For example, in the field of audio processing, in audio recording, playback and editing devices, the circuit module provided in the embodiments of the present application can be used to perform downsampling processing on high-sampling-rate audio signals, and at the same time effectively suppress environmental noise and noise generated by the device itself, ensuring high-quality output of audio signals. Specifically, in a portable audio player, by using this circuit module to downsample a high-sampling-rate audio file to a sampling rate suitable for device processing and optimizing the quality of the audio signal, the user's auditory experience can be improved.

[0100] In wireless communication and wired communication systems, the circuit module provided in the embodiments of the present application can be used to preprocess received signals. Through functions such as anti-aliasing downsampling and noise suppression, the reliability and transmission efficiency of the signals are improved, and the bit error rate is reduced. At the same time, the signal format conversion function can achieve compatibility with different communication protocols and devices, meeting the diverse needs of communication systems.

[0101] In industrial automation and sensor signal processing, the circuit module provided in the embodiments of the present application can perform operations such as anti-aliasing downsampling, gain adjustment and noise suppression on sensor signals, convert the original signals into a format suitable for industrial control system processing, and provide reliable data support for the monitoring and control of the production process.

[0102] In medical devices such as electrocardiographs and electroencephalographs, the circuit module provided in the embodiments of the present application can effectively remove noise interference in physiological signals, perform downsampling processing on the signals to reduce the data volume, and at the same time ensure the integrity and accuracy of the signals, providing a reliable basis for medical diagnosis.

[0103] The embodiment of the present application also provides a chip, including the above anti-aliasing downsampling circuit, which is used to reduce the sampling rate of a signal while avoiding aliasing distortion, thereby reducing the amount of data. The anti-aliasing downsampling circuit can remove redundant calculations and has characteristics such as a small circuit scale and low power consumption.

[0104] The chip provided by the embodiment of the present application can be used in consumer electronic products such as smart phones, tablet computers, and smart speakers for audio and video signal processing. For example, during the audio recording and playback of a smart phone, the chip can perform anti-aliasing downsampling processing on the audio signal collected by the microphone, while optimizing the audio quality to provide a clear and realistic sound quality experience. In terms of video shooting and playback, the chip can efficiently process the video signal output by the camera to achieve video downsampling and format conversion to meet different storage and transmission requirements.

[0105] On an industrial automation production line, the chip can be used to process signals collected by various sensors, such as temperature sensors, pressure sensors, and acceleration sensors. By performing anti-aliasing downsampling and optimization processing on the sensor signals, various parameter information in the production process can be accurately obtained, providing reliable data support for the industrial control system. In the field of the Internet of Things, the chip can be applied to various intelligent devices and sensor nodes to achieve efficient processing and transmission of massive data, improving the performance and reliability of the Internet of Things system.

[0106] In medical devices such as electrocardiographs, electroencephalographs, and ultrasonic diagnostic instruments, the chip can effectively remove noise interference in biomedical signals and perform precise anti-aliasing downsampling processing on the signals to ensure that doctors can obtain accurate diagnostic information. At the same time, the multi-channel processing ability of the chip can achieve synchronous processing of multiple biomedical signals, improving the working efficiency of medical devices.

[0107] In a communication system, the chip can be used for the processing of wireless signals and wired signals. For example, in base station equipment, the chip can perform anti-aliasing downsampling processing on the received radio frequency signal to improve the signal quality and transmission efficiency. In network equipment, the chip can process data signals to achieve data downsampling and format conversion to meet different network transmission protocols and bandwidth requirements.

[0108] The embodiment of the present application also provides a signal processing device, including the above circuit module or chip. The signal processing device can be used in smart home systems, intelligent transportation systems, aerospace systems, and financial transaction systems to provide reliable solutions for various complex signal processing tasks.

[0109] Those skilled in the art can understand that, on the premise of no conflict, the above-mentioned preferred solutions can be freely combined and superimposed. Among them, the flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of the systems according to various embodiments disclosed in the present application. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and this module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order from that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions. The numbering of the steps in this article is only for convenience of explanation and reference, and is not used to limit the sequence before and after. The specific execution sequence is determined by the technology itself, and those skilled in the art can determine various permitted and reasonable sequences according to the technology itself.

[0110] Those skilled in the art can understand that, on the premise of no conflict, the above-mentioned preferred solutions can be freely combined and superimposed.

[0111] It should be understood that the above-mentioned embodiments are merely exemplary and not restrictive. Without departing from the basic principles of the present application, various obvious or equivalent modifications or substitutions that those skilled in the art can make to the above details will be included within the scope of the claims of the present application.

Claims

1. An anti-aliasing downsampling circuit, characterized in that: include: A first multiplication-accumulation module, at least one second multiplication-accumulation module, a third multiplication-accumulation module, a module I counter and latch registers; The first input end of the first multiplication-accumulation module, the first input end of the second multiplication-accumulation module and the first input end of the third multiplication-accumulation module are connected together, the second input end of the first multiplication-accumulation module inputs data 0, the output end of the first multiplication-accumulation module is connected to the second input end of the second multiplication-accumulation module, the output end of the second multiplication-accumulation module is connected to the second input end of the third multiplication-accumulation module, and the output end of the third multiplication-accumulation module is connected to the latch register; The model I The counter is connected to the control input end of the first multiplication accumulation module, the second multiplication accumulation module, the third multiplication accumulation module and the latch register, and the module I The value of the count variable of the counter increases with the change of the clock cycle. Under the control of the value of the count variable, the first multiplication and accumulation module selects the corresponding filter coefficient and 0 or the accumulation result of the first multiplication and accumulation module, the second multiplication and accumulation module selects the corresponding filter coefficient and the output result of the first multiplication and accumulation module or the accumulation result of the second multiplication and accumulation module, and the third multiplication and accumulation module selects the corresponding filter coefficient and the output result of the second multiplication and accumulation module or the accumulation result of the third multiplication and accumulation module to perform multiplication and accumulation operations; According to the value of the count variable, the latch register outputs I Downsampling results; The number of the second multiplication-accumulation modules is determined according to the filter order and the module I Modulus value of the counter I Sure.

2. The anti-aliasing downsampling circuit according to claim 1, characterized in that: According to the filter order M and model I Modulus value of the counter I , set the second multiplication-accumulation module to indivual.

3. The anti-aliasing downsampling circuit according to claim 2, characterized in that: The first input ends of each of the second multiplication-accumulation modules are connected together, the second input ends are connected to the output end of the adjacent first multiplication-accumulation module or the output end of the adjacent previous second multiplication-accumulation module, and the output end of each of the second multiplication-accumulation modules is connected to the second input end of the adjacent next second multiplication-accumulation module or the input end of the adjacent third multiplication-accumulation module.

4. The anti-aliasing downsampling circuit according to claim 1, characterized in that: The first multiplication-accumulation module comprises a first multiplier, a first adder, a first multiplexer and a first accumulation register, and the filter coefficient and input data corresponding to the first multiplication-accumulation module are input into the first multiplier for multiplication operation; The first multiplexer is in the mode I Under the numerical control of the counting variable of the counter, the output is selected to be 0 or the output result of the first accumulator register, and the first adder performs an addition operation on the output result of the first multiplier and the result selected to be output by the first multiplexer; The first accumulation register stores the output result of the first adder, and uses the stored result as the input of the second multiplication-accumulation module, and inputs the stored result into the first adder through the first multiplexer.

5. The anti-aliasing downsampling circuit according to claim 4, characterized in that: The second multiplication-accumulation module comprises a second multiplier, a second adder, a second multiplexer and a second accumulation register, and the filter coefficient and input data corresponding to the second multiplication-accumulation module are input into the second multiplier for multiplication operation; The second multiplexer is in the module I Under the numerical control of the counting variable of the counter, the output result of the first accumulator register or the output result of the second accumulator register is selected to be output, and the second adder performs an addition operation on the output result of the second multiplier and the result selected and outputted by the second multiplexer; The second accumulation register stores the output result of the second adder, and uses the stored result as the input of the third multiplication-accumulation module, and inputs the stored result into the second adder through the second multiplexer.

6. The anti-aliasing downsampling circuit according to claim 5, characterized in that: The third multiplication-accumulation module comprises a third multiplier, a third adder, a third multiplexer and a third accumulation register, and the filter coefficient and input data corresponding to the third multiplication-accumulation module are input into the third multiplier for multiplication operation; The third multiplexer is in the mode I Under the numerical control of the counting variable of the counter, the output result of the second accumulator register or the output result of the third accumulator register is selected and outputted, and the third adder performs an addition operation on the output result of the third multiplier and the result selected and outputted by the third multiplexer; The third accumulator register stores the output result of the third adder, inputs the stored result into the latch register for latching, and inputs the stored result into the third adder through the third multiplexer.

7. The anti-aliasing downsampling circuit according to claim 6, characterized in that: According to the filter order M and model I Modulus value of the counter I ,Will M +1 filter coefficient written coefficient tables, each with I filter coefficients.

8. The anti-aliasing downsampling circuit according to claim 7, characterized in that: when M +1 Not I When the value is an integer multiple of Some filter coefficients in the coefficient table are padded with 0.

9. The anti-aliasing downsampling circuit according to claim 7, characterized in that: The value of the counting variable ranges from 0 to I -1.

10. The anti-aliasing downsampling circuit according to claim 9, characterized in that: When the value of the counting variable is 0: The first multiplexer selects to output 0, the first adder performs an addition operation on 0 and an output result of the first multiplier, and the output result of the first adder is stored in the first accumulator register; The second multiplexer selects and outputs the output result of the first accumulator register, the second adder performs an addition operation on the output result of the first accumulator register and the output result of the second multiplier, and the output result of the second adder is stored in the second accumulator register; The third multiplexer selects and outputs the output result of the second accumulator register, the third adder adds the output result of the second accumulator register and the output result of the third multiplier, the output result of the third adder is stored in the third accumulator register, and the output result of the third accumulator register is input into the latch register for latching.

11. The anti-aliasing downsampling circuit according to claim 9, characterized in that: The value of the counting variable is 1~ I -1 hour: The first multiplexer selects and outputs an output result of the first accumulator register in the previous clock cycle, the first adder performs an addition operation on the output result of the first accumulator register in the previous clock cycle and the output result of the first multiplier, and the output result of the first adder is stored in the first accumulator register; The second multiplexer selects and outputs the output result of the second accumulator register in the previous clock cycle, the second adder performs an addition operation on the output result of the second accumulator register in the previous clock cycle and the output result of the second multiplier, and the output result of the second adder is stored in the second accumulator register; The third multiplexer selects and outputs the output result of the third accumulator register in the previous clock cycle, the third adder adds the output result of the third accumulator register in the previous clock cycle and the output result of the third multiplier, the output result of the third adder is stored in the third accumulator register, and the output result of the third accumulator register is input into the latch register for latching.

12. The anti-aliasing downsampling circuit according to claim 11, characterized in that: The value of the count variable is I -1, the third accumulator register stores the result as I The down-sampling result is input into the latch register for latching.

13. A circuit module, characterized in that: It comprises the anti-aliasing downsampling circuit as described in any one of claims 1 to 12.

14. A chip, characterized in that: It comprises the anti-aliasing downsampling circuit as described in any one of claims 1 to 12.

15. A signal processing device, characterized in that: Includes the circuit module as claimed in claim 13 or the chip as claimed in claim 14.

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