Logic code quality inspection method and device, server and storage medium

Abstract

The invention provides a logic code quality inspection method and device, a server and a storage medium, and is applied to the technical field of computers. According to the method, after logic synthesis of an integrated circuit is completed, starting point registers and end point registers of all time sequence paths in the integrated circuit are extracted; counting the number of rear-stage fan-out registers and the number of front-stage fan-in registers of each register, obtaining a register number threshold value corresponding to the integrated circuit, and if the number of the front-stage fan-in registers or the number of the rear-stage fan-out registers corresponding to any register is larger than the register number threshold value, determining that the logic code of the integrated circuit is abnormal. Compared with the prior art in which the quality of the logic code is detected after layout and wiring are completed, the method provided by the invention can detect the quality of the code after logic synthesis is completed, can complete the quality detection of the logic code as early as possible, effectively avoids the situation that the logic code is found to be abnormal after all physical designs are completed, and improves the design efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular, to a method, apparatus, server, and storage medium for checking the quality of logic code. Background Art

[0002] In the existing integrated circuit design process, there is an obvious gap between logic design and physical design: the logic design stage mainly focuses on function implementation, while the timing convergence problem often needs to be exposed through static timing analysis until the physical design stage (such as after placement and routing).

[0003] With the continuous increase in the amount of logic code data, the lag in the design process has led to a significant extension of the design iteration cycle. That is, if a logic code quality problem is discovered late in the physical design, it may lead to readjustment of the logic code, which not only consumes a large amount of resources but also may introduce new design risks due to repeated modifications.

[0004] Therefore, how to detect the quality of logic code as early as possible and discover the quality problems of logic code has become one of the technical problems that need to be solved urgently by those skilled in the art. Summary of the Invention

[0005] In view of this, this application is committed to providing a method, apparatus, server, and storage medium for checking the quality of logic code to solve the problem in the prior art that it is difficult to check the quality of logic code as early as possible and the abnormal logic code leads to a long integrated circuit design cycle.

[0006] In a first aspect, this application provides a method for checking the quality of logic code, including: After completing the logic synthesis of the integrated circuit, extract the starting register and ending register of all timing paths in the integrated circuit; Count the number of fan-out registers in the subsequent stage and the number of fan-in registers in the previous stage of each register. The number of fan-out registers in the subsequent stage is the total number of the first registers connected to the subsequent stage of this register, and the number of fan-in registers in the previous stage is the total number of the first registers connected to the previous stage of this register; Obtain the register quantity threshold corresponding to the integrated circuit; If the number of fan-in registers in the previous stage or the number of fan-out registers in the subsequent stage corresponding to any register is greater than the register quantity threshold, determine that the logic code of the integrated circuit is abnormal.

[0007] In an optional implementation manner, extracting the starting register and ending register of all timing paths in the integrated circuit includes: Obtain the timing constraint file of the integrated circuit and the gate-level netlist obtained after completing the logic synthesis; Perform static timing analysis on the gate netlist based on the timing constraint file, and identify the starting register and the ending register corresponding to each timing path through static timing analysis.

[0008] In an alternative embodiment, obtaining the register quantity threshold corresponding to the integrated circuit includes: Obtain the design parameters of the integrated circuit, where the design parameters include the target clock frequency, the single-stage delay duration, and the target single-stage fan-out value; Determine the register quantity threshold corresponding to the integrated circuit according to the target clock frequency, the single-stage delay duration, and the target single-stage fan-out value.

[0009] In an alternative embodiment, determining the register quantity threshold corresponding to the integrated circuit according to the target clock frequency, the single-stage delay duration, and the target single-stage fan-out value includes: Determine the maximum allowable number of stages corresponding to the integrated circuit according to the target clock frequency and the single-stage delay duration; Determine the register quantity threshold corresponding to the integrated circuit according to the maximum allowable number of stages and the target single-stage fan-out value.

[0010] In an alternative embodiment, the process of obtaining the single-stage delay duration includes: Determine the delay duration of the logic cell with the shortest inherent time delay in the integrated circuit as the target cell delay; Segment and statistically analyze the wire delays of all metal wires in the integrated circuit at preset time intervals, and fit a normal distribution curve based on the statistical results; Determine the wire delay expectation value calculated based on the normal distribution curve as the target wire delay; Determine the sum of the target cell delay and the target wire delay as the single-stage delay duration.

[0011] In an alternative embodiment, the process of obtaining the target single-stage fan-out value includes: Complete the placement and routing of the integrated circuit according to different preset single-stage fan-out values to obtain corresponding initial design results; Perform static timing analysis on each of the initial design results to obtain corresponding timing violation results; Use the preset single-stage fan-out value corresponding to the best timing violation result among the preset single-stage fan-out values as the target single-stage fan-out value.

[0012] In an alternative embodiment, the method provided in the first aspect of the present application further includes: Registers with the number of prefix fan-in registers or the number of suffix fan-out registers greater than the register number threshold are regarded as target registers; Perform logical design optimization or physical design optimization on the target registers.

[0013] In an alternative embodiment, the process of performing logical design optimization on the target registers includes: Copy the target register to obtain N target registers, where N is greater than or equal to 2; Decouple the target timing path to which the target register belongs into N groups of optimized timing paths; Connect each group of the optimized timing paths to one of the target registers.

[0014] In an alternative embodiment, the process of performing logical design optimization on the target registers includes: Start from the target register and traverse step by step along the suffix timing path; If there is a branch point with logical bifurcation before traversing to the end register, insert a new register at the target branch point so that the new register connects part of the logical path, and the target branch point is the first branch point that appears along the timing path direction; If traversing to the end register and there is no branch point with logical bifurcation, delete or move part of the logical path of the target register.

[0015] In an alternative embodiment, the process of performing physical design optimization on the target registers includes: Obtain the physical design layout of the integrated circuit; Extract the path information of each timing path to which the target register belongs in the physical design layout; Based on the path information, determine the target timing paths to be optimized among the timing paths to which the target register belongs; Perform optimization design on the target timing paths.

[0016] In an alternative embodiment, the path information includes the position coordinates of the start register and the end register of the timing path in the physical design layout; Based on the path information, determining the target timing paths to be optimized among the timing paths to which the target register belongs includes: For each timing path to which the target register belongs, calculate the stack distance between the start register and the end register based on the position coordinates of the start register and the end register of the timing path; Regard the timing paths with stack distance greater than the preset stack distance threshold as the target timing paths to be optimized.

[0017] In an alternative embodiment, the path information includes the current number of stages corresponding to the timing path; Based on the path information, determining a target timing path to be optimized among the timing paths to which the target register belongs includes: Regarding the timing paths to which the target register belongs, taking the timing paths with the current number of stages greater than the maximum allowable number of stages as the target timing paths to be optimized, where the maximum allowable number of stages is determined based on the target clock frequency of the integrated circuit and the single-stage delay duration.

[0018] In an alternative embodiment, optimizing the design of the target timing path includes at least one of the following methods: Shortening the link length of the target timing path; Adjusting the metal layer to which the metal wires in the target timing path belong; During the clock tree synthesis stage, adjusting the clock path length of the starting register or the ending register of the target timing path.

[0019] In a second aspect, the present application provides a logic code quality inspection device, including: A first acquisition unit, configured to extract the starting register and the ending register of all timing paths in the integrated circuit after completing the logic synthesis of the integrated circuit; A statistics unit, configured to count the number of post-stage fan-out registers and the number of pre-stage fan-in registers of each register, where the number of post-stage fan-out registers is the total number of the first registers connected to the post-stage of this register, and the number of pre-stage fan-in registers is the total number of the first registers connected to the pre-stage of this register; A second acquisition unit, configured to obtain the register quantity threshold corresponding to the integrated circuit; A determination unit, configured to determine that the logic code of the integrated circuit is abnormal if the number of pre-stage fan-in registers or the number of post-stage fan-out registers corresponding to any register is greater than the register quantity threshold.

[0020] In a third aspect, the present application provides a server, including a memory, a processor, and a computer program stored on the memory and executed by the processor. When the processor executes the computer program, the steps of the logic code quality inspection method according to any item in the first aspect of the present application are implemented.

[0021] In a fourth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the logic code quality inspection method according to any item in the first aspect of the present application are implemented.

[0022] Based on the above, through the logic code quality inspection method provided by this application, after the logic synthesis of the integrated circuit is completed, the starting register and the ending register of all timing paths in the integrated circuit are extracted, the number of fan-out registers of the subsequent stage and the number of fan-in registers of the previous stage of each register are counted, and the register number threshold corresponding to the integrated circuit is obtained. If the number of fan-in registers of the previous stage or the number of fan-out registers of the subsequent stage corresponding to any register is greater than the register number threshold, it is determined that the logic code of the integrated circuit is abnormal. This method realizes the inspection of the logic code quality based on the number of fan-out registers of the subsequent stage and the number of fan-in registers of the previous stage corresponding to the register. The inspection process is simple and easy to implement. Moreover, the physical design of the integrated circuit can be divided into logic synthesis and placement and routing. Compared with the prior art where the logic code quality is detected after the placement and routing are completed, the method provided by this application can perform the code quality detection after the logic synthesis is completed. Therefore, the quality detection of the logic code can be completed as early as possible, effectively avoiding the discovery of logic code abnormalities only after all physical designs are completed, which helps to improve the design efficiency of the integrated circuit. Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0024] Figure 1 It is a flowchart of a method for inspecting the quality of integrated circuit logic code provided by this application.

[0025] Figure 2 It is a schematic diagram of the fan-out register of the subsequent stage and the fan-out register of the previous stage mentioned in this application.

[0026] Figure 3 It is a schematic diagram of the fan-out register of the subsequent stage mentioned in this application.

[0027] Figure 4 It is a schematic diagram of the fan-in register of the previous stage mentioned in this application.

[0028] Figure 5 It is a schematic diagram of the number of stages of the timing path between the starting register and the ending register.

[0029] Figure 6 It is a flowchart of a method for determining the register number threshold provided by this application.

[0030] Figure 7 It is a normal distribution curve graph of the wire delay of the metal wire in the integrated circuit.

[0031] Figure 8 It is a flowchart of another integrated circuit logic code quality inspection method provided by this application.

[0032] Figure 9 It is a flowchart of a register physical design optimization method provided by this application.

[0033] Figure 10 It is a schematic diagram of the physical layout of an integrated circuit.

[0034] Figure 11 It is a structural block diagram of an integrated circuit logic code quality inspection device provided by this application.

[0035] Figure 12 It is a structural block diagram of another integrated circuit logic code quality inspection device provided by this application.

[0036] Figure 13 It is a structural block diagram of a server provided by this application. Specific implementation manners

[0037] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of this application.

[0038] In the related art, the design process of an integrated circuit can be divided into logic design and physical design. Among them, logic design is to write corresponding logic code according to the usage scenario, function, and related performance requirements of the integrated circuit, following relevant protocol standards. Physical design is to convert the logic code in the logic design stage into gate circuits, and according to the process requirements, complete operations such as layout and wiring of a large number of logic units on a silicon wafer, and after passing the feasibility verification, tape out and hand it over to the process manufacturer to produce the corresponding chip.

[0039] In the existing integrated circuit design process, there is an obvious gap between logic design and physical design: the logic design stage mainly focuses on function implementation, while the timing convergence problem often needs to be exposed through static timing analysis until the physical design stage (such as after layout and wiring). With the continuous increase in the amount of logic code data, the iteration time of very large scale integrated circuits in the physical design stage is getting longer and longer. If the quality problem of the logic code is discovered only in the later stage of physical design, it may lead to readjustment of the logic code, which not only consumes a large amount of resources, but also may introduce new design risks due to repeated modifications.

[0040] To solve the above problems, the present application provides a method for checking the quality of logic code, which realizes the quality check of logic code based on the number of fan-out registers corresponding to a register and the number of fan-in registers of the previous stage. The checking process is easy to implement. Moreover, the checking process is carried out immediately after logic synthesis. Compared with the prior art that checks the quality of logic code after placement and routing are completed, the quality detection of logic code can be completed earlier, effectively avoiding the discovery of logic code anomalies only after all physical designs are completed, which helps to improve the design efficiency of integrated circuits.

[0041] The method for checking the quality of logic code provided by the present application is applied to an electronic device, which can be a laptop computer, a personal computer (PC), a tablet computer. Of course, it can also be other electronic devices that can run the application program corresponding to the method for checking the quality of logic code provided by the present application, which will not be listed one by one here. Of course, in some cases, it can also be applied to a server on the network side. See Figure 1 As shown, the method for checking the quality of logic code provided by the present application includes the following steps.

[0042] S100. After the logic synthesis of the integrated circuit is completed, extract the starting register and the ending register of all timing paths in the integrated circuit.

[0043] In the related art, the logic design process of an integrated circuit can be further divided into two stages, namely logic synthesis and placement and routing. Compared with the related art that checks the quality of logic code after placement and routing are completed, the present application starts to check the quality of logic code immediately after the logic synthesis of the integrated circuit is completed, in order to determine the quality of logic code as soon as possible and avoid unnecessary placement and routing operations in the case of abnormal logic code quality, wasting a lot of manpower and material resources.

[0044] An integrated circuit can be divided into a combinational logic circuit and a sequential logic circuit. Among them, the output of the combinational logic circuit only depends on the current input and has no memory function. While the sequential logic circuit contains not only basic logic gate units but also storage elements such as registers to save past information. Its stable output depends not only on the current input but also on the state formed by past inputs. Each sequential logic circuit corresponds to a timing path, and the start and end of the timing path are divided by registers, that is, each timing path corresponds to a register at the start, that is, the starting register, and correspondingly, it also corresponds to a register at the end, that is, the ending register. In the related art, each timing path can also be called a stack.

[0045] Static Timing Analysis (STA) is a timing verification technique independent of input stimuli. It aims to traverse all timing paths, find the worst-case delay of the timing logic circuit, and check whether the setup time and hold time meet the requirements. This analysis method mainly determines whether the design can operate at the required working frequency by analyzing the maximum and minimum delays of the timing logic paths. This analysis method is very convenient, especially in large integrated circuits, which can greatly reduce the simulation workload and time cost, and ensure the timing correctness of the digital system by combining STA with formal verification. The main purpose of STA is to increase the system's working main frequency and stability by reducing the occurrence of metastability and controlling the synthesis, mapping, placement, and routing results of the logic to reduce logic and routing delays, thereby increasing the working frequency.

[0046] More importantly, through STA analysis, every timing path in the integrated circuit can be traversed. Therefore, as an alternative implementation, the timing constraint file of the integrated circuit and the gate-level netlist after logic synthesis can be obtained first, and static timing analysis can be performed on the gate-level netlist of the integrated circuit based on the timing constraint file to obtain the corresponding analysis results. Finally, the starting register and ending register corresponding to each timing path in the integrated circuit can be extracted from the obtained analysis results. As for the specific execution process of static timing analysis, it can be implemented with reference to related technologies and will not be elaborated here.

[0047] S110. Count the number of fan-out registers of the subsequent stage and the number of fan-in registers of the previous stage for each register.

[0048] Combined with Figure 2 As shown, taking the register Reg as an example, it can be used as the starting register of a certain timing path or the ending register of a certain timing path. Based on this, for each register extracted in S100 in this application, the number of fan-out registers connected to the register and the number of fan-in registers of the previous stage need to be counted.

[0049] In an alternative implementation, after all the registers in the integrated circuit are extracted through S100, a register list can be created to record all the registers in the integrated circuit. Further, when performing this step, the traversal method can be adopted to count the number of fan-out registers of the subsequent stage and the number of fan-in registers of the previous stage corresponding to each register one by one according to the recording order of the register list.

[0050] Specifically, combined with Figure 2As shown, taking the register Reg as an example, starting from the output pin Q of the register Reg, trace backward the logic units directly connected to the Q pin, and then starting from the output segment of this logic unit, continue to trace downstream in the signal transmission direction until the first register connected to the subsequent stage of the register Reg is encountered, then stop tracing, and increment the number of fan-out registers in the subsequent stage by 1. Repeat this process until all the timing paths connected to the subsequent stage of the register Reg are traversed, and the number of fan-out registers corresponding to the register Reg is obtained. For the final statistical result, please refer to Figure 3 as shown, that is, the number of fan-out registers mentioned in this application is the total number of the first registers connected to the subsequent stage of any register.

[0051] In an alternative embodiment, after completing the statistics of the number of fan-out registers corresponding to all the registers in the integrated circuit, the registers can also be sorted in descending order according to the number of fan-out registers, so as to clearly display the number of fan-out registers connected to each register in the integrated circuit. At the same time, it can also be used for the execution of S130 in the subsequent steps. The specific details will be elaborated in the subsequent content and will not be described in detail here.

[0052] Furthermore, still taking the register Reg as an example, starting from the input terminal D of the register Reg, trace backward the logic units directly connected to the D pin, and then starting from the output segment of this logic unit, continue to trace upstream in the signal transmission direction until the first register connected to the previous stage of the register Reg is encountered, then stop tracing, and increment the number of fan-in registers in the previous stage by 1. Repeat this process until all the timing paths connected to the previous stage of the register Reg are traversed, and the number of fan-in registers corresponding to the register Reg is obtained. For the final statistical result, please refer to Figure 4 as shown, that is, the number of fan-in registers mentioned in this application is the total number of the first registers connected to the previous stage of each register.

[0053] It should be noted that the input pins of the register do not allow a multi-driven structure. In digital circuit design, if a signal is simultaneously driven by multiple driving sources, this may cause the value of the signal to be in an uncertain state because different driving sources may send signals at different times, resulting in logic errors or unpredictable behaviors. Therefore, when counting the number of fan-in registers in the previous stage, the logic unit traced back from any register to the previous stage is single, but the signal before this logic unit can be multi-port. For example, in the case of a common two-input AND gate, when counting, it is necessary to continue to trace the units before all the input ports of the first logic unit connected to the input side of the register to ensure that all the timing paths are traversed.

[0054] Referring to the processing method of the number of post-stage fan-in registers mentioned above, after the number of pre-stage fan-in registers corresponding to all registers in the integrated circuit is counted, the registers can also be sorted in descending order according to the number of pre-stage fan-in registers, so as to clearly display the number of pre-stage fan-in registers connected to each register in the integrated circuit.

[0055] S120. Obtain the register quantity threshold value corresponding to the integrated circuit.

[0056] In the design process of the logic code, the realization of the logic function of the integrated circuit requires the cooperation of many standard logic units, such as selectors, comparators, adders, multipliers, shift registers, etc. The circuit shapes of these logic units are relatively regular and easy to integrate. Connecting these logic units together according to the design requirements can form the corresponding data path. At the same time, a specially designed control unit controls the components of the data path to work together according to their respective functional requirements and specific timing relationships.

[0057] In practical applications, the driving ability of each logic unit is limited. When the number of loads connected to any logic unit is greater than its corresponding maximum fan-out value, a buffer needs to be added to meet the driving requirements of all loads.

[0058] Combined with Figure 5 As shown, assuming that the maximum maximum fan-out value corresponding to each stage of logic units is 32, the number of post-stage fan-out units corresponding to each stage of logic units between register RegA and register RegB cannot exceed 32. Once it exceeds, a buffer needs to be added to solve it. Based on Figure 5 As can be seen from the figure, L1_1, L1_2, L1_3... are newly added in the first stage, and L2_1, L2_2, L2_3... are newly added in the second stage. Then, for the timing path from register RegA to register RegB, a total of N-level units L1_1, L2_1, L3_1... LN_1 are newly added.

[0059] It can be understood that taking the post-stage fan-out register as an example, the increase in the number of post-stage fan-out registers affects the timing in two aspects. On the one hand, the metal wires from one starting register to multiple ending registers increase, resulting in insufficient routing channels and easy congestion. On the other hand, the increase in the number of logic unit stages in the post-stage timing path of the register, and the introduction of new buffers will lead to an increase in the total delay of the timing path, which will undoubtedly increase the possibility of timing violations. The same problem exists for the pre-stage fan-in registers and will not be repeated here. It can be seen that if the number of pre-stage fan-in registers or post-stage fan-out registers corresponding to any register is too large, the possibility of timing violations in the timing path to which the register belongs is also greater, and it should be the key inspection object. Further, combined with Figure 5As can be seen, there is a corresponding relationship between the number of input registers in the previous stage and the number of output registers in the subsequent stage and the number of levels of logic units in the timing path.

[0060] Based on the above, the present application provides a method for obtaining the register number threshold corresponding to an integrated circuit. Specifically, refer to Figure 6 As shown, the method provided in this embodiment mainly includes the following steps.

[0061] S1201. Obtain the design parameters of the integrated circuit, where the design parameters include the target clock frequency, the single-stage delay duration, and the target single-stage fan-out value.

[0062] The target clock frequency refers to the clock frequency adopted by the integrated circuit during actual use, which is usually determined during the logic code design stage of the integrated circuit. The target clock frequency can be determined through corresponding design specifications or design guidelines. Of course, the target clock frequency can also be obtained through other means. The present application does not limit the specific acquisition method of the target clock frequency.

[0063] The single-stage delay duration can be obtained in the following manner.

[0064] First, determine the delay duration of the logic unit with the shortest inherent time delay in the integrated circuit as the target unit delay. It can be understood that in the existing logic unit design, different logic units correspond to different inherent time delays, that is, different speed performance thresholds. The higher the speed performance threshold, the faster the signal transmission speed, and correspondingly, the shortest the inherent time delay. The present application takes the delay duration of the logic unit with the shortest inherent time delay as the target unit delay, which means that if there are timing violations in the timing path using the logic unit with the optimal speed performance, then other timing paths will inevitably also generate timing violations.

[0065] Furthermore, segment and statistically analyze the wire delays of all metal lines in the integrated circuit at a preset time interval, fit a normal distribution curve based on the statistical results, and finally determine the expected value of the wire delay calculated based on the obtained normal distribution curve as the target wire delay. Specifically, in combination with Figure 7 As shown, assume that the preset time interval is 1 ps (picosecond). Based on this preset time interval, take each time interval such as 0 - 1 ps, 1 - 2 ps... 29 - 30 ps as the abscissa of the normal distribution function. Secondly, statistically analyze the wire delays of all metal lines in the integrated circuit within each time interval as the ordinate of the normal distribution function, construct a normal distribution curve as shown in Figure 7 and calculate the expected value according to the obtained normal distribution curve , and the obtained expected value of the wire delay is the target wire delay.

[0066] In practical applications, the specific value of the foregoing preset time interval can be determined based on factors such as the actual computing power of the hardware device and the accuracy requirements of the target line delay. This application does not make any limitations in this regard. As for the specific process of fitting the normal distribution curve and calculating the expected value, it can be implemented with reference to related technologies, and this application does not make specific limitations in this regard either.

[0067] Finally, calculate the sum of the target unit delay and the target line delay, and use the obtained calculation result as the single-stage delay duration.

[0068] The target single-stage fan-out value can be determined in the following manner.

[0069] In practical applications, the process manufacturer will give different single-stage fan-out values allowed for logic units. This application uses the single-stage fan-out values provided by the process manufacturer as the preset single-stage fan-out values. Based on this, layout and routing are performed on the integrated circuit according to different preset single-stage fan-out values, and the initial design results corresponding to each preset single-stage fan-out value are obtained. Then, static timing analysis is performed on each initial design result to obtain the corresponding timing violation results. It can be understood that since each initial design result corresponds to a preset single-stage fan-out value, each preset single-stage fan-out value also corresponds to a timing violation result. Based on this, the preset single-stage fan-out value corresponding to the best timing violation result among the preset single-stage fan-out values is used as the target single-stage fan-out value. As for the specific process of static timing analysis and the evaluation method of timing violation results, they can all be implemented with reference to related technologies, and this application does not make specific limitations in this regard. It can be understood that the target single-stage fan-out value determined in the above manner is usually less than the maximum single-stage fan-out value required by the process manufacturer.

[0070] S1202. Determine the register quantity threshold corresponding to the integrated circuit according to the target clock frequency, the single-stage delay duration, and the target single-stage fan-out value.

[0071] First, determine the maximum allowable number of stages corresponding to the integrated circuit according to the target clock frequency and the single-stage delay duration.

[0072] Specifically, it can be calculated according to the following formula: N = T / D (1) Wherein, N represents the maximum allowable number of stages corresponding to the integrated circuit; T represents the target clock frequency; D represents the single-stage delay duration.

[0073] It should be noted that if the calculation result of T / D contains a decimal, the value obtained by rounding up the calculation result is used as the maximum allowable number of stages.

[0074] Secondly, determine the register quantity threshold corresponding to the integrated circuit according to the maximum allowable number of stages and the target single-stage fan-out value.

[0075] Specifically, the register quantity threshold can be calculated according to the following formula.

[0076] M = U N (2) Wherein, M represents the register quantity threshold; U represents the target single-stage fan-out value.

[0077] S130. If the number of pre-stage fan-in registers or the number of post-stage fan-out registers corresponding to any register is greater than the register quantity threshold, it is determined that the logic code of the integrated circuit is abnormal.

[0078] After the foregoing steps, the number of pre-stage fan-in registers and the number of post-stage fan-out registers corresponding to each register in the integrated circuit, as well as the register quantity threshold corresponding to the integrated circuit, have been obtained. Based on this, the number of pre-stage fan-in registers and the number of post-stage fan-out registers corresponding to each register are respectively compared with the register quantity threshold. If there is at least one register whose number of pre-stage fan-in registers or number of post-stage fan-out registers is greater than the register quantity threshold, it indicates that there is a possibility of timing violation in the integrated circuit, and thus it can be determined that the logic design code of the integrated circuit is abnormal.

[0079] In an alternative embodiment, in S110, the registers are sorted in descending order of the number of post-stage fan-out registers and in descending order of the number of pre-stage fan-in registers. Based on this, when performing this step, the statistical results of each register can be compared with the register quantity threshold in turn according to the sorting results of the foregoing steps. It can be understood that the comparison process based on the sorting results can significantly improve the comparison efficiency. For example, if the number of post-stage fan-out registers and the number of pre-stage fan-in registers of the first register in the sorting result are both less than the register quantity threshold, it can be determined that the statistical results of all the remaining registers are less than the register quantity threshold, and thus there is no need to perform subsequent comparison processes. Correspondingly, after it is determined that the number of post-stage fan-out registers and the number of pre-stage fan-in registers of any register are both less than the register quantity threshold, the other registers located after this register also do not need to be judged for the size relationship with the register quantity threshold.

[0080] In summary, the present method realizes the inspection of the quality of logic code based on the number of post-stage fan-out registers and the number of pre-stage fan-in registers corresponding to the registers. The inspection process is simple and easy to implement. Moreover, the physical design of an integrated circuit can be divided into logic synthesis and placement and routing. Compared with the prior art where the quality of logic code is detected after the placement and routing are completed, the method provided in this application can perform code quality detection after the logic synthesis is completed. Therefore, the quality detection of logic code can be completed as early as possible, effectively avoiding the discovery of logic code anomalies only after the entire physical design is completed, which helps to improve the design efficiency of integrated circuits.

[0081] Further, this application provides another method for inspecting the quality of logic code. Refer to Figure 8 as shown, based on the embodiment shown in Figure 1 , the inspection method provided in this embodiment further includes the following steps: S140: Registers with the number of pre-stage fan-in registers or the number of post-stage fan-out registers greater than the register number threshold are used as target registers.

[0082] In the case where it is determined through the foregoing steps that there are quality problems in the logic code of the integrated circuit, registers with the number of pre-stage fan-in registers or the number of post-stage fan-out registers greater than the register number threshold in the integrated circuit are used as target registers.

[0083] In an alternative implementation manner, in S110, each register is sorted in descending order according to the number of post-stage fan-out registers, and each register is sorted in descending order according to the number of pre-stage fan-in registers. Based on this, when performing this step, the statistical results of each register can be compared with the register number threshold in turn according to the sorting results of the foregoing steps, so as to screen out target registers with the number of pre-stage fan-in registers or the number of post-stage fan-out registers greater than the register number threshold.

[0084] Correspondingly, since the number of pre-stage fan-in registers or post-stage fan-out registers connected to the target register is too large, the possibility of a timing violation occurring in the timing path to which the target register belongs is relatively high, and it will be the key optimization object of the method provided in this application.

[0085] S150: Perform logical design optimization or physical design optimization on the target register.

[0086] Since the design of the integrated circuit can be corrected both in the logical design stage and in the physical design stage, this application provides two optimization design ideas to optimize the target register and the timing path to which the target register belongs in the logical design stage and the physical design stage respectively.

[0087] This application provides the following optimization method to perform logical design optimization on the target register.

[0088] In an alternative embodiment, if there are no logic cells between adjacent timing paths, that is, in the signal transmission direction, the end register of the upstream timing path is directly connected to the start register of the adjacent downstream timing path by a metal wire without any logic cells, then a copy operation can be performed on the target register to obtain N target registers, where N ≥ 2. Further, the multiple timing paths to which the target register belongs are decoupled into N groups of optimized timing paths, and each group of optimized timing paths is connected to a target register. Assuming that the number of fan-out registers at the subsequent stage corresponding to the target register is F, after uniform grouping, the number of fan-out registers at the subsequent stage corresponding to each copied target register will become F / N. Thus, the number of fan-out registers corresponding to each of the copied target registers can be significantly reduced. According to the foregoing, in some cases, due to the reduction in the load of the logic cells, the number of buffers used can even be reduced, thereby reducing the number of stages corresponding to the timing path and further shortening the delay duration of the timing path, which helps to repair the timing violation of the timing path.

[0089] In another alternative embodiment, if there are logic cells between adjacent timing paths, then the timing paths to which the target register belongs cannot be decoupled and split. In this case, starting from the target register, traverse step by step along the subsequent timing path to find the earliest branch point of the logic fork. If a branch point of the logic fork is found before traversing to any end register, take the first branch point that appears along the timing path direction as the target branch point, and insert a new register at this target branch point. Connect the original partial logic path connected to the target register through this new register to reduce the fan-out number of the target register, that is, reduce the number of fan-out registers at its subsequent stage finally connected. Correspondingly, if no branch point of the logic fork is found until traversing to the end register, then some logic paths of the target register can be deleted or moved. It should be noted that the premise of this operation is that after deleting or moving the logic path, a logic equivalence check needs to be performed to determine whether the logic function is modified. If the logic is equivalent, the circuit function described by the logic code does not need to be changed. If it is not equivalent, it will cause a modification of the logic function.

[0090] It should be noted that the above optimization measures in the logic design stage are illustrated by taking the fan-out registers at the subsequent stage of the register as an example. The same optimization method can be adopted for the fan-in registers at the previous stage, which will not be repeated here.

[0091] If it is difficult to perform repairs and optimizations during the logic design phase before the code is completed, logic synthesis and placement and routing can be performed in the conventional manner, that is, physical design is carried out. Due to congestion and increased timing path delay caused by high fan-in or high fan-out problems, resulting in timing violations, optimizations can also be carried out during the physical design phase. For this purpose, the present application further provides a method for optimizing target registers during the physical design phase. See Figure 9 As shown, the method specifically includes the following steps.

[0092] S1501. Obtain the physical design layout of the integrated circuit.

[0093] After completing the physical design processes such as logic synthesis and placement and routing of the integrated circuit, the physical design layout of the integrated circuit can be obtained. Combining the Figure 10 schematic diagram of the physical design layout shown and the relevant information of the physical design layout in the related art, it can be known that the physical design layout of the integrated circuit not only records the physical dimensions of each logic unit in the integrated circuit, but also records the position coordinates of each logic power supply in the physical design layout. Of course, other relevant information is also recorded in the physical design layout, which will not be elaborated here.

[0094] S1502. Extract the path information of each timing path to which the target register in the physical design layout belongs.

[0095] During the physical design process, static timing analysis can also be performed on the integrated circuit. According to the static timing analysis results, the timing paths with timing violations in the integrated circuit can be determined. In one possible application scenario, the timing paths with timing violations are also the timing paths with high fan-in or high fan-out determined through the foregoing steps. In another possible application scenario, the timing paths with timing violations do not belong to the timing paths with high fan-in or high fan-out, but are caused by other reasons. For the latter application scenario, the logical quantity of the timing paths is often small and the structure is relatively simple, and conventional optimization methods can be used for optimization, such as reducing the timing path delay, replacing logic units with faster speeds, and adjusting the clock duration, etc., without using the optimization method provided by the present application. The optimization method provided by the present application mainly aims at the former application scenario.

[0096] For each target register determined in the foregoing steps, extract the path information of each timing path to which the target register in the physical design layout belongs, specifically including the position coordinates of the starting register and the ending register corresponding to each timing path in the physical design layout. It can be understood that for any timing path, one of the starting register and the ending register must be the target register, that is to say, the target register may be the register with the number of fan-in registers in the previous stage greater than the register number threshold, or the register with the number of fan-out registers in the subsequent stage greater than the register number threshold.

[0097] Further, the path information may further include the current stage number corresponding to the timing path. The statistics of the timing path stage number can be completed in the logic synthesis stage or in the physical design stage. Regardless of the specific stage, the rule for counting the current stage number is the same, that is, count the number of all logic units and buffers between the starting register and the ending register in any timing path, and the obtained number is the current stage number of the corresponding timing path.

[0098] Of course, the path information may further include other information, which will not be elaborated here for the time being.

[0099] S1503. Based on the path information, determine the target timing path to be optimized among the timing paths to which the target register belongs.

[0100] In practical applications, the position coordinates of each logic unit in the physical design layout of the integrated circuit are determined under the same preset coordinate system. Therefore, the Manhattan distance between any two logic units can be calculated based on the position coordinates of each logic unit. Based on this, in an optional implementation manner, for each timing path to which the target register belongs, calculate the stack distance between the starting register and the ending register according to the position coordinates of the starting register and the ending register of the timing path. For example, if the position coordinate of the starting register is (X1, Y1) and the position coordinate of the ending register is (X2, Y2), then the stack distance corresponding to this timing path is |X2 - X1| + |Y2 - Y1|. All timing paths are calculated one by one using the same calculation method until the stack distances of all timing paths to which the target register belongs are obtained.

[0101] Further, compare the size relationship between the stack distance of each timing path and the preset stack distance threshold, and use the timing path with a stack distance greater than the preset stack distance threshold as the target timing path to be optimized. As mentioned above, different timing paths may correspond to different stage numbers, and the longer the transmission distance of the timing path with more stages. And the timing paths to which the target register belongs have different lengths. Therefore, each timing path may correspond to a different preset stack distance threshold. In an optional implementation manner, a mapping relationship between the timing path stage number and the preset distance threshold can be established, and the mapping relationship can be queried according to the current stage number of different timing paths, so as to determine the preset distance threshold matching the stage number of this timing path. Of course, the preset distance threshold matching the actual situation of the timing path can also be determined by other means, which will not be elaborated here. Without exceeding the core idea of this application, it also belongs to the scope protected by this application.

[0102] In another alternative embodiment, it is also possible to determine whether a timing path needs to be optimized based on the number of stages of the timing path. Specifically, for each timing path in the timing paths to which the target register belongs, the current number of stages of each timing path is counted. The specific counting method can refer to the foregoing content and will not be repeated here. Further, the magnitude relationship between the current number of stages of each timing path and the maximum allowable number of stages of the integrated circuit is compared. Among the timing paths to which the target register belongs, the timing paths with the current number of stages greater than the maximum allowable number of stages are used as the target timing paths to be optimized, where the maximum allowable number of stages is determined based on the target clock frequency of the integrated circuit and the single-stage delay duration. The specific calculation process can be found in the relevant content of S1202 in the foregoing Figure 1 illustrated embodiment, which will not be repeated here.

[0103] S1504. Optimize the design of the target timing path.

[0104] After determining the target timing path to be optimized based on the foregoing steps, the target timing path can be optimized. The specific optimization method can be one or more of the following three methods.

[0105] In an alternative embodiment, the layout of the integrated circuit can be updated, that is, the target timing path is processed in the layout stage, mainly to shorten the link length of the target timing path. Specifically, the single-stage delay duration Ds corresponding to the target timing path before the pre-optimization design and the link length L of the target timing path are obtained. Assuming that the link length of the target timing path after the update is X, then X should satisfy the following relational expression: (3) where X represents the link length of the target timing path after the update; T represents the target clock frequency of the integrated circuit.

[0106] It can be understood that in practical applications, it is necessary to consider the optimization processing of the pre-stage path and the post-stage path of the target register at the same time.

[0107] In another alternative embodiment, the metal layer to which the metal wires in the target timing path belong can be adjusted, and the metal wires in the target timing path are preferentially routed to the high-thickness metal layer with a smaller resistance. That is, the metal wires with the largest delay are preferentially adjusted to the high-thickness metal layer, and the wiring resource priorities are dynamically allocated. Specifically, first, obtain the utilization of the high-level metal wire (i.e., the metal wire with a thicker metal layer) wiring resources in the area passed by the target timing path in the physical design layout. If there is no metal wire occupied in the corresponding area, directly arrange the metal wires of the target timing path to this high-level metal layer; on the contrary, if there are already metal wires arranged in this area, sort the priorities according to the size of the violation. For example, an integrated circuit has 14 metal layers, and the resistances are sorted from large to small as 1, 2, 3... 14. Select a metal wire area with the largest wire delay on the target path, and obtain the timing violation conditions of each layer of wires inside the area from the static timing analysis results, and adjust the wiring metal selection priority of the target path according to the size of the violation. Then, the length and width of the target path area are selected. With the metal wire as the center, the length of the area is specified as the length of the metal wire passing through, and the width of the area is the area enclosed by multiplying the width of the metal wire by a preset ratio. As for the specific implementation method of updating the layer to which the metal wire belongs, it can also refer to the related technology and will not be elaborated here.

[0108] After updating the wiring information, if the timing violation still cannot be repaired, continue to select other metal wire areas with a larger delay sorting on the target timing path, and continue to adjust the metal wire weights. Through this solution, the common path is preferentially processed. That is, for the multi-fanout path, the metal wire weights can be adjusted sequentially from the starting point according to the above solution, and for the multi-fanin path, the metal wire weights can be adjusted sequentially from the end point backwards according to the above solution.

[0109] In another alternative embodiment, during the clock tree synthesis stage, the timing path length of the starting register or the ending register of the target timing path can also be adjusted. That is, for the starting register of the high-fanout path, shorten the clock path length, or for the ending register of the high-fanin path, extend the clock path length. The specific clock path length adjustment method can refer to the related technology and will not be elaborated here.

[0110] If the requirements are still not met after processing according to the above optimization measures, the above steps can be repeated until the optimized physical design meets the requirements.

[0111] In summary, based on the foregoing embodiments, the inspection method provided in this embodiment can optimize the target register with high fan-in or high fan-out, and provide a method for screening the target timing path to be optimized according to the stack distance and the number of levels of the timing path, which can efficiently screen the target timing path in multiple timing paths, help improve the design efficiency of the integrated circuit, and shorten the design cycle of the integrated circuit.

[0112] The following introduces the logic code quality inspection device provided by the present invention. The logic code quality inspection device provided by the present invention belongs to the same inventive concept as the logic code quality inspection method provided in the embodiments of the present application, can execute the logic code quality inspection method provided in any embodiment of the present application, and has the corresponding functional modules and beneficial effects for executing the logic code quality inspection method. For technical details not described in detail in this embodiment, reference can be made to the logic code quality inspection method provided in the embodiments of the present application, which will not be elaborated here.

[0113] See Figure 11 , the integrated circuit logic code quality inspection device provided in this embodiment includes the following units: The first acquisition unit 10 is used to extract the starting register and the ending register of all timing paths in the integrated circuit after the logic synthesis of the integrated circuit is completed; The statistics unit 20 is used to count the number of fan-out registers of the subsequent stage and the number of fan-in registers of the previous stage of each register. The number of fan-out registers of the subsequent stage is the total number of the first registers connected to the subsequent stage of this register, and the number of fan-in registers of the previous stage is the total number of the first registers connected to the previous stage of this register; The second acquisition unit 30 is used to obtain the register quantity threshold corresponding to the integrated circuit; The determination unit 40 is used to determine that the logic code of the integrated circuit is abnormal if the number of fan-in registers of the previous stage or the number of fan-out registers of the subsequent stage corresponding to any register is greater than the register quantity threshold.

[0114] Furthermore, the present application also provides another integrated circuit logic code quality inspection device. See Figure 12 As shown, on the basis of the embodiment shown in Figure 11 , the inspection device provided in this embodiment further includes: The screening unit 50 is used to use the register whose number of fan-in registers of the previous stage or the number of fan-out registers of the subsequent stage is greater than the register quantity threshold as the target register; The optimization unit 60 is used to perform logical design optimization or physical design optimization on the target register.

[0115] Next, refer to Figure 13 to describe the server provided in the embodiment of the present invention. The server provided in this embodiment may include: at least one processor 100, at least one communication interface 200, at least one memory 300, and at least one communication bus 400; In the embodiment of the present invention, the number of the processor 100, the communication interface 200, the memory 300, and the communication bus 400 is at least one, and the processor 100, the communication interface 200, and the memory 300 complete communication with each other through the communication bus 400; Obviously,Figure 13 The communication connection shown among the processor 100, communication interface 200, memory 300 and communication bus 400 shown is only optional; Optionally, the communication interface 200 may be an interface of a communication module, such as an interface of a GSM module; The processor 100 may be a central processing unit CPU, or a specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0116] The memory 300 may include high-speed RAM memory and may also include non-volatile memory, such as at least one disk memory.

[0117] Among them, the processor 100 is specifically configured to execute the application programs in the memory to implement the steps of the above-described logical code quality inspection method.

[0118] In some embodiments, the present embodiment also provides a computer-readable storage medium, such as a floppy disk, optical disk, hard disk, flash memory, USB flash drive, SD (Secure Digital Memory Card) card, MMC (Multimedia Card) card, etc. One or more instructions for implementing the above steps are stored in the computer-readable storage medium. When the one or more instructions are executed by one or more processors, the processor executes the logical code quality inspection method described above. For the related specific implementation, please refer to the foregoing description and will not be elaborated here.

[0119] In addition to the above methods and devices, the embodiments of the present application may also be a computer program product, which includes computer program instructions. When the computer program instructions are run by a processor, the processor executes the steps in the logical code quality inspection method according to various embodiments of the present application described above in this specification.

[0120] The computer program product can be written in any combination of one or more programming languages to write program code for performing the operations of the embodiments of the present application. The programming languages include object-oriented programming languages, such as Java, C++, etc., and also include conventional procedural programming languages, such as the "C" language or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, executed as an independent software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0121] Those skilled in the art can understand that the content disclosed in the present disclosure can have various variations and improvements. For example, the various devices or components described above can be implemented by hardware, or by software, firmware, or a combination of some or all of the three.

[0122] In addition, although the present disclosure makes various references to certain units in the system according to the embodiments of the present disclosure, however, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0123] Flowcharts are used in the present disclosure to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the preceding or subsequent steps do not necessarily need to be carried out precisely in sequence. On the contrary, they can be carried out in reverse order or various steps can be processed simultaneously. At the same time, other operations can also be added to these processes.

[0124] Those of ordinary skill in the art can understand that all or part of the steps in the above methods can be completed by instructing relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, etc. Optionally, all or part of the steps of the above embodiments can also be implemented using one or more integrated circuits. Accordingly, the various modules / units in the above embodiments can be implemented in the form of hardware or in the form of software function modules. The present disclosure is not limited to any specific form of the combination of hardware and software.

[0125] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure pertains. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formalized sense, unless explicitly defined as such herein.

[0126] The above is an explanation of the present disclosure and should not be considered a limitation thereof. Although several exemplary embodiments of the present disclosure have been described, those skilled in the art will easily understand that many modifications can be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure defined by the claims. It should be understood that the above is an explanation of the present disclosure and should not be considered limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A method for checking the quality of logic code, characterized in that: include: After completing the logic synthesis of the integrated circuit, extracting the starting register and the ending register of all the timing paths in the integrated circuit; Count the number of subsequent fan-out registers and the number of previous fan-in registers of each register, where the number of subsequent fan-out registers is the total number of the first register connected to the subsequent stage of the register, and the number of previous fan-in registers is the total number of the first register connected to the previous stage of the register; Obtaining a register quantity threshold corresponding to the integrated circuit; If the number of preceding fan-in registers or the number of succeeding fan-out registers corresponding to any register is greater than the register number threshold, it is determined that the logic code of the integrated circuit is abnormal.

2. The method according to claim 1, characterized in that Extracting the starting register and the ending register of all timing paths in the integrated circuit, including: Obtaining a timing constraint file of the integrated circuit and a gate netlist obtained after completing logic synthesis; Static timing analysis is performed on the gate netlist based on the timing constraint file, and the starting register and the end register corresponding to each timing path are identified through the static timing analysis.

3. The method according to claim 1, characterized in that: Obtaining a register quantity threshold corresponding to the integrated circuit, including: Acquire design parameters of the integrated circuit, wherein the design parameters include a target clock frequency, a single-stage delay time, and a target single-stage fan-out value; A threshold value of the number of registers corresponding to the integrated circuit is determined according to the target clock frequency, the single-stage delay time and the target single-stage fan-out value.

4. The method according to claim 3, characterized in that Determining a threshold value of the number of registers corresponding to the integrated circuit according to the target clock frequency, the single-stage delay time, and the target single-stage fan-out value includes: Determining a maximum allowed number of stages corresponding to the integrated circuit according to the target clock frequency and the single-stage delay time; A threshold value of the number of registers corresponding to the integrated circuit is determined according to the maximum allowed number of stages and the target single-stage fan-out value.

5. The method according to claim 3, characterized in that: The process of obtaining the single-stage delay duration includes: Determining the delay time length of the logic unit with the shortest inherent time delay in the integrated circuit as the target unit delay; Performing segmented statistics on the line delays of all metal lines in the integrated circuit at preset time intervals, and fitting a normal distribution curve based on the statistical results; Determine the expected value of line delay calculated based on the normal distribution curve as the target line delay; The sum of the target unit delay and the target line delay is determined as the single-stage delay length.

6. The method according to claim 3, characterized in that The process of obtaining the target single-stage fan-out value includes: According to different preset single-stage fan-out values, the layout and routing of the integrated circuit are completed to obtain corresponding initial design results; Performing static timing analysis on each of the initial design results to obtain corresponding timing violation results; The preset single-stage fan-out value corresponding to the best timing violation result among the preset single-stage fan-out values ​​is used as the target single-stage fan-out value.

7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: The registers whose number of previous-stage fan-in registers or subsequent-stage fan-out registers is greater than the register number threshold are used as target registers; Performing logic design optimization or physical design optimization on the target register.

8. The method according to claim 7, characterized in that The process of performing logic design optimization on the target register includes: Copying the target register to obtain N target registers, where N is greater than or equal to 2; Decoupling the target timing path to which the target register belongs into N groups of optimized timing paths; Each group of the optimized timing paths is connected to one of the target registers.

9. The method according to claim 7, characterized in that: The process of performing logic design optimization on the target register includes: Starting from the target register, traversing along the subsequent timing path step by step; If there is a branch point of logical bifurcation before traversing to the end register, insert a new register at the target branch point so that the new register connects part of the logical path, and the target branch point is the first branch point that appears along the timing path direction; If the destination register is traversed and there is no branch point of logical bifurcation, a portion of the logical path of the target register is deleted or moved.

10. The method according to claim 7, characterized in that The process of performing physical design optimization on the target register includes: Obtaining a physical design layout of the integrated circuit; Extracting path information of each timing path to which the target register belongs in the physical design layout; Based on the path information, determining a target timing path to be optimized among the timing paths to which the target register belongs; The target timing path is optimized and designed.

11. The method according to claim 10, characterized in that The path information includes the position coordinates of the starting register and the ending register of the timing path in the physical design layout; Determining a target timing path to be optimized in each timing path to which the target register belongs based on the path information includes: For each timing path to which the target register belongs, based on the position coordinates of the starting register and the ending register of the timing path, the stack distance between the starting register and the ending register is calculated; The timing path whose inter-stack distance is greater than a preset inter-stack distance threshold is used as a target timing path to be optimized.

12. The method according to claim 10, characterized in that The path information includes the current level corresponding to the timing path; Determining a target timing path to be optimized in each timing path to which the target register belongs based on the path information includes: Among the timing paths to which the target register belongs, the timing path whose current number of stages is greater than the maximum allowed number of stages is taken as the target timing path to be optimized, and the maximum allowed number of stages is determined based on the target clock frequency of the integrated circuit and the single-stage delay duration.

13. The method according to claim 10, characterized in that Optimizing the target timing path includes at least one of the following methods: shortening the link length of the target timing path; Adjusting the metal layer to which the metal line in the target timing path belongs; In the clock tree synthesis stage, the clock path length of the start register or the end register of the target timing path is adjusted.

14. A logic code quality inspection device, characterized in that: include: A first acquisition unit is used to extract the starting register and the ending register of all timing paths of the integrated circuit after completing the logic synthesis of the integrated circuit; A statistical unit, used to count the number of subsequent fan-out registers and the number of previous fan-in registers of each register, wherein the number of subsequent fan-out registers is the total number of the first register connected to the subsequent stage of the register, and the number of previous fan-in registers is the total number of the first register connected to the previous stage of the register; A second acquisition unit, used to acquire a register quantity threshold value corresponding to the integrated circuit; The determination unit is used to determine that the logic code of the integrated circuit is abnormal if the number of previous-stage fan-in registers or the number of subsequent-stage fan-out registers corresponding to any register is greater than the register number threshold.

15. A server comprising a memory, a processor, and a computer program stored in the memory and executed by the processor, characterized in that: When the processor executes the computer program, the steps of the logic code quality checking method according to any one of claims 1 to 13 are implemented.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the logic code quality checking method according to any one of claims 1 to 13 are implemented.

Images