Wiring method, device and equipment for chip layout and readable storage medium

Abstract

The invention provides a wiring method, device and equipment for a chip layout and a readable storage medium. The method comprises the steps that a layout object and a corresponding wiring area are determined based on wiring parameters of a chip; wherein the layout object comprises all target signal lines meeting the chip delay deflection requirement and buffer units connected to the target signal lines; determining a target position parameter of each layout object in the wiring area based on a preset wiring strategy; and based on each target position parameter, respectively arranging each layout object into the wiring area so as to output the chip layout. According to the scheme, on the basis of the delay skew requirement of DDR layout design, the routing mode of the matched signal lines can be optimized, the buffer units with high driving capacity are selected, the positions of the buffer units are determined on the basis of the layout of SSTL IO and PHY, layout placement of all the signal lines and the buffer units is completed by using a wiring tool, and while it is ensured that the DDR delay skew requirement is met, the service life of the buffer units is prolonged. And the wiring efficiency is greatly improved.

Description

Technical Field

[0001] The present application relates to the technical field of chip design, and particularly to a wiring method, device, equipment and readable storage medium for a chip layout. Background Art

[0002] In the related art, the DDR IP protocol for chips has put forward requirements for delay skew for DDR3 / DDR4; with the update and iteration of DDR, the rate of DDR is getting higher and higher, the working voltage is getting lower and lower, and the data transmission rate is getting faster and faster. The requirements for the delay skew of matching signals are also getting stricter. Moreover, as the semiconductor chip design becomes more and more complex, there is usually more than one set of differential clock pairs and key signals in the whole design that need to perform delay matching. For this reason, it is usually necessary to adjust the signal lines one by one manually. However, using manual adjustment is very time-consuming and not conducive to design iteration. This inefficient design method is no longer applicable to large-scale digital chip designs with a large number of differential clock pair signals, a large number of key signals, and strict requirements for delay skew, and an efficient wiring method needs to be found. Summary of the Invention

[0003] Embodiments of the present application provide a wiring method, device, equipment and readable storage medium for a chip layout, which can at least solve the problems of low efficiency of the wiring method for the chip layout in the related art and difficulty in meeting the strict requirements for delay skew of matching signals.

[0004] The first aspect of the embodiments of the present application provides a wiring method for a chip layout, including:

[0005] Determining a layout object for the layout based on the wiring parameters of the chip, and determining the wiring area where the layout object is located; wherein, the layout object includes all target signal lines that meet the chip delay skew requirements and buffer units connected to the target signal lines;

[0006] Determining target position parameters of each layout object in the wiring area based on a preset wiring strategy;

[0007] Layouting each layout object into the wiring area respectively based on each target position parameter to output a chip layout.

[0008] The second aspect of the embodiments of the present application provides a wiring device for a chip layout, including:

[0009] A first determination module, configured to determine a layout object for the layout based on the wiring parameters of the chip, and determine the wiring area where the layout object is located; wherein, the layout object includes all target signal lines that meet the chip delay skew requirements and buffer units connected to the target signal lines;

[0010] The second determination module is configured to determine the target position parameters of each layout object in the routing area based on a preset routing strategy;

[0011] The layout output module is configured to layout each layout object in the routing area respectively based on the target position parameters, so as to output the chip layout.

[0012] In a third aspect of the embodiments of the present application, an electronic device is provided, including: a memory and a processor. The processor is configured to execute a computer program stored on the memory. When the processor executes the computer program, each step in the routing method of the chip layout provided in the first aspect of the embodiments of the present application is implemented.

[0013] In a fourth aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, each step in the routing method of the chip layout provided in the first aspect of the embodiments of the present application is implemented.

[0014] As can be seen from the above, according to the routing method, device, equipment and readable storage medium of the chip layout provided by the solution of the present application, the layout objects are determined based on the routing parameters of the chip, and the routing area where the layout objects are located is determined; wherein, the layout objects include all target signal lines that meet the chip delay skew requirements and the buffer units connected to the target signal lines; based on a preset routing strategy, the target position parameters of each layout object in the routing area are determined; based on the target position parameters, each layout object is respectively laid out in the routing area, so as to output the chip layout. Through the implementation of the solution of the present application, the signal lines that meet the delay skew requirements are determined according to the routing parameters required by the IP manual, and the position parameters of the signal lines and the corresponding buffer units are determined based on a preset routing strategy, that is, the routing mode of each signal line is determined; then, based on the calculated position parameters, the signal lines and the corresponding buffer units are laid out in the corresponding positions of the layout structure by using a routing tool, so as to obtain a chip layout that meets the chip design requirements; thus controlling the routing operation of the chip layout can effectively improve the DDR delay skew requirement efficiency of the chip layout structure and improve the routing operation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic flowchart of the basic process of a routing method of a chip layout provided in the first embodiment of the present application;

[0016] Figure 2 It is a schematic diagram of the placement positions of a PHY and an IO provided in the first embodiment of the present application;

[0017] Figure 3 It is a schematic diagram of the signal feature composition of a delay skew group provided in the first embodiment of the present application;

[0018] Figure 4 Schematic diagram of the composition of a chip layout structure provided by the first embodiment of the present application;

[0019] Figure 5 Schematic diagram of the brief routing of a differential signal line provided by the first embodiment of the present application;

[0020] Figure 6 Schematic diagram of the brief routing of a differential signal line when the line length needs to be compensated provided by the first embodiment of the present application;

[0021] Figure 7 Schematic diagram of the refined routing of a differential signal line provided by the first embodiment of the present application;

[0022] Figure 8 Schematic diagram of the routing of a non-differential signal line provided by the first embodiment of the present application;

[0023] Figure 9 Schematic diagram of a visual delay skew provided by the first embodiment of the present application;

[0024] Figure 10 Schematic diagram of the refined process of a chip layout wiring method provided by the second embodiment of the present application;

[0025] Figure 11 Schematic diagram of the program module of a chip layout wiring device provided by the third embodiment of the present application;

[0026] Figure 12 Schematic diagram of the structure of an electronic device provided by the fourth embodiment of the present application. Detailed implementation manners

[0027] In order to make the invention objectives, features, and advantages of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0028] In the description of the embodiments of the present application, it should be understood that the orientation or positional relationships indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0029] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, "a plurality of" means two or more unless otherwise specifically defined.

[0030] In the embodiments of the present application, unless otherwise clearly specified and limited, terms such as "installed", "connected", "coupled", "fixed", etc. shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0031] To solve the problems in the related art that the wiring method of the chip layout is inefficient and it is difficult to meet the strict delay skew requirements of the matching signals, the first embodiment of the present application provides a wiring method for a chip layout, as Figure 1 is a schematic diagram of the basic process of the wiring method for the chip layout provided in this embodiment. The wiring method for the chip layout includes the following steps:

[0032] Step 101: Determine the layout objects of the layout based on the wiring parameters of the chip, and determine the wiring area where the layout objects are located.

[0033] Specifically, the layout objects of the layout include all target signal lines that meet the chip delay skew requirements and buffer units connected to the target signal lines. Among them, one or more buffer units can be provided on the same target signal line. In some embodiments, the above wiring parameters can be obtained based on the chip's IP manual, directly input by the user, or selected and determined by the user from the database table, and no further limitation is made here. Preferably, the wiring parameters can be extracted from the chip IP manual. That is, in this embodiment, various design information of the chip, including wiring parameters, wiring rules, etc., can be stored through the chip IP manual, and these design information of the chip can be recorded in the form of a netlist, a constraint file, etc. As Figure 2As shown, before the steps of determining the layout objects based on the chip's wiring parameters and determining the wiring area where the layout objects are located, it is also possible to first determine the positions of the PHY and IO based on the requirements of the chip IP manual, and reserve enough core area (i.e., the above-mentioned wiring area) between the PHY and IO to place the layout objects (i.e., the above-mentioned target signal lines and buffer units).

[0034] Step 102: Based on a preset wiring strategy, determine the target position parameters of each layout object in the wiring area.

[0035] Specifically, in the wiring strategy, the relevant routing methods can be determined by combining the type of the target signal line, communication transmission requirements, etc., so as to determine the positions of each signal line and the insertion positions of the buffer units, in order to perform precise wiring operations subsequently.

[0036] Step 103: Based on each target position parameter, layout each layout object into the wiring area respectively to output the chip layout.

[0037] Specifically, after determining the position parameters of each target signal line and buffer unit, corresponding TCL script languages can be generated based on these position parameters, so as to control the APR tool to perform wiring automatically and orderly through these TCL script languages, and finally obtain the required chip layout. During the wiring process, the routing behavior can be precisely controlled through the wiring tool. For example: using high-level metal routing to reduce the load of the line; adding shield lines to maintain the consistency of the sidewall capacitance of differential signal lines; adopting the shortest routing method to reduce the ratio of the routing delay to the path delay.

[0038] In some embodiments of this embodiment, the wiring parameters include PHY position parameters and IO position parameters; correspondingly, the above step of determining the layout objects based on the chip's wiring parameters includes: combining the PHY position parameters and IO position parameters to determine all target signal lines that meet the chip delay skew requirements; wherein, one end of the target signal line is connected to the target IO, and the other end is connected to the PHY; based on the chip IP manual, determine the demand parameters of each target signal line for delay skew respectively; according to each demand parameter, determine the delay skew group to which each target signal belongs respectively; wherein, all target signal lines within the same delay skew group meet the delay skew requirements defined by the same target skew value; based on the buffer unit layout rules corresponding to each delay skew group, determine all buffer units corresponding to each target signal line.

[0039] Specifically, the PHY (Physical Layer) is the physical layer of the chip. The DDR PHY in this embodiment can be used to be responsible for signal transmission and processing at the actual physical level to implement functions such as sending and receiving data signals, extracting and synchronizing clock signals, and controlling data timing. Information such as the location of the PHY, the location of each IO, and the number of wirings between the PHY and the IO can be determined through the netlist file in the IP manual, so as to determine the target signal lines and buffer units that need to be routed and laid out, and determine the reserved spacing between the PHY and the IO (that is, determine the above-mentioned wiring area), and reserve sufficient wiring resources for subsequent wiring operations. The buffer unit layout rules in this embodiment can be obtained based on the chip IP manual. Among them, the buffer unit layout rules include the placement requirements of the chip for the buffer units, and the placement requirements include: requirements made by each target signal line for at least one of the influencing factors such as the delay difference of the up / down flip units, the signal transition time difference of the output rising / falling edges, the output pin capacitance, the power consumption, and the driving ability of the buffer unit. Based on the comprehensive consideration of the above influencing factors, the buffer units that meet the requirements are selected for insertion. It can be understood that the buffer unit layout rules in this embodiment are used only after the required target signal lines are determined, that is, after the required target signal lines and the routing methods of each target signal line are determined, can the number of buffer units to be inserted be further calculated; and in this embodiment, the target signal lines in different delay skew groups correspond to different routing method requirements.

[0040] Further, in some embodiments of this embodiment, after the step of combining the PHY position parameters and the IO position parameters to determine all target signal lines that meet the chip delay skew requirements, it further includes: calculating the number of target signal lines, the total width of the first line widths of all target signal lines, the total line spacing between adjacent target signal lines, and the total width of the second line widths of all shield lines based on the chip IP manual; combining the number of target signal lines, the total width of the first line widths, the total line spacing, and the total width of the second line widths to determine the wiring area where the layout object of the layout is located.

[0041] In some embodiments of this embodiment, the delay skew group includes a differential signal line group and a non-differential signal line group; specifically, the target signal lines in the differential signal line group are differential signal lines, and the target signal lines in the non-differential signal line group are non-differential signal lines. The target signal lines in the same delay skew group have the same delay skew value (T_skew). During the grouping process, that is, during the process of determining the delay skew group to which each target signal belongs, information such as the signal transition time and the data transmission direction of each group of target signal lines can also be determined. It can be passed through such as Figure 3Record the signal line characteristics of each delay skew group in the manner shown, where T_tran represents the signal transition time, that is, the time required for the signal to be transmitted from the input end of one clock cycle to the output end of the next clock cycle; T_skew represents the delay skew value. Delay skew refers to the difference in transmission times on different paths among multiple signal paths, and it is the control threshold set by the designer for these delay differences; Group_N represents the Nth group after grouping; Direction represents the data direction of each path within the group. If the data comes in from outside the chip, it is set to input; if the data is output from the chip to the outside, it is set to output; Group is the path formed by the starting point and the ending point of each routing path within the group.

[0042] Further, in some embodiments of the present embodiment, the delay skew group includes a differential signal line group and a non-differential signal line group; correspondingly, based on the preset routing strategy, determining the target position parameters of each layout object in the routing area includes: based on the preset routing strategy, determining the placement requirements of buffer units on each target signal line, and determining the routing requirements of the target signal lines in each delay skew group; among them, the routing requirements corresponding to the differential signal line group include: all signal lines in the group are routed in parallel, the routing lengths are equal, and shielding lines are added on both sides of the signal lines; the buffer unit is used to divide the target signal line into multiple sub-segments; the routing requirements corresponding to the non-differential signal line group include: the routing lengths of all signal lines in the group are equal, and the lengths of the sub-segments of all signal lines in the group are less than or equal to the preset line length value; combining the placement requirements and the routing requirements, determine the target position parameters of each layout object in the routing area.

[0043] Specifically, as Figure 4 Shown is a schematic diagram of a chip layout structure provided by this embodiment. To construct a layout structure that meets the DDR delay skew requirement performance requirements, requirements such as length and routing method need to be made for the target signal lines of each delay skew group. In some specific embodiments, the routing requirements corresponding to the differential signal line group may further include: meeting the wiring requirements of 2 times the minimum line width, 2 times the line pitch, parallel routing, and using ground wires as shielding lines on both sides of the differential lines. Here, the "line width" may refer to the preset standard line width, and the "line pitch" may refer to the preset standard line pitch; the routing requirements corresponding to the non-differential signal line group may further include: meeting the wiring requirements such as 2 times the minimum line width, single or 2 times the line pitch, and S-shaped winding; through the setting of these wiring requirements, the delay skew requirements between the differential signals of the differential pair and between the matching signal lines can be achieved.

[0044] In some specific embodiments, the lengths of the target signal lines and their sub - segments in the non - differential signal line group can be determined based on the constraint file in the IP manual. That is, based on the distance between the IO farthest from the PHY and the PHY and the number of buffer units to be inserted, the maximum length of each section of the non - differential signal line (i.e., the above - mentioned preset line length value) can be determined and the corresponding constraint file can be generated.

[0045] Further, in some embodiments of this embodiment, the step of determining the target position parameters of each layout object in the routing area by combining the placement requirements and the routing requirements includes: determining the number of buffer unit stages of each target signal line based on the placement requirements; where the number of buffer unit stages represents the number of buffer units on the same target signal line; combining the number of buffer unit stages and the routing requirements to determine the target position parameters of each layout object in the routing area.

[0046] Specifically, in this embodiment, based on the placement requirements, that is, based on the requirements made by at least one of the influencing factors such as the delay difference of the target signal line in each delay skew group for the up / down flip - flop unit, the output rising - edge / falling - edge signal conversion time difference, the output - end pin capacitance, the power consumption, and the driving ability of the buffer unit, the type of the buffer unit can be determined first, and then according to the type of the buffer, the number of buffer unit stages of the target signal line can be determined. There are two types of buffer units used in this embodiment, one is a buffer and the other is an inverter; among them, two inverters can form a buffer. In the process of determining the type of buffer unit used, the number of buffer unit stages, and the position of the buffer unit in this embodiment, aspects such as the delay difference of the signal line for the up / down flip - flop unit, the output rising - edge / falling - edge signal conversion time difference, the output - end pin capacitance, the driving ability, and the power consumption can be considered.

[0047] Exemplarily, for the TSMC28 process, based on the above - mentioned placement requirements, finally, CKND*BWP40P140 can be selected as the buffer unit from three types of buffer units: CKND*BWP40P140, CKBD*BWP40P140, and INVD*BWP40P140, and the selection factors are shown in Table 1.

[0048] Table 1

[0049]

[0050] Specific comparative analysis is as follows:

[0051] 1. Delay difference of the up / down flip - flop unit: Comparing the t PLH and t PHL of the three types of units, the difference of the CKND*BWP40P140 unit is smaller.

[0052] 2. Output rising / falling edge signal conversion time difference: Comparing the rising and falling signal conversion time of the three types of units, the difference between the rising and falling edges of the CKND*BWP40P140 unit is smaller, and the difference of individual units can be as low as 1.52ps.

[0053] 3. Within the range of the signal conversion time lookup table, select a buffer unit with driving capability that meets the requirements; the impact of load deviation on the delay of a buffer unit with large driving capability is smaller than that on the delay of a buffer unit with small driving capability, and the line delay is also relatively small.

[0054] 4. Unit delay: Path delay consists of unit delay and line delay. A larger unit delay can significantly reduce the impact of line differences on delay skew differences. In this embodiment, the line delay is required to account for about 30% of the path delay.

[0055] Therefore, based on the above considerations, the CKBD unit can be selected as the buffer unit on the path.

[0056] Further, in some implementations of the present embodiment, the step of determining the number of buffer unit levels for each target signal line according to the placement requirements includes: when it is determined based on the placement requirements that all buffer units on the same target signal line are buffers, determining that the corresponding number of buffer units is greater than or equal to a first level threshold and less than or equal to a second level threshold; when it is determined based on the placement requirements that all buffer units on the same target signal line are inverters, determining that the corresponding number of buffer units is greater than or equal to twice the first level threshold and less than or equal to twice the second level threshold.

[0057] Specifically, regarding the determination of the number of buffer unit levels, the routing strategy of the chip can also be obtained through the IP manual, and the corresponding buffer unit layout rules (and placement requirements) are determined based on the routing strategy; illustratively, let X be the number of clock buffers used, X is a natural number; Y is the number of clock inverters used, Y is a natural number, then:

[0058] If the target signal line only uses the clock buffer, it must meet the following conditions: 1≤X≤4;

[0059] If the target signal line only uses the clock inverter, it must meet the following conditions: 2≤Y≤8, where Y is an even number;

[0060] If a clock buffer and a clock inverter are used at the same time, the total number of buffer units used is Z, where Z is a natural number and satisfies the following conditions: Z=X+Y, 0≤X≤4, 0≤Y≤8, 1≤2X+Y≤8; that is, the first level threshold can be set to 1, and the second level threshold can be set to 4. Through the specific settings of X and Y, the positions of the target signal lines, buffers, and inverters in the layout are further calculated.

[0061] In some specific embodiments, for differential signal lines, as Figure 5 shown, the parallel routing method is adopted for routing, which can maintain the consistency of the routing environment between differential signal lines. In some specific embodiments, after calculating the initial routing nodes (i.e., preliminarily determining the number of buffer unit stages) and determining the preliminary routing method, the line length of the target signal line can be further calculated to check whether it meets the requirements. If it does not meet the requirements, an additional line length is walked in the vertical direction of the trace for compensation, as Figure 6 shown.

[0062] In some embodiments of this embodiment, before the step of respectively placing each layout object in the routing area based on the respective target position parameters to output the chip layout, it further includes: determining the routing priority of each target signal line according to the target skew value corresponding to each delay skew group; wherein, the delay skew group includes a differential signal line group, a critical signal line group, and a general signal line group, the first target skew value corresponding to the differential signal line group is less than the second target skew value corresponding to the critical signal line group, and the second target skew value is less than the third target skew value corresponding to the general signal line group; correspondingly, the step of respectively placing each layout object in the routing area based on the respective target position parameters to output the chip layout includes: combining the respective target position parameters and each routing priority, and respectively placing each layout object in the routing area to output the chip layout.

[0063] Specifically, in this embodiment, according to the segmentation of the delay, the target signal lines can be divided into three categories, from the clock source point to the PHY clock terminal, from the pin of the PHY to the pin of the IO, and from the clock source point through the PHY to the pin of the IO; that is, they can be divided into: differential clock signals (i.e., the above-mentioned differential signal lines), critical matching signals (i.e., the above-mentioned critical signal lines), and general matching signals (i.e., the above-mentioned general signal lines). The stricter the delay skew requirement, the higher the routing priority. In this embodiment, the priority value of the differential signal line group is greater than the priority value of the key signal line group, and the priority value of the critical signal line group is greater than the priority value of the general signal line group; that is, in the overall unrouted stage, the most sufficient routing resources are preferentially used to route the differential signal lines; after completing the routing of the differential signal lines, then the critical signal lines are routed; after completing the routing of the critical signal lines, the general matching signal lines are routed.

[0064] It should be understood that non-differential signal lines include critical signal lines and ordinary signal lines. Thus, in some embodiments, when determining the delay skew groups, the target signal lines can be divided into differential signal line groups and non-differential signal line groups, or the target signal lines can be divided into differential signal line groups, critical signal line groups, and ordinary signal line groups, which is not limited herein. The above two grouping methods do not affect the determination of the placement requirements and routing requirements, nor do they affect the determination of the target signal lines and the position parameters of the buffer units.

[0065] Further, in some embodiments of this embodiment, regarding the setting of the routing method in the routing requirements, such as Figure 7 shown, for the differential signal lines with the most stringent delay skew requirements: use the second-highest metal layer and route them in a parallel routing manner, and add ground wires as shielding wires. For critical signal lines and ordinary matching signal lines: route them using the second-highest metal layer based on the limitation condition of 2 times the line width, and add ground wires as shielding wires. Exemplarily, the above second-highest metal layer can be the seventh and eighth metal layers. Taking 1P10M as an example, there are a total of 10 metal layers, and the top two layers M9 and M10 are not used. The M7 / M8 metal layers are used as the delay skew routing layers. The matching lines are added with shielding, and the ground wires are used as shielding wires. As Figure 8 shown, in some embodiments, for non-differential signal lines, the delay skew requirements are relatively low. In order to match the consistent routing lengths, an S-shaped winding routing method (as shown in the area within the ellipse in the figure) can be used.

[0066] In some embodiments of this embodiment, after the step of respectively placing each layout object in the layout into the routing area based on the respective target position parameters to output the chip layout, it further includes: extracting the parasitic parameters of the chip layout, and determining the actual skew values and actual signal transition times of each delay skew group in the chip layout based on the parasitic parameters; respectively calculating the first differences between each actual skew value and the target skew value corresponding to the chip IP manual; respectively calculating the second differences between each actual signal transition time and the target signal transition time corresponding to the chip IP manual; combining each first difference and each second difference to determine whether the current chip layout meets the actual chip design requirements.

[0067] Specifically, after completing the layout design, parasitic parameters of the chip layout can be extracted using design tools. Through timing commands, delay parameters of each delay skew group wiring and signal transition times of each net can be obtained, and the actual skew value of each group can be calculated. Compare the actual skew value of this delay skew group with the target skew value required in the IP manual. If the actual skew value of this group is less than the target skew value required in the IP manual (that is, the above first difference is greater than zero), it means that the skew value of this delay skew group meets the design requirements of the chip IP manual. Calculate the actual signal transition time of each net corresponding to each delay skew group. Compare this actual signal transition time with the target signal transition time required in the IP manual. If the actual signal transition time of this delay skew group is less than the target signal transition time required in the IP manual (that is, the above second difference is greater than zero), it means that the signal transmission speed of this delay skew group meets the design requirements of the chip IP manual. If it is found based on the above first difference and / or second difference that the skew value and / or signal transition time of the corresponding delay skew group do not meet the corresponding delay skew requirements and / or signal transmission speed requirements, an adjustment strategy can be generated based on the above first difference and / or second difference to adjust the positions of relevant target signal lines and / or buffer units.

[0068] Further, in some specific embodiments, when determining whether the generated chip layout meets the delay skew requirements, visual analysis of the path delay should be performed at different process corners after the wiring is completed, and check whether its actual delay skew value meets the requirements of the manual through a TCL language script. The checking operations include: checking the delay skew value of the differential pair path, checking the delay skew value of the critical data signal path, checking the delay skew value of the ordinary signal path, and checking the clock transition time on all signal paths. Exemplarily, when performing visual analysis, for a 28nm process design, as Figure 9 shown, taking the grouping of pll_ddr_clk_out, ck_dif_0, dx_signals_1 (see label 202) as an example, the result is as Figure 9As shown, the view (see label 201) in the figure covers all process corners. Under different process corners, the measurement signals are high-to-low, low-to-high, high-to-low, and low-to-high (see label 203). According to the requirements of the maximum delay skew (see label 204) and the maximum transition time (see label 206) in the manual, the actual delay skew value (see label 205) and the maximum transition time on the actual path (see label 207) are obtained through a script. For example: The required delay skew for the ck_dif_0 group in the manual is 0.010 ns. Through comprehensive analysis of all process corners, its actual maximum delay skew value is under the process corner ssg_0p81v_125c_cworst, and its delay skew is 0.007 ns, meeting the requirement of 0.010 ns; for the analysis of the rising-edge transition time and the falling-edge transition time, the process corner with the largest transition time is ssg_0p81v_m40c_cworst, and its transition time is 0.019 ns, which also meets the design requirement of 0.083 ns.

[0069] Based on the technical solution of the embodiment of the present application above, determine the layout objects of the layout according to the wiring parameters of the chip IP manual, and determine the wiring area where the layout objects are located; among them, the layout objects include all target signal lines that meet the chip delay skew requirements and the buffer units connected to the target signal lines; based on the preset wiring strategy, determine the target position parameters of each layout object in the wiring area; based on each target position parameter, layout each layout object into the wiring area respectively to output the chip layout. Through the implementation of the solution of the present application, determine the signal lines that meet the delay skew requirements according to the wiring parameters required by the IP manual, and determine the position parameters of the signal lines and the corresponding buffer units based on the preset wiring strategy, that is, determine the routing method of each signal line; then based on the calculated position parameters, use the wiring tool to layout each signal line and the corresponding buffer unit into the corresponding positions of the layout structure to obtain a chip layout that meets the chip design requirements; performing the wiring operation of the chip layout in this way can effectively improve the DDR delay skew requirement efficiency of the chip layout structure and improve the wiring operation efficiency.

[0070] Figure 10 The method in [reference] is a refined wiring method for the chip layout provided by the second embodiment of the present application. This wiring method for the chip layout includes:

[0071] Step 1001: Determine the PHY position parameter and the IO position parameter based on the chip IP manual.

[0072] Step 1002: Combine the PHY position parameter and the IO position parameter to determine all target signal lines that meet the chip delay skew requirements.

[0073] Step 1003: Based on the chip IP manual, determine the demand parameters of each target signal line pair for delay skew respectively, and calculate the number of target signal lines, the total first line width of all target signal lines, the total line spacing between adjacent target signal lines, and the total second line width of all shield lines.

[0074] Step 1004: Combine the number of target signal lines, the total first line width, the total line spacing, and the total second line width to determine the wiring area where the layout object is located.

[0075] Specifically, the layout object includes all target signal lines that meet the chip delay skew requirements and the buffer units connected to the target signal lines.

[0076] Step 1005: According to each demand parameter, determine the delay skew group to which each target signal belongs respectively.

[0077] Specifically, all target signal lines within the same delay skew group meet the delay skew requirements defined by the same target skew value.

[0078] Step 1006: According to the delay skew requirements of the target signal lines in each delay skew group, determine the wiring priority of each target signal line and determine the buffer units to be inserted for each target signal line.

[0079] Specifically, according to the target skew value corresponding to each delay skew group, determine the wiring priority of each target signal line. Based on the buffer unit layout rules corresponding to each delay skew group, determine all buffer units corresponding to each target signal line.

[0080] Step 1007: Based on the preset wiring strategy, determine the placement requirements of the buffer units on each target signal line and determine the routing requirements of the target signal lines in each delay skew group.

[0081] Specifically, in this embodiment, the routing requirements corresponding to the differential signal line group include: all signal lines in the group are routed in parallel, the routing lengths are equal, and shield lines are added on both sides of the routing; the buffer unit is used to divide the target signal line into multiple sub-segments; the routing requirements corresponding to the non-differential signal line group include: the routing lengths of all signal lines in the group are equal, and the lengths of the sub-segments of all signal lines in the group are less than or equal to the preset line length value. In this embodiment, the placement requirements include the first requirement of each target signal line for the delay difference of the up / down flip unit, the second requirement for the signal conversion time difference of the output rising / falling edge, and the driving ability requirement for the buffer unit. The selected buffer unit can be determined in combination with the above placement requirements, and the corresponding buffer unit stages of each target signal line can be determined.

[0082] Step 1008: Combine the priorities, placement requirements, and routing requirements corresponding to each delay skew group, and layout each layout object of the chip layout into the routing area respectively to output the chip layout.

[0083] Specifically, the position parameters of each target signal line and each buffer unit can be calculated in combination with the placement requirements and routing requirements.

[0084] Step 1009: Perform visual analysis on the chip layout to determine whether the current chip layout meets the actual chip design requirements.

[0085] Provide the implementation of this embodiment. First, determine the positions of the PHY and IO based on the requirements of the manual, and leave enough core area between the PHY and IO for placing standard cells and routing (the width of this core area is determined by the number of wirings, the width occupied by wirings and shield lines, and the spacing between wirings); then sort out the matching signal lines, and sort out the start points and end points of each delay skew group according to the manual requirements. Based on the buffer unit layout rules of the IP manual, determine the buffer units, that is, the type of the inserted unit, the number of stages of the inserted unit, and the position of the inserted unit; optimize the selection rules of the buffer units, which can reduce the influence of path delay differences caused by wiring differences, improve the ratio of buffer unit delay to path delay, so as to achieve the effect of reducing the differences in grouped path delay skews. Control the routing behaviors of differential signal lines, key signal lines, and ordinary signal lines, including routing methods, layers, line lengths, and shielding. Use high-level metal routing to reduce the load of differential signal lines, add shield lines to maintain the consistency of the sidewall capacitance of differential signal lines, adopt the shortest routing method to reduce the ratio of routing delay to path delay, and adopt parallel routing to maintain the consistency of the routing environment between differential signal lines. Through delay checking, check whether the delay skews of each group meet the delay requirements in the manual. Through the comprehensive control of the above steps, the DDR delay skew requirement efficiency can be greatly improved. Through the implementation of this embodiment, it is possible to decide how to design buffer positions, routing lengths, etc. according to different project designs, different DDR rates, and different design processes, and improve efficiency while ensuring chip performance, which has broad practical application prospects.

[0086] It should be understood that the magnitudes of the sequence numbers of the steps in this embodiment do not mean the order of execution of the steps. The order of execution of each step should be determined by its function and internal logic, and should not constitute a unique limitation on the implementation process of the embodiments of this application.

[0087] Figure 11 A routing device for a chip layout provided in the third embodiment of this application. This routing device for a chip layout can be applied to the aforementioned routing method for a chip layout. As Figure 11 shown, this routing device for a chip layout mainly includes:

[0088] The first determination module 1101 is configured to determine a layout object based on the routing parameters of the chip and determine the routing area where the layout object is located; wherein, the layout object includes all target signal lines that meet the chip delay skew requirements and buffer units connected to the target signal lines.

[0089] The second determination module 1102 is configured to determine the target position parameters of each layout object in the routing area based on a preset routing strategy.

[0090] The layout output module 1103 is configured to layout each layout object in the routing area respectively based on each target position parameter to output a chip layout.

[0091] In some implementation manners of this embodiment, the routing parameters include PHY position parameters and IO position parameters; the first determination module is specifically configured to: combine the PHY position parameters and the IO position parameters to determine all target signal lines that meet the chip delay skew requirements; wherein, one end of the target signal line is connected to a target IO, and the other end is connected to a PHY; based on the chip IP manual, determine the demand parameters of each target signal line for delay skew respectively; according to each demand parameter, determine the delay skew group to which each target signal belongs respectively; wherein, all target signal lines within the same delay skew group meet the delay skew requirements defined by the same target skew value; based on the buffer unit layout rules corresponding to each delay skew group, determine all buffer units corresponding to each target signal line.

[0092] Further, in some implementation manners of this embodiment, after the first determination module executes the function of combining the PHY position parameters and the IO position parameters to determine all target signal lines that meet the chip delay skew requirements, the first determination module is further specifically configured to: based on the chip IP manual, calculate the number of target signal lines, the total first line width of all target signal lines, the total line spacing between adjacent target signal lines, and the total second line width of all shield lines; combine the number of target signal lines, the total first line width, the total line spacing, and the total second line width to determine the routing area where the layout object is located.

[0093] Further, in some embodiments of this embodiment, the delay skew group includes a differential signal line group and a non-differential signal line group; correspondingly, the second calculation module is specifically configured to: based on a preset routing strategy, determine the placement requirements of buffer units on each target signal line, and determine the routing requirements of target signal lines in each delay skew group; wherein, the routing requirements corresponding to the differential signal line group include: all signal lines in the group are routed in parallel and have equal routing lengths; the buffer unit is used to divide the target signal line into multiple sub-segments; the routing requirements corresponding to the non-differential signal line group include: all signal lines in the group have equal routing lengths, and the lengths of sub-segments of all signal lines in the group are less than or equal to a preset line length value; combining the placement requirements and the routing requirements, determine the target position parameters of each layout object in the routing area.

[0094] Further, in some embodiments of this embodiment, when the second determination module executes the function of combining the placement requirements and the routing requirements to determine the target position parameters of each layout object in the routing area, it is specifically configured to: determine the number of buffer unit stages of each target signal line according to the placement requirements; wherein, the number of buffer unit stages represents the number of buffer units on the same target signal line; the placement requirements include the first requirement for the delay difference of the up / down flip unit of each target signal line, the second requirement for the signal conversion time difference of the output rising / falling edge, and the driving ability requirement for the buffer unit; combining the number of buffer unit stages and the routing requirements, determine the target position parameters of each layout object in the routing area.

[0095] Further, in some embodiments of this embodiment, the types of buffer units include buffers and inverters; correspondingly, when the second determination module executes the function of determining the number of buffer unit stages of each target signal line according to the placement requirements, it is specifically configured to: when it is determined based on the placement requirements that all buffer units on the same target signal line are buffers, determine that the corresponding number of buffer unit stages is greater than or equal to a first stage threshold and less than or equal to a second stage threshold; when it is determined based on the placement requirements that all buffer units on the same target signal line are inverters, determine that the corresponding number of buffer unit stages is greater than or equal to twice the first stage threshold and less than or equal to twice the second stage threshold.

[0096] Further, in some embodiments of this embodiment, the layout output module is further specifically configured to: determine the routing priority of each target signal line according to the target skew value corresponding to each delay skew group; wherein, the delay skew group includes a differential signal line group, a critical signal line group, and a general signal line group, the first target skew value corresponding to the differential signal line group is less than the second target skew value corresponding to the critical signal line group, and the second target skew value is less than the third target skew value corresponding to the general signal line group; combining each target position parameter and each routing priority, layout each layout object into the routing area respectively to output the chip layout.

[0097] Further, in some embodiments of this embodiment, it further includes a layout verification module, and the layout verification module is specifically used for: after outputting the chip layout, extracting the parasitic parameters of the chip layout, and determining the actual skew value and the actual signal transition time of each delay skew group in the chip layout based on the parasitic parameters; respectively calculating the first difference between each actual skew value and the target skew value corresponding to the chip IP manual; respectively calculating the second difference between each actual signal transition time and the target signal transition time corresponding to the chip IP manual; combining each first difference and each second difference to determine whether the current chip layout meets the actual chip design requirements.

[0098] According to the wiring device of the chip layout provided in this embodiment, the layout objects are determined based on the wiring parameters of the chip, and the wiring area where the layout objects are located is determined; wherein, the layout objects include all target signal lines that meet the chip delay skew requirements and the buffer units connected to the target signal lines; based on a preset wiring strategy, the target position parameters of each layout object in the wiring area are determined; based on each target position parameter, each layout object is respectively laid out in the wiring area to output the chip layout. Through the implementation of the solution of this application, the signal lines that meet the delay skew requirements are determined according to the wiring parameters required by the IP manual, and the position parameters of the signal lines and the corresponding buffer units are determined based on a preset wiring strategy, that is, the routing methods of each signal line are determined; then based on the calculated position parameters, the wiring tool is used to layout each signal line and the corresponding buffer unit to the corresponding positions in the layout structure to obtain a chip layout that meets the chip design requirements; by performing the wiring operation of the chip layout in this way, the DDR delay skew requirement efficiency of the chip layout structure can be effectively improved, and the wiring operation efficiency can be improved.

[0099] Figure 12 An electronic device provided in the fourth embodiment of this application. This electronic device can be used to implement the wiring method of the chip layout in the foregoing embodiments, and mainly includes:

[0100] A memory 1201, a processor 1202, and a computer program 1203 stored on the memory 1201 and executable on the processor 1202. The memory 1201 and the processor 1202 are communicatively connected. When the processor 1202 executes the computer program 1203, the methods in the foregoing Embodiment 1 or 2 are implemented. Wherein, the number of processors can be one or more.

[0101] The memory 1201 may be a high-speed random access memory (RAM), or may also be a non-volatile memory, such as a disk memory. The memory 1201 is used to store executable program codes, and the processor 1202 is coupled to the memory 1201.

[0102] Furthermore, an embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium may be disposed in the above-mentioned electronic device, and the computer-readable storage medium may be the memory in the foregoing Figure 8 illustrated embodiment.

[0103] A computer program is stored on the computer-readable storage medium. When the program is executed by a processor, it implements the wiring method of the chip layout in the foregoing embodiment. Further, the computer-readable storage medium includes non-permanent and permanent, non-removable and removable media, and information storage can be implemented by any method and technology. The information may be computer-readable instructions, data structures, program modules, or other data. The computer storage media include, but are not limited to: phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette tapes, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible by a computing device.

[0104] In several embodiments provided by the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other may be through some interfaces. The indirect coupling or communication connection of the device or module may be in an electrical, mechanical or other form.

[0105] The modules described as separate components may or may not be physically separated. The components displayed as modules may or may not be physical modules, that is, they may be located in one place, or may be distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0106] In addition, in each embodiment of the present application, each functional module can be integrated into one processing module, or each module can exist physically alone, or two or more modules can be integrated into one module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of a software functional module.

[0107] If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in each embodiment of the present application. The aforementioned readable storage medium includes: various media such as USB flash drives, mobile hard disks, ROM, RAM, magnetic disks, or optical discs that can store program codes.

[0108] It should be noted that for the foregoing method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the present application is not limited by the described action sequence, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present application.

[0109] In the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0110] The above is the description of the wiring method, device, equipment, and readable storage medium of the chip layout provided by the present application. For those skilled in the art, according to the idea of the embodiments of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A chip layout wiring method, characterized in that: include: Determine a layout object based on the wiring parameters of the chip, and determine a wiring area where the layout object is located; wherein the layout object includes all target signal lines that meet the chip delay skew requirements and buffer units connected to the target signal lines; Based on a preset routing strategy, determining a target position parameter of each of the layout objects in the routing area; Based on each of the target position parameters, each of the layout objects is placed in the wiring area to output a chip layout.

2. The chip layout wiring method according to claim 1, characterized in that: The wiring parameters include PHY position parameters and IO position parameters; The determining of the layout object based on the wiring parameters of the chip includes: In combination with the PHY position parameter and the IO position parameter, all the target signal lines that meet the chip delay skew requirement are determined; wherein one end of the target signal line is connected to the target IO, and the other end is connected to the PHY; Based on the chip IP manual, respectively determine the required parameters of the delay skew of each target signal line pair; According to each of the required parameters, the delay skew group to which each of the target signals belongs is determined respectively; wherein all of the target signal lines in the same delay skew group meet the delay skew requirement defined by the same target skew value; Based on the buffer unit layout rules corresponding to each of the delay skew groups, all of the buffer units corresponding to each of the target signal lines are determined.

3. The chip layout wiring method according to claim 2, characterized in that: After combining the PHY position parameter and the IO position parameter to determine all the target signal lines that meet the chip delay skew requirement, the method further includes: Based on the chip IP manual, calculate the number of the target signal lines, the sum of the first line widths of all the target signal lines, the sum of the line spacings between adjacent target signal lines, and the sum of the second line widths of all shielding lines; The routing area where the layout object is located is determined by combining the number of the target signal lines, the first line width sum, the line spacing sum, and the second line width sum.

4. The chip layout wiring method according to claim 2, characterized in that: The delay skew group includes a differential signal line group and a non-differential signal line group; the target position parameter of each layout object in the wiring area is determined based on a preset wiring strategy, including: Based on the preset wiring strategy, the placement requirements of the buffer unit on each of the target signal lines are determined, and the routing requirements of the target signal lines in each of the delay skew groups are determined; wherein the routing requirements corresponding to the differential signal line group include: all signal lines in the group are routed in parallel, the routing lengths are equal, and shielding lines are added on both sides of the signal lines; the buffer unit is used to divide the target signal line into multiple sub-segments; the routing requirements corresponding to the non-differential signal line group include: the routing lengths of all signal lines in the group are equal, and the lengths of the sub-segments of all signal lines in the group are less than or equal to the preset line length value; In combination with the placement requirements and the routing requirements, target position parameters of each of the layout objects in the wiring area are determined.

5. The chip layout wiring method according to claim 4, characterized in that: Determining the target position parameters of each of the layout objects in the wiring area in combination with the placement requirements and the routing requirements includes: Determine the number of buffer units of each target signal line according to the placement requirements; the number of buffer units represents the number of buffer units on the same target signal line; In combination with the number of buffer unit levels and the routing requirements, target position parameters of each of the layout objects in the routing area are determined.

6. The chip layout wiring method according to claim 5, characterized in that: Types of the buffer unit include buffers and inverters; The step of determining the number of buffer unit levels of each target signal line according to the placement requirement includes: When it is determined based on the placement requirement that all the buffer units on the same target signal line are the buffers, determining that the corresponding buffer unit level is greater than or equal to a first level threshold and less than or equal to a second level threshold; When it is determined based on the placement requirement that all the buffer units on the same target signal line are the inverters, it is determined that the corresponding buffer unit level is greater than or equal to twice the first level threshold and less than or equal to twice the second level threshold.

7. The chip layout wiring method according to claim 2, characterized in that: Before respectively placing each of the layout objects into the wiring area based on each of the target position parameters to output the chip layout, the method further includes: Determine the routing priority of each of the target signal lines according to the target skew values ​​corresponding to each of the delay skew groups; wherein the delay skew group includes a differential signal line group, a key signal line group, and a common signal line group, the first target skew value corresponding to the differential signal line group is smaller than the second target skew value corresponding to the key signal line group, and the second target skew value is smaller than the third target skew value corresponding to the common signal line group; The step of placing each of the layout objects into the wiring area based on each of the target position parameters to output a chip layout comprises: In combination with each of the target position parameters and each of the routing priorities, each of the layout objects is placed in the routing area to output a chip layout.

8. The chip layout wiring method according to any one of claims 1 to 7, characterized in that: After placing each of the layout objects into the wiring area based on each of the target position parameters to output the chip layout, the method further includes: Extracting parasitic parameters of the chip layout, and determining actual skew values ​​and actual signal conversion times of each of the delay skew groups in the chip layout based on the parasitic parameters; Calculate first differences between each of the actual skew values ​​and the target skew value corresponding to the chip IP manual respectively; Calculate the second difference between each of the actual signal conversion time and the target signal conversion time corresponding to the chip IP manual; In combination with each of the first differences and each of the second differences, it is determined whether the chip layout meets actual chip design requirements.

9. A wiring device for a chip layout, characterized in that: include: A first determination module is used to determine a layout object based on the wiring parameters of the chip, and determine a wiring area where the layout object is located; wherein the layout object includes all target signal lines that meet the chip delay skew requirements and buffer units connected to the target signal lines; A second determination module is used to determine the target position parameters of each of the layout objects in the wiring area based on a preset wiring strategy; The layout output module is used to place each of the layout objects into the wiring area based on each of the target position parameters to output the chip layout.

10. An electronic device, characterized in that: The device comprises a memory and a processor, wherein: The processor is used to execute the computer program stored in the memory; When the processor executes the computer program, the steps in the method according to any one of claims 1 to 8 are implemented.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps in the method according to any one of claims 1 to 8 are implemented.

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