Page buffer, method of operating page buffer, memory device, and memory system

Abstract

The embodiment of the invention discloses a page buffer, an operation method of the page buffer, a memory device and a memory system, relates to the field of semiconductors, and can simplify a circuit structure and reduce cost and occupied space. The page buffer includes a plurality of latch circuits. Each latch circuit comprises a latch configuration circuit and a latch transmission circuit. The latch configuration circuit is connected with the first data node and the second data node, and is configured to respectively configure the first data node and the second data node into different logic levels in response to a configuration signal. Wherein the logic levels of the first data node and the second data node are opposite. The latch transmission circuit is connected with the first data node, the second data node and the sensing node, and is configured to respond to a transmission signal, so that the second data node is coupled with the sensing node, and a configuration result of the latch configuration circuit is transmitted to the sensing node.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor technology, and relate to, but are not limited to, a page buffer and an operation method thereof, a memory device, and a memory system. Background Art

[0002] Semiconductor memories can be roughly divided into two categories depending on whether the stored data is retained when power is off; these two categories of semiconductor memories are: volatile memories and non-volatile memories. Volatile memories lose the stored data when power is off, and non-volatile memories retain the stored data when power is off. In non-volatile memories, memory cells are respectively connected to bit lines and word lines, and thus have good random access time characteristics.

[0003] With the improvement of the integration degree of memories, the area occupied by the page buffer in the peripheral circuit of the memory device is limited and there is a need for its area to tend to decrease. Therefore, the number of elements constituting the page buffer also needs to be streamlined. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a page buffer and an operation method thereof, a memory device, and a memory system.

[0005] On the one hand, embodiments of the present application provide a page buffer. The page buffer includes a plurality of latch circuits. Each of the latch circuits includes a latch configuration circuit and a latch transfer circuit. The latch configuration circuit is connected to a first data node and a second data node, and is configured to, in response to a configuration signal, configure the first data node and the second data node to different logic levels respectively, wherein the logic levels of the first data node and the second data node are opposite. The latch transfer circuit is connected to the first data node, the second data node, and a sense node, and is configured to, in response to a transfer signal, couple the second data node to the sense node to transfer the configuration result of the latch configuration circuit to the sense node.

[0006] In some examples, the latch configuration circuit is configured to, in response to a set signal being in an enabled state, set the first data node and the second data node to a first logic level and a second logic level respectively; in response to a reset signal being in an enabled state, initialize the first data node and the second data node to the second logic level and the first logic level respectively. The first logic level is higher than the second logic level.

[0007] The latch transfer circuit is configured to, when the sensing node is at the second logic level, in response to the transfer signal being in the enabled state and the first data node and the second data node being at the second logic level and the first logic level respectively, connect the second data node to the sensing node, and the sensing node changes from the second logic level to the first logic level.

[0008] In some examples, the latch transfer circuit is further configured to, when the sensing node is at the second logic level, in response to the transfer signal being in the enabled state and the first data node and the second data node being at the first logic level and the second logic level respectively, keep the sensing node at the second logic level.

[0009] In some examples, the latch configuration circuit includes a data transfer circuit, a set control circuit, and a reset control circuit. Among them, the data transfer circuit is connected to the power supply voltage node, the first data node, and the second data node, and is configured to make the logic levels of the first data node and the second data node opposite. The set control circuit is connected to the second data node and the ground voltage node, and is configured to receive the set signal and control the connection or disconnection between the second data node and the ground voltage node according to the level of the set signal. The reset control circuit is connected to the first data node and the ground voltage node, and is configured to receive the reset signal and control the connection or disconnection between the first data node and the ground voltage node according to the level of the reset signal.

[0010] In some examples, the data transfer circuit includes a first transistor and a second transistor. The control electrode of the first transistor is connected to the first data node, the first electrode of the first transistor is connected to the power supply voltage node, and the second electrode of the first transistor is connected to the second data node. The control electrode of the second transistor is connected to the second data node, the first electrode of the second transistor is connected to the power supply voltage node, and the second electrode of the second transistor is connected to the first data node.

[0011] In some examples, the set control circuit includes a third transistor. The control electrode of the third transistor receives the set signal, the first electrode of the third transistor is connected to the ground voltage node, and the second electrode of the third transistor is connected to the second data node. The reset control circuit includes a fourth transistor. The control electrode of the fourth transistor receives the reset signal, the first electrode of the fourth transistor is connected to the ground voltage node, and the second electrode of the fourth transistor is connected to the first data node.

[0012] In some examples, the latch transfer circuit includes a fifth transistor and a sixth transistor connected in series; the fifth transistor and the sixth transistor are P-type transistors.

[0013] In some examples, the control electrode of the fifth transistor is connected to the first data node, the second electrode of the fifth transistor is connected to the second data node, and the first electrode of the fifth transistor is connected to the second electrode of the sixth transistor. The control electrode of the sixth transistor receives the transfer signal, and the first electrode of the sixth transistor is connected to the sense node.

[0014] In some examples, the latch circuit further includes a voltage stabilizing circuit. The voltage stabilizing circuit is connected to the first data node and the second data node, and is configured to stabilize the voltage difference between the first data node and the second data node.

[0015] In some examples, the voltage stabilizing circuit includes a capacitor. The first plate of the capacitor is connected to the first data node, and the second plate of the capacitor is connected to the second data node.

[0016] In some examples, the voltage stabilizing circuit includes a seventh transistor. The control electrode of the seventh transistor is connected to the second data node, and the first and second electrodes of the seventh transistor are both connected to the first data node.

[0017] In some examples, the page buffer further includes a bit line control circuit and a bit line discharge circuit. The bit line control circuit is connected to a power supply voltage node, a bit line, and the sense node, and is configured to control the potential level of the sense node based on the current level of the bit line during a sensing operation. The bit line discharge circuit is connected between the bit line and a ground voltage node, and is configured to discharge the potential level of the bit line in response to a discharge control signal.

[0018] In this application, the latch configuration circuit in the page buffer is connected to the first data node and the second data node, and the connection or disconnection between the latch transfer circuit and the sense node is controlled according to the logic levels of the first data node and the second data node. In this way, without connecting the latch configuration circuit and the latch transfer circuit to the ground voltage node, not only the grounding line structure is reduced. Moreover, not directly using an inverter also reduces the number of electronic components (such as transistors), reducing the manufacturing cost of the page buffer and the occupied space of the page buffer in the memory device; especially in the case where the memory device includes a page buffer group or a page buffer for driving a multi-level memory cell type, the manufacturing cost and occupied space of the page buffer can be significantly reduced.

[0019] Moreover, by means of a simplified circuit structure, the complexity of the signal transmission path between the page buffer and the sensing node is reduced, and the loss during the transmission of the level signal is reduced, thereby improving the performance of the memory device as a whole.

[0020] On the other hand, the present application provides a memory device. The memory device includes a memory cell array and a plurality of page buffers as provided in any of the above examples. The memory cell array is connected to a plurality of bit lines. Each of the page buffers is connected to one of the bit lines and is configured to perform a sensing operation based on the current level of the bit line.

[0021] The beneficial effects achieved by the memory device provided in this example are the same as those of the page buffer provided in any of the above examples, and will not be elaborated here.

[0022] On yet another aspect, the present application provides a memory system. The memory system includes one or more memory devices as provided in the above aspect and a memory controller. The memory controller is connected to the memory device and is configured to control the memory device.

[0023] The beneficial effects achieved by the memory system provided in this example are the same as those of the memory device provided in the above example, and will not be elaborated here.

[0024] On still another aspect, the present application provides an operation method for a page buffer. The page buffer includes a plurality of latch circuits, and each latch circuit includes a latch configuration circuit disposed between a first data node and a second data node and a latch transmission circuit connected to the first data node, the second data node, and a sensing node. The operation method includes:

[0025] In a reset stage, in response to the enabling state of the reset signal, the latch configuration circuit initializes the first data node and the second data node to a second logic level and a first logic level, respectively. The first logic level is higher than the second logic level.

[0026] In a read stage after the reset stage, the sensing node is at the second logic level; and, in response to the enabling state of the transmission signal, the latch transmission circuit connects the second data node to the sensing node and transmits the first logic level of the second data node to the sensing node. The sensing node changes from the second logic level to the first logic level.

[0027] In some examples, the operation method further includes: in a setting stage, in response to the enabling state of the setting signal, the latch configuration circuit sets the first data node and the second data node to the first logic level and the second logic level, respectively.

[0028] In the reading stage after the setting stage, the sensing node is at the second logic level; and, the latch transfer circuit disconnects the second data node from the sensing node, and the level of the sensing node remains at the second logic level.

[0029] The operation method of the page buffer provided by this application includes two processes. One is based on the level signals stored in the first data node and the second data node during the reset stage, and in the reading stage, the latch transfer circuit is connected to the sensing node through the enabling state of the transmission signal, causing the level of the sensing node to change. The other is based on the level signals stored in the first data node and the second data node during the setting stage. In the reading stage, even in response to the enabling state of the transmission signal, the latch transfer circuit is not connected to the sensing node, and the level of the sensing node is maintained. These two processes are based on different page buffers including multiple latch circuits. Different latch circuits may have different states during the same time period, which is characterized in that the data read in the reading stage of the page buffer operation process can be the data stored in the setting stage, or the data stored in the reset stage. In this way, in the reading stage, the latch circuits of different page buffers have different effects on the level of the sensing node, so that different data of different page buffers can be obtained through the sensing node. The circuit structure of the page buffer provided by this application can simultaneously read data in different states of the storage unit. Description of the Drawings

[0030] In the drawings, similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The drawings generally illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0031] Figure 1 Schematic structural diagram of an electronic system provided by an embodiment of this application;

[0032] Figure 2 Schematic structural diagram of a memory card provided by an embodiment of this application;

[0033] Figure 3 Schematic structural diagram of a solid state drive (SSD, Solid State Disk) provided by an embodiment of this application;

[0034] Figure 4 and Figure 5 Schematic structural diagram of a memory including a storage cell array and a peripheral circuit provided by an embodiment of this application;

[0035] Figure 6 Schematic structural diagram of a memory including a page buffer group provided by an embodiment of this application;

[0036] Figure 7Schematic diagram of a page buffer provided for an exemplary embodiment;

[0037] Figure 8 Schematic of a page buffer provided for an embodiment of the present application Figure 1 ;

[0038] Figure 9 Schematic of a page buffer provided for an embodiment of the present application Figure 2 ;

[0039] Figure 10 Schematic of a latch circuit of a page buffer provided for an embodiment of the present application Figure 1 ;

[0040] Figure 11 Schematic of a latch circuit of a page buffer provided for an embodiment of the present application Figure 2 ;

[0041] Figure 12 Schematic of a partial logic circuit of a latch circuit of a page buffer provided for an embodiment of the present application Figure 1 ;

[0042] Figure 13 Schematic of a partial logic circuit of a latch circuit of a page buffer provided for an embodiment of the present application Figure 2 ;

[0043] Figure 14 Schematic of a partial logic circuit of a latch circuit of a page buffer provided for an embodiment of the present application Figure 3 ;

[0044] Figure 15 Schematic of a partial logic circuit of a latch circuit of a page buffer provided for an embodiment of the present application Figure 4 ;

[0045] Figure 16 Schematic diagram of the logic circuit of a latch circuit of a page buffer provided for an embodiment of the present application;

[0046] Figure 17 Schematic of the structure of a voltage stabilizing circuit of a page buffer provided for an embodiment of the present application Figure 1 ;

[0047] Figure 18 Schematic of the logic circuit of a voltage stabilizing circuit of a page buffer provided for an embodiment of the present application Figure 1 ;

[0048] Figure 19 Schematic of the logic circuit of a voltage stabilizing circuit of a page buffer provided for an embodiment of the present application Figure 2 ;

[0049] Figure 20Schematic diagram of the logic circuit of a bit line control circuit and a bit line discharge circuit for a page buffer provided by an embodiment of the present application;

[0050] Figure 21 Schematic diagram of the logic circuit of a page buffer provided by an embodiment of the present application;

[0051] Figure 22A Timing of the latch circuit of a page buffer provided by an embodiment of the present application Figure 1 ;

[0052] Figure 22B Timing of the latch circuit of a page buffer provided by an embodiment of the present application Figure 2 ;

[0053] Figure 23 is Figure 22A Flowchart of an operation method of a page buffer provided;

[0054] Figure 24 is Figure 22B Flowchart of an operation method of a page buffer provided. Detailed implementation manners

[0055] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant attached drawings. The preferred embodiments of the present application are given in the attached drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0057] The "first", "second" and similar terms used in the present application do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "one" or "the" do not denote a quantity limitation, but mean that there is at least one. The terms such as "comprising" or "including" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0058] To thoroughly understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this application. The preferred embodiments of this application are described in detail below. However, in addition to these detailed descriptions, this application may have other implementation manners.

[0059] As Figure 1 shown, an embodiment of this application illustrates an electronic system 10. By way of example, the electronic system 10 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or a system of any other suitable electronic device having a memory device 32.

[0060] Please continue to refer to Figure 1 , the electronic system 10 may include a host 20 and a memory system 30.

[0061] The host 20 may be a processor of the electronic device (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP))). The host 20 may be configured to send data to the memory system 30 or receive data from the memory system 30.

[0062] The memory system 30 includes a memory controller 31 and one or more memory devices 32, as well as other integrated circuit structures for signal transmission. Among them, the memory controller 31 and one or more memory devices 32 may be integrated and packaged in the same storage device. In this way, it is beneficial to apply the memory system 30 to different types of terminal electronic products.

[0063] By way of example, the types of storage devices integrating the memory controller 31 and one or more memory devices 32 include: universal flash storage (UFS) or embedded multimedia card (eMMC), and other types of storage devices.

[0064] There are various ways of integrating the integrated circuit of this storage device. For example, it may be a memory card 40 formed by integrating a single memory device 32 and a memory controller 31 (as Figure 2As shown), or it can be an SSD 50 formed by integrating multiple memory devices 32 and a memory controller 31 together (as Figure 3 shown).

[0065] Exemplarily, the memory card 40 may include one or more types of storage devices such as a Personal Computer Memory Card International Association (PC) card, a CompactFlash (CF) card, a Smart Media (SM) card, a Memory Stick, a Multi-Media Card (MMC (Multi-Media Card), RS-MMC (Reduced-Size MMC), MMC micro), a Secure Digital (SD) card (SD, miniSD, microSD, Secure Digital High Capacity (SDHC)), and a Universal Flash Storage (UFS).

[0066] Wherein, please continue to refer to Figure 2 , the memory card 40 further includes a memory card connector 41. The memory card connector 41 is configured to couple the memory card 40 to a host (e.g., Figure 1 the host 20 in). For example, the memory card connector 41 includes gold fingers.

[0067] Alternatively, please continue to refer to Figure 3 , the SSD 50 further includes an SSD connector 51. The SSD connector 51 is configured to couple the SSD 50 to a host (e.g., Figure 1 the host 20 in). For example, the SSD connector 51 includes gold fingers.

[0068] It can be understood that the storage capacity and / or operating speed of the SSD 50 is greater than that of the memory card 40.

[0069] The memory controller 31 integrated in the same storage device is coupled to the memory device 32 (and the host 20), and the memory controller 31 is configured to control the memory device 32.

[0070] Exemplarily, the memory controller 31 can be designed to operate in a low-duty-cycle environment. For example, it can be used to operate in a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive; or in other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. Again exemplarily, the memory controller 31 can be designed to operate in a high-duty-cycle environment, for example, to operate in a solid-state drive (SSD) or an embedded Multi-Media Card (eMMC). Among them, the SSD or eMMC can be used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0071] Furthermore, the memory controller 31 can manage the data in the memory device 32 and communicate with the host 20. The memory controller 31 can be configured to control operations such as reading, erasing, and programming of the memory device 32; it can also be configured to manage various functions regarding the data stored in or to be stored in the memory device 32, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.; it can also be configured to process the error checking and correction (ECC) of the data read from or written to the memory device 32.

[0072] In addition, the memory controller 31 can also perform any other suitable functions, such as formatting the memory device 32, or communicating with external devices according to a specific communication protocol (for example, Figure 1communicate with the host 20. For example, the memory controller 31 can communicate with the host 20 through at least one of various interface protocols. Among them, the interface protocols include one or more of the USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, Peripheral Component Interconnect Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Development Equipment (IDE) protocol, Firewire protocol, etc.

[0073] The above memory device 32 can include, but is not limited to, one or more of NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Magnetoresistive Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), Nano Random Access Memory (NRAM), etc.

[0074] Based on the above description, in this application, the memory device 32 is a semiconductor memory. For example, a solid-state electronic device (such as a NAND-type memory) for storing data information made by semiconductor integrated circuit technology is used as an example for the subsequent embodiments. The subsequent examples of this application do not limit the specific internal structure of the memory device 32.

[0075] It can be understood that, in order to facilitate the distinction of the adaptive adjustments made by the memory device 32 for different scenarios, for example, based on the various structures of the memory device 32 in the examples described above, the memory device (such as a NAND-type memory) provided in the subsequent examples of the present application will be described with the memory device 60.

[0076] As Figure 4 shown, in some embodiments, the memory device 60 may include a memory cell array 61 and a peripheral circuit 62 coupled to the memory cell array 61 and other circuit structures.

[0077] The memory cell array 61 is connected to a plurality of bit lines. Exemplarily, the memory cell array 61 may be a NAND flash memory cell array. For example, the memory cell array 61 is a circuit structure arranged in the form of an array of NAND memory strings 611. Each NAND memory string 611 extends vertically on the substrate. Exemplarily, each NAND memory string 611 may include a plurality of memory cells (cells) coupled in series and vertically stacked. Among them, each memory cell transmits signals in a state of maintaining a continuous analog value (for example, voltage or charge), and the analog value of the memory cell depends on the number of electrons captured in the memory cell region.

[0078] Exemplarily, each memory cell in the memory cell array 61 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor. The present application does not limit this.

[0079] In some examples, the storage type of the above-mentioned memory cells includes any one of single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC).

[0080] Exemplarily, each memory cell of the SLC can store one bit of data and has two possible first storage states and second storage states. Among them, the first storage state (for example, "0") corresponds to a first threshold voltage range, and the second storage state (for example, "1") corresponds to a second threshold voltage range. In this way, the second storage state (for example, "1") is used as the erased state, and the first storage state (for example, "0") is used as the programmed state.

[0081] As another example, each memory cell of the MLC can store two-bit data and has four possible first storage states, second storage states, third storage states, and fourth storage states. Among them, the first storage state (e.g., "11") corresponds to a first threshold voltage range, the second storage state (e.g., "01") corresponds to a second threshold voltage range, the third storage state (e.g., "10") corresponds to a third threshold voltage range, and the fourth storage state (e.g., "00") corresponds to a fourth threshold voltage range. In this way, the fourth storage state (e.g., "00") is used as the erased state, and the first storage state (e.g., "11"), the second storage state (e.g., "01"), and the third storage state (e.g., "10") are used as the programmed states.

[0082] Similarly, each memory cell of the TLC can store three-bit data and has eight possible storage states. The eight storage states respectively correspond to eight threshold voltage ranges, and the specific storage states are not elaborated here. Among them, one of the eight threshold voltage ranges is used as the erased state (e.g., "111"), and the remaining seven threshold voltage ranges are used as the programmed states. Also, each memory cell of the QLC can store four-bit data and has sixteen possible storage states. The sixteen storage states respectively correspond to sixteen threshold voltage ranges, and the specific storage states are not elaborated here. Among them, one of the sixteen threshold voltage ranges is used as the erased state (e.g., "1111"), and the remaining fifteen threshold voltage ranges are used as the programmed states.

[0083] Please continue to refer to Figure 4 , the above-mentioned peripheral circuit 62 can be coupled to the memory cell array 61 through a bit line (Bit Line, BL), a word line (Word Line, WL), a source line, a source select gate (Source Select Gate, SSG), and a drain select gate (Drain Select Gate, DSG). The peripheral circuit 62 is configured to apply a voltage signal and / or a current signal to each target memory cell and sense the voltage signal and / or the current signal from each target memory cell by means of the bit line BL, the word line WL, the source SL, the source select gate SSG, or the drain select gate DSG, etc., so as to implement the logical operations (such as programming, reading, or writing operations) of the memory cell array 61.

[0084] Exemplarily, the peripheral circuit 62 includes various types of circuit structures formed by metal-oxide-semiconductor (Metal-Oxide-Semiconductor, MOS) transistors. For example, as Figure 5As shown, the peripheral circuit 62 may include various circuit structures such as a row decoder / word line driver 620, a page buffer (PB) / sense amplifier 621, a column decoder / bit line driver 623, a voltage generator 624, a control logic unit 625, a latch circuit 626, an interface 627, and a data bus 628.

[0085] Furthermore, as Figure 6 shown, the peripheral circuit 62 may include a page buffer group composed of multiple page buffers 621. The page buffer group may be coupled to the memory cell array 61 via multiple bit lines (BL1 to BLk). One page buffer 621 is coupled to the memory cell array 61 via one bit line. For example, as Figure 6 shown, multiple page buffers 621 may be respectively coupled to the memory cell array 61 via corresponding bit lines BL1 to BLk.

[0086] Based on the above, in some embodiments, the page buffer 621 of the peripheral circuit 62 includes multiple latches 6211. By way of example, as Figure 7 shown, the page buffer 621 of the peripheral circuit 62 includes at least five latches 6211.

[0087] Among them, the latch 6211 includes two inverters 6212 connected end to end, a data transfer circuit 6213, and other electronic components. The two inverters 6212 include at least four transistors. Thus, in the case where the page buffer 621 includes multiple latches 6211, especially for TLC and QLC type memory cells, the page buffer 621 needs to set a larger number of latches 6211 to implement data reading or programming, and then the number of transistors in each page buffer 621 is larger. Furthermore, in the case where the peripheral circuit 62 implements logic (such as programming, reading, or writing) operations through a page buffer group (see Figure 6 ), the number of electronic components of multiple page buffers 621 is superimposed, resulting in a sharp increase in the space occupied by the peripheral circuit 62 in the memory device 60 (for example, occupying nearly 1 / 3 of the space inside the memory device 60), and reducing the energy efficiency ratio of the memory device 60.

[0088] To solve the above problems, as Figures 8 - 21 shown, the present application provides a structure of a page buffer 622, which simplifies the circuit structure and reduces the occupied space and manufacturing cost of the page buffer 622 in the memory device 60.

[0089] In some embodiments, as Figure 8 shown, the page buffer 622 includes a bit line control circuit 6221, a bit line discharge circuit 6222, and multiple latch circuits 6223.

[0090] The bit line control circuit 6221 is connected to the power supply voltage node VDD, the bit line BL, and the sense node SO, and is configured to control the potential level of the sense node SO based on the current level of the bit line BL during the sensing operation. For example, it can be determined whether to charge the bit line according to the programmed verification result latched in the latch circuit 6223. For example, when the programmed verification result indicates that the memory cell reaches the target threshold voltage, the bit line BL coupled to the memory cell can be charged to the programming-forbidden bit line voltage (e.g., VDD) through the bit line control circuit 6221 to prohibit programming; when the programmed verification result indicates that the memory cell does not reach the target threshold voltage, the bit line BL coupled to the memory cell can be adjusted to the normal programming bit line voltage (e.g., VSS) or the bit line BL forced voltage (greater than VSS and less than VDD) through the bit line control circuit 6221 to continue programming.

[0091] The bit line discharge circuit 6222 is connected between the bit line BL and the ground voltage node GND, and is configured to discharge the potential level of the bit line BL in response to a discharge control signal (e.g., VDD).

[0092] It can be understood that the level of the power supply voltage node VDD above is VDD, and the level of the ground voltage node GND is VSS. The identification symbols of the "nodes" adopted in the examples of this application only exemplarily characterize the characteristics of the level signals transmitted by the nodes, and do not limit the magnitude of the actual level signals transmitted by the nodes.

[0093] Multiple latch circuits 6223 are all connected to the sense node SO, and realize the charging and discharging of the level of the sense node SO under the drive of the bit line control circuit 6221 and the bit line discharge circuit 6222. For example, as Figure 9 shown in the page buffer 622, the number of the multiple latch circuits 6223 is six. The six latch circuits 6223 can include a sense latch (SLatch), a low voltage latch (LVT Latch), three data latches (DLatch), and a cache latch (C Latch).

[0094] Among them, the sense latch S Latch can be used to store the prohibition information and the verification information from the verification operation.

[0095] The cache latch C Latch is used for data exchange with the outside. For example, first transfer the data from the outside to the cache latch C Latch, and then transfer it to the sense latch SLatch through the cache latch C Latch. Another example is to transfer the data in the sense latch S Latch to the cache latch C Latch, and then transfer it to the outside through the cache latch C Latch. The outside can be a memory controller 31 or a host 20, etc. Another example is that the cache latch C Latch can also be used for other functions, such as for temporarily storing verification information.

[0096] The data latch D Latch can be used to latch the data of a specified page of the storage unit.

[0097] The low-voltage latch LVT Latch can be used to store prohibition information and the verified information adjusted from the verification operation.

[0098] In some examples, the storage types based on the storage unit include storage types such as SLC, MLC, TLC, and QLC.

[0099] If the storage unit is SLC, the latch circuit 6223 in the page buffer 622 may include a cache latch. The cache latch is used to latch the data of the storage unit.

[0100] If the storage unit is MLC, in addition to the cache latch C Latch, the page buffer 622 may also include a data latch D Latch. Among them, the data latch D Latch can be used to latch the lower-page data of the storage unit, and the cache latch C Latch can be used to latch the upper-page data of the storage unit.

[0101] If the storage unit is TLC, in addition to the cache latch C Latch, the page buffer 622 may also include two data latches D Latch. Among them, one data latch D Latch can be used to latch the lower-page data of the storage unit, and the other data latch D Latch can be used to latch the middle-page data of the storage unit, and the cache latch C Latch can be used to latch the upper-page data of the storage unit.

[0102] By analogy, if the storage unit is nLC, the number of data latches D Latch in the page buffer 622 can be (n - 1), and the (n - 1) data latches D Latch respectively latch the data of the specified page of the storage unit, where n is a positive integer greater than 0.

[0103] It can be understood that the sense latch S Latch, the low-voltage latch LVT Latch, the data latch DLatch, and the cache latch C Latch include sub-circuits with some identical structures, and these sub-circuits with identical structures can achieve complete data transmission. Among them, the sense latch S Latch and the cache latch C Latch also include additional electronic components to assist in the realization of data transmission, and the structure of the additional electronic components is not specifically limited in this application. In the subsequent examples, some identical circuit structures of different types of latch circuits 6223 are described. Therefore, the latch circuits 6223 mentioned in the subsequent examples do not limit the types of the latch circuits 6223.

[0104] In some embodiments, as Figure 10 shown, each latch circuit 6223 includes a latch configuration circuit 6201 and a latch transmission circuit 6202.

[0105] The latch configuration circuit 6201 is connected to the first data node Data and the second data node Data_bar, and is configured to, in response to a configuration signal, configure the first data node Data and the second data node Data_bar to different logic levels respectively, where the logic levels of the first data node Data and the second data node Data_bar are opposite.

[0106] In some embodiments, as Figure 10 shown, the "configuration signal" includes a set signal set transmitted from the Set terminal and a reset signal rst transmitted from the Rst terminal.

[0107] Moreover, the logic level of the first data node Data is a high level, and the logic level of the second data node Data_bar is a low level. Or, the logic level of the first data node Data is a low level, and the logic level of the second data node Data_bar is a high level. In different timing stages of the circuit, the logic levels of the first data node Data and the second data node Data_bar are different, as long as the logic levels of the first data node Data and the second data node Data_bar are opposite, which will be specifically described in the subsequent operation method.

[0108] It can be understood that the "high level" and the "low level" are two signals of the relative magnitudes of the level signals.

[0109] The latch transmission circuit 6202 is connected to the first data node Data, the second data node Data_bar, and the sense node SO, and is configured to, in response to a transmission signal rd, couple the second data node Data_bar to the sense node SO to transmit the configuration result of the latch configuration circuit 6201 to the sense node SO.

[0110] It should be noted that the "configuration result of the latch configuration circuit 6201" is a signal that controls the connection or disconnection between the latch transfer circuit 6202 and the sensing node SO based on the enabling state of the transmission signal rd, and further determines whether the logic level of the second data node Data_bar can be transmitted to the sensing node SO, thereby affecting the magnitude of the logic level of the sensing node SO. For example, when the logic level of the first data node Data is high and the logic level of the second data node Data_bar is low, if the latch transfer circuit 6202 is controlled to be disconnected from the sensing node SO, the logic level of the second data node Data_bar cannot be transmitted to the sensing node SO, and the logic level of the sensing node SO remains unchanged. Or, when the transmission signal rd is enabled, if the logic level of the first data node Data is low and the logic level of the second data node Data_bar is high, and the latch transfer circuit 6202 is controlled to be connected to the sensing node SO, the logic level of the second data node Data_bar can be transmitted to the sensing node SO, and the logic level of the sensing node SO changes to the high level of the second data node Data_bar.

[0111] The above-mentioned transmission signal rd is the signal transmitted from the Rd terminal. For the convenience of understanding, in the examples provided in this application, the identification of the signal terminal and the identification symbol of the signal it transmits are distinguished by the capitalization of the first letter. Similarly, in the subsequent examples, the identification of signals such as the setting signal set, the reset signal rst, the prech_sel_en signal, the prech_all_en signal, and the data setting signal rst_sa_latch (referred to Figure 16 and Figure 20 corresponding) is mentioned.

[0112] In this application, the latch configuration circuit 6201 in the page buffer 622 is connected to the first data node Data and the second data node Data_bar, and the connection or disconnection between the latch transfer circuit 6202 and the sensing node SO is controlled according to the logic levels of the first data node Data and the second data node Data_bar.

[0113] In this way, without connecting the latch configuration circuit 6201, the latch transfer circuit 6202 to the ground voltage node GND (such as Figure 7 the inverter 6212 is grounded and the data transfer circuit 6213 is grounded in ), not only the grounding line structure is reduced; moreover, the number of electronic components (such as transistors) is also reduced without using the inverter 6212, reducing the manufacturing cost of the page buffer 622 and the occupied space in the memory device 60; especially when the memory device 60 includes a page buffer group or a page buffer 622 for driving a multi-level memory cell type, the manufacturing cost and occupied space of the page buffer 622 can be significantly reduced.

[0114] Moreover, through a simplified circuit structure, the complexity of the signal transmission path between the page buffer 622 and the sensing node SO is reduced, and the loss during the transmission of the level signal is reduced, thereby improving the performance of the memory device 60 as a whole.

[0115] In addition, with the area occupied by the page buffer 622 remaining unchanged, a larger number of latch circuits 6223 can be provided (for example, by adding data latch circuits 6223) to meet the requirements of the memory device 60 for higher-bit data, so that more bits of data information can be stored, which is beneficial to improving the bit density of the memory device 60.

[0116] In some examples, please continue to refer to Figure 10 , the latch configuration circuit 6201 is configured to set the first data node Data and the second data node Data_bar to the first logic level and the second logic level respectively in response to the set signal set being in the enabled state; in response to the reset signal rst being in the enabled state, the first data node Data and the second data node Data_bar are initialized to the second logic level and the first logic level respectively. The first logic level is higher than the second logic level.

[0117] It can be understood that the first logic level is a high level and the second logic level is a low level. For example, the first logic level is VDD. The second logic level is VSS.

[0118] Please continue to refer to Figure 10 , the latch transmission circuit 6202 is configured to connect the second data node Data_bar to the sensing node SO when the sensing node SO is at the second logic level, in response to the transmission signal rd being in the enabled state and the first data node Data and the second data node Data_bar being at the second logic level and the first logic level respectively, and the sensing node SO changes from the second logic level to the first logic level.

[0119] Alternatively, the latch transmission circuit 6202 is further configured to keep the sensing node SO at the second logic level when the sensing node SO is at the second logic level, in response to the transmission signal rd being in the enabled state and the first data node Data and the second data node Data_bar being at the first logic level and the second logic level respectively.

[0120] The above latch control circuit 6201 and latch transmission circuit 6202 charge or discharge the level of the sensing node SO in response to different signals at different stages of the driving process of the page buffer 622, and the specific signal transmission process will be described in the operation method of the page buffer 622 in subsequent examples.

[0121] In some examples, such asFigure 11 As shown, the latch configuration circuit 6201 includes a data transmission circuit 6203, a set control circuit 6204, and a reset control circuit 6205.

[0122] Among them, the data transmission circuit 6203 is connected to the power supply voltage node VDD, the first data node Data, and the second data node Data_bar, and is configured to make the logic levels of the first data node Data and the second data node Data_bar opposite.

[0123] The set control circuit 6204 is connected to the second data node Data_bar and the ground voltage node GND, and is configured to receive the set signal set and control the connection or disconnection between the second data node Data_bar and the ground voltage node GND according to the level of the set signal set.

[0124] The reset control circuit 6205 is connected to the first data node Data and the ground voltage node GND, and is configured to receive the reset signal and control the connection or disconnection between the first data node Data and the ground voltage node GND according to the level of the reset signal rst.

[0125] In some examples, as Figure 12 shown, the data transmission circuit 6203 includes a first transistor T1 and a second transistor T2.

[0126] The control electrode of the first transistor T1 is connected to the first data node Data, the first pole of the first transistor T1 is connected to the power supply voltage node VDD, and the second pole of the first transistor T1 is connected to the second data node Data_bar. The control electrode of the second transistor T2 is connected to the second data node Data_bar, the first pole of the second transistor T2 is connected to the power supply voltage node VDD, and the second pole of the second transistor T2 is connected to the first data node Data.

[0127] For example, please continue to refer to Figure 12 , the first transistor T1 and the second transistor T2 are P-type transistors.

[0128] In some examples, as Figure 13 shown, the set control circuit 6204 includes a third transistor T3. The control electrode of the third transistor T3 receives the set signal set, the first pole of the third transistor T3 is connected to the ground voltage node GND, and the second pole of the third transistor T3 is connected to the second data node Data_bar.

[0129] Such as Figure 14As shown, the reset control circuit 6205 includes a fourth transistor T4. The control electrode of the fourth transistor T4 receives a reset signal rst. The first electrode of the fourth transistor T4 is connected to a ground voltage node GND, and the second electrode of the fourth transistor T4 is connected to a first data node Data.

[0130] In some examples, as Figure 15 shown, the latch transfer circuit 6202 includes a fifth transistor T5 and a sixth transistor T6 connected in series.

[0131] The control electrode of the fifth transistor T5 is connected to the first data node Data. The second electrode of the fifth transistor T5 is connected to a second data node Data_bar. The first electrode of the fifth transistor T5 is connected to the second electrode of the sixth transistor T6. The control electrode of the sixth transistor T6 receives a transfer signal rd, and the first electrode of the sixth transistor T6 is connected to a sense node SO.

[0132] For examples, please continue to refer to Figure 15 , the fifth transistor T5 and the sixth transistor T6 are P-type transistors. In this way, considering the property that P-type transistors conduct under the control of low-level signals. To reduce the problem that the level signal received by the control electrode of the transistor cannot turn on the transistor or the turn-on degree of the transistor is poor due to the loss of the level signal during transmission in the circuit signal line (i.e., the relationship between the voltage difference between the control electrode and the first electrode and the threshold voltage characterizes the turn-on degree of the transistor), in the circuit structure for transmitting the level signal between the latch circuit 6223 and the sense node SO, using P-type transistors can reduce the probability of the adverse effects caused by this problem.

[0133] For examples, at least two latch circuits 6223 share one latch transfer circuit 6202. For example, two latch circuits 6223 share one latch transfer circuit 6202. In this way, the area occupied by the structure of the page buffer 622 is smaller, and the area of the memory device 60 can be further reduced, which is beneficial to achieving the high integration and small size of the memory device 60.

[0134] Based on the structure of the latch circuit 6223 provided by the above examples, as Figure 16 shown, the latch circuit 6223 includes 6 transistors. Combining with Figure 7 the structure of the latch 6211 shown, the latch circuit 6223 of the present application not only reduces two transistors, but also reduces the cost of the page buffer 622 and the space occupied in the memory device 60. Among them, reducing the transistors of two inverters reduces the peak current generated by transmitting signals through multiple transistors through the two inverters, and improves the signal transmission stability of the page buffer 622.

[0135] Moreover, while implementing the charging and discharging operation functions of the sensing node SO, the stability of the line transmission level signal between the latch circuit 6223 and the sensing node SO is improved, the accuracy of the sensing signal of the sensing node SO is improved, and thus the performance of the page buffer 622 is improved.

[0136] In some examples, as Figures 17 - 19 shown, the latch circuit 6223 further includes a voltage stabilizing circuit 6206. As Figure 17 shown, the voltage stabilizing circuit 6206 is connected to the first data node Data and the second data node Data_bar, and is configured to stabilize the voltage difference between the first data node Data and the second data node Data_bar.

[0137] Exemplarily, as Figure 18 shown, the voltage stabilizing circuit 6206 includes a capacitor C1. The first plate of the capacitor C1 is connected to the first data node Data, and the second plate of the capacitor C2 is connected to the second data node Data_bar. In this way, under the bootstrap action of the capacitor C1, the voltage difference between the first plate and the second plate is maintained stable, and further the voltage difference between the first data node Data and the second data node Data_bar is stabilized, so that the voltage difference between the control electrode and the first electrode of the fifth transistor T5 is stable, that is, the signal flowing through the fifth transistor T5 is ensured to be stable.

[0138] Another example is that, as Figure 19 shown, the voltage stabilizing circuit 6206 includes a seventh transistor T7. The control electrode of the seventh transistor T7 is connected to the second data node Data_bar, and the first electrode and the second electrode of the seventh transistor T7 are both connected to the first data node Data. In this way, the first electrode and the second electrode of the seventh transistor T7 are connected to the same node (i.e., the first data node Data). Whether the seventh transistor T7 is turned on or off under the control of the level signal of the second data node Data_bar, the level of the first data node Data can be maintained stable. Furthermore, the opening degree of the first transistor T1 controlled by the level of the first data node Data is stable, and the level of the second data node Data_bar is stable. Thus, the voltage difference between the control electrode and the first electrode of the fifth transistor T5 is stable, that is, the signal flowing through the fifth transistor T5 is ensured to be stable.

[0139] For example, the seventh transistor T7 is an N-type transistor. Considering that the leakage current of the N-type transistor is small, the voltage stabilizing circuit 6206 adopts an electronic component with an N-type transistor, which can reduce the probability of the voltage stabilizing effect decreasing due to the leakage current.

[0140] In addition, the voltage stabilizing circuit 6206 may also be a circuit including other electronic components with voltage stabilizing effects. By way of example, the voltage stabilizing circuit 6206 is a circuit including one or more of a voltage stabilizing diode and a linear voltage regulator (such as a low dropout regulator (LDO)). The embodiments of the present application do not limit this.

[0141] For ease of understanding, based on the page buffer 622 with the latch circuit 6223 provided in the above example, an exemplary description is given of the process of a latch circuit 6223 implementing data latching and adjusting the potential of the sensing node SO. It should be noted that other latch circuits 6223 in the page buffer 622 can perform similar methods for data setting operations.

[0142] As Figure 21 shown, the page buffer 622 includes a bit line control circuit 6221, a bit line discharge circuit 6222, and five latch circuits 6223. Among them, the five latch circuits 6223 include a sense latch circuit 6223-1, three data latch circuits 6223-2, 6223-3, and 6223-4, and a cache latch circuit 6223-5.

[0143] The sensing node SO is charged through the bit line control circuit 6221, so that the sensing node SO has a high voltage (for example, the power supply voltage VDD). At the same time, the third transistor T3 in Figure 16 is turned on, so that the ground voltage from the ground terminal can be provided to the second data node Data_bar of the sense latch circuit 6223-1, that is, the sense latch circuit 6223-1 latches the data as "1". Alternatively, the fourth transistor T4 in Figure 16 is turned on, so that the ground voltage from the ground terminal can be transmitted to the first data node Data of the sense latch circuit 6223-1, that is, the sense latch circuit 6223-1 latches the data as "0".

[0144] It should be noted that the data "1" can represent a high level or a low level, and the data "0" can represent a low level or a high level. The embodiments of the present application take the data "1" representing a high level and the data "0" representing a low level as an example for description.

[0145] The sense latch circuit 6223-1 receives the enabled transmission signal rd (for example, the rd signal is a low-level signal), and the latch transmission circuit 6202 in the sense latch circuit 6223-1 is turned on. If the data stored in the sense latch circuit 6223-1 is "1", the high voltage on the sense node SO can be discharged to a low voltage through the latch transmission circuit 6202; if the data stored in the sense latch circuit 6223-1 is "0", the latch transmission circuit 6202 in the sense latch circuit 6223-1 is turned off, and the high voltage on the sense node SO cannot be discharged through the latch transmission circuit 6202, and the voltage on the sense node SO remains high.

[0146] Therefore, the data information stored in the sense latch circuit 6223-1 can be obtained by sensing the voltage at the sense node SO at this time. Similarly, the data information stored in the corresponding latch circuit 6223 can be sensed by using each latch circuit 6223.

[0147] In addition, please continue to refer to Figure 21 , the page buffer 622 further includes a data setting circuit 6224. The data setting circuit 6224 is a forced setting circuit, that is, when the second data setting signal rst_sa_latch is enabled (for example, the rst_sa_latch signal is a high-level signal), regardless of the voltage magnitude of the sense node at this time, the specified latch circuit 6223 can be set with data.

[0148] Exemplarily, as Figure 21 shown, the data setting circuit 6224 includes an eighth transistor T8. The control electrode of the eighth transistor T8 is configured to receive the data setting signal rst_sa_latch; the first electrode of the eighth transistor T8 is connected to the latch circuit 6223; the second electrode of the eighth transistor T8 is connected to the ground voltage node GND.

[0149] The eighth transistor T8 includes, but is not limited to, a P-type transistor or an N-type transistor. In the embodiments of the present application, the eighth transistor T8 is taken as an N-type transistor as an example for illustration.

[0150] In the embodiments provided by the present application, before enabling the page buffer 622, the data setting circuit 6224 can be used to perform a set or reset operation on one or more latch circuits 6223 in the page buffer 622. For example, the reset operation can be represented by the binary data "0", and the set operation can be represented by "1".

[0151] In some examples, the peripheral circuit 62 further includes a control logic circuit ( Figure 21 not shown in the figure). The control logic circuit is connected to the data setting circuit 6224 of the page buffer 622 and is configured to generate the data setting signal rst_sa_latch. For example, Figure 5The control logic unit 625 shown includes the control logic circuit.

[0152] The control logic circuit can also be used to generate various control signals required by the page buffer 100, including but not limited to the data setup signal rst_sa_latch.

[0153] On the other hand, based on the page buffer 622 provided in any of the above examples (see Figures 8 - 21 ), as Figure 23 and Figure 24 shown, the embodiment of the present application also provides an operation method for the page buffer 622. In combination with Figure 20 , Figure 21 , Figure 22A and Figure 22B , an exemplary description of the operation method of the page buffer 622 is given. Among them, the latch circuit 6223 of the page buffer 622 takes the Figure 16 shown circuit structure as an example. The operation method of the page buffer 622 of the present application does not limit that all latch circuits 6223 are of the Figure 16 shown circuit structure. For example, the latch circuit 6223 can also include the circuit structure of the voltage stabilizing circuit 6206 as shown in Figures 17 - 19 .

[0154] As Figure 20 and Figure 21 shown, the page buffer 622 includes a bit line control circuit 6221, a bit line discharge circuit 6222, and a plurality of latch circuits 6223.

[0155] The bit line control circuit 6221 is connected to the power supply voltage node VDD, the bit line BL, and the sense node SO, and is configured to control the potential level of the sense node SO based on the current level of the bit line BL during the sensing operation.

[0156] Exemplarily, the bit line control circuit 6221 can set the voltage at the sense node SO by sensing the data latched in the latch circuit 6223; it can also directly set the voltage at the sense node SO based on the power supply voltage VDD provided by the power supply voltage node VDD in response to the level signals at the Prech_all_en terminal and the Prech_sel_en terminal being in the enabled state. For example, when the signals transmitted at the Prech_all_en terminal and the signals transmitted at the Prech_sel_en terminal are both enabled, the power supply voltage (such as VDD) can be applied to the sense node SO through the bit line control circuit 6221.

[0157] Exemplarily, during the process of programming a memory cell, the bit line control circuit 6221 can be used to apply a prohibited programming bit line voltage (e.g., VDD) or a normal programming bit line voltage (e.g., VSS) to the bit line BL connected to the memory cell. Exemplarily, the charging function of the bit line control circuit 6221 is used to apply a high level to the bit line to achieve the effect of prohibiting programming, or the discharging function of the bit line control circuit 6221 is used to discharge the bit line, so that the voltage of the bit line is pulled down to the ground voltage to achieve the effect of allowing programming. Among them, the normal programming bit line voltage < the prohibited programming bit line voltage.

[0158] The bit line discharging circuit 6222 is connected between the bit line BL and the ground voltage node GND, and is configured to discharge the potential level of the bit line BL in response to the discharging control signal prech_all_en.

[0159] Exemplarily, the bit line discharging circuit 6222 can be a combination of multiple N-type transistors and / or P-type transistors. Alternatively, the bit line discharging circuit 6222 includes components that can be used to clamp the voltage or regulate the voltage, such as one or more of a Zener diode, a transient voltage suppressor, a varistor, etc. Exemplarily, the bit line discharging circuit 6222 can generate different bit line forced voltages based on different electronic components. For example, a first bit line forced voltage, a second bit line forced voltage. And the normal programming bit line voltage < the first bit line forced voltage < the second bit line forced voltage < the prohibited programming bit line voltage.

[0160] In this way, the bit line discharging circuit 6222 can be used to apply different bit line forced voltages to the bit line BL to achieve fine-grained programming of the memory cell, making the target threshold voltage distribution narrower, increasing the read window between memory cells in different programming states, and ensuring accurate data reading.

[0161] A plurality of latch circuits 6223 are connected to the sense node SO, and charge and discharge the level of the sense node SO under the drive of the bit line control circuit 6221 and the bit line discharging circuit 6222. As Figure 10 shown, each latch circuit 6223 includes a latch configuration circuit 6201 disposed between the first data node Data and the second data node Data_bar, and a latch transmission circuit 6202 connected to the first data node Data, the second data node Data_bar, and the sense node SO.

[0162] In some examples, as Figure 20 shown, in the bit line control circuit 6221, when the prech_sel_en signal and the prech_all_en signal are both enabled, the power supply voltage (VDD) can be directly applied to the sense node SO.

[0163] At this time, the second transistor T2 in the latch circuit 6223 is turned off. The latch circuit 6223 is coupled to the ground voltage node GND through the data setting circuit 6224, and under the combined action of the first transistor T1 and the second transistor T2 (i.e., the fifth transistor T5 is turned on). Furthermore, when the latch circuit 6223 is enabled in response to the rd signal, the latch circuit 6223 is coupled to the sense node SO, and the level of the sense node SO is discharged. In this way, when the vbias signal and the vsoblk signal are enabled simultaneously, the level signal of the sense node SO is fed back to the bit line BL. The bit line BL obtains the data stored in the latch circuit 6223 by reading the level of the sense node SO.

[0164] Or, please continue to refer to Figure 20 , when the prech_sel_en signal is in the enabled state and the prech_all_en signal is in the disabled state, the bit line control circuit 6221 applies the power supply voltage (VDD) to the sense node SO in response to the signal transmitted by the latch circuit 6223.

[0165] At this time, the second transistor T2 in the latch circuit 6223 is turned on. The latch circuit 6223 is coupled to the ground voltage node GND through the data setting circuit 6224, and under the combined action of the first transistor T1 and the second transistor T2 (i.e., the fifth transistor T5 is turned off), the latch circuit 6223 does not discharge the level of the sense node SO.

[0166] Furthermore, when the bit line control circuit 6221 is enabled in response to both the vbias signal and the vsoblk signal to couple the bit line BL and the sense node SO, the bit line BL obtains the data stored in the latch circuit 6223 by reading the level of the sense node SO.

[0167] To more clearly illustrate the driving process of the latch circuit 6223 of the page buffer 622, the following combines Figure 22A and Figure 22B The shown timing diagram, taking the latch circuit 6223 shown in Figure 16 as an example, will elaborate on the above steps in detail.

[0168] As Figure 16 shown, the latch circuit 6223 includes a latch configuration circuit 6201 and a latch transmission circuit 6202. The latch configuration circuit 6201 includes a data transmission circuit 6203, a setting control circuit 6204, and a reset control circuit 6205.

[0169] The data transmission circuit 6203 includes a first transistor T1 and a second transistor T2. Both the first transistor T1 and the second transistor T2 are P-type transistors.

[0170] The setup control circuit 6204 includes a third transistor T3. The third transistor T3 is an N-type transistor.

[0171] The reset control circuit 6205 includes a fourth transistor T4. The fourth transistor T4 is an N-type transistor.

[0172] The latch transfer circuit 6202 includes a fifth transistor T5 and a sixth transistor T6 connected in series. Both the fifth transistor T5 and the sixth transistor T6 are P-type transistors.

[0173] Based on this, as Figure 23 and Figure 24 shown, the operation method includes at least S100, S200, S300, and S400. Among them, as Figure 22A and Figure 22B shown, the operation process of the page buffer 622 includes three stages: a setup stage P-SET, a reset stage P-RST, and a read stage P-RD. And, Figure 22A and Figure 22B The provided timing diagram only exemplarily represents the signals used during the driving process of the latch circuit 6223. There can be a certain time interval between different stages, or they can be adjacent. This application does not limit this.

[0174] At the same time, in order to reflect the characteristics of the latch circuit 6223, that is, in different stages, the latch circuit 6223 responds to configuration signals with opposite logic levels (for example, the logic levels of the setup signal set and the reset signal rst are opposite in the same stage), so that the logic levels of the first data node Data and the second data node Data_bar connected to the latch configuration circuit 6201 are opposite.

[0175] Exemplarily, as Figure 22A shown, the previous stage of the read stage P-RD can be the reset stage P-RST. The logic levels of the first data node Data and the second data node Data_bar obtained in the reset stage P-RST are a set of target levels. Then, based on the characteristics of the latch circuit 6223, before the reset stage P-RST, there must be a process in which the logic levels of the first data node Data and the second data node Data_bar are opposite to this set of target levels (for example, the setup stage P-SET).

[0176] Another exemplarily, as Figure 22BAs shown, the previous stage of the read stage P-RD can also be the set stage P-SET, and the logic levels of the first data node Data and the second data node Data_bar obtained in the set stage P-SET are a set of target levels. Then, based on the characteristics of the latch circuit 6223, there must be a process in which the logic levels of the first data node Data and the second data node Data_bar are opposite to the set of target levels before the set stage P-SET (for example, the reset stage P-RST).

[0177] Moreover, considering that the states of multiple latch circuits 6223 in different page buffers 622 can be the same or different. For example, some latch circuits 6223 perform write data operations, and another part of the latch circuits 6223 perform active data transfer operations. That is to say, the read stage P-RD reads the data latched in the previous stage (set stage P-SET or reset stage P-RST) of the current state of the latch circuit 6223. In this way, within the same time period, the signals transmitted by different latch circuits 6223 are different, and the data read in the read stage P-RD is different.

[0178] Therefore, as Figure 22A and Figure 22B shown, in the same timing process, two front-back sequences of the set stage P-SET and the reset stage P-RST are reflected.

[0179] To clearly distinguish the different operation methods for the read stage P-RD of different latch circuits 6223 to obtain data, Figure 22A and Figure 23 , and Figure 22B and Figure 24 these two operation methods are taken as examples for illustration.

[0180] In some examples, as Figure 22A and Figure 23 shown, the operation process of the page buffer 622 includes the set stage P-SET, the reset stage P-RST after the set stage P-SET, and the read stage P-RD after the reset stage P-RST.

[0181] Exemplarily, as Figure 16 , Figure 22A and Figure 23 shown, the operation method includes S300, S100, and S200.

[0182] S300: In the set stage P-SET, in response to the enable state of the set signal set, the latch configuration circuit 6201 sets the first data node Data and the second data node Data_bar to the first logic level and the second logic level respectively. The first logic level is higher than the second logic level.

[0183] For example, please continue to refer to Figure 16 and Figure 22A , a pre-charge operation is performed on the sensing node SO, so that the sensing node SO has a first logic level. For example, the first logic level is VDD.

[0184] Set the third transistor T3 of the control circuit 6204 to be turned on in the enabled state in response to the set signal, couple the ground voltage node GND to the second data node Data_bar, and transmit the second logic level to the control pole of the second transistor T2 in the data transmission circuit 6203. The second transistor T2 is turned on, and the first logic level of the power supply voltage node VDD is transmitted to the first data node Data. At this time, the fourth transistor T4 of the reset control circuit 6205 is turned off in response to the reset signal rst, and the level of the first data node Data remains the first logic level.

[0185] At the same time, the first transistor T1 in the data transmission circuit 6203 is turned off in response to the first logic level of the first data node Data, and the level of the second data node Data_bar remains the second logic level. For example, the second logic level is VSS.

[0186] In this way, the fifth transistor T5 of the latch transmission circuit 6202 is turned off in response to the level signal of the first data node Data. The latch circuit 6223 is not connected to the sensing node SO, and the sensing node SO remains the first logic level.

[0187] S100: In the reset stage P-RST, in response to the enabled state of the reset signal rst, the latch configuration circuit 6201 initializes the first data node Data and the second data node Data_bar to the second logic level and the first logic level respectively.

[0188] For example, please continue to refer to Figure 16 and Figure 22A , the reset setting circuit 6205 responds to the enabled state of the reset signal rst, the fourth transistor T4 of the reset control circuit 6205 is turned on, and the level of the ground voltage node GND is transmitted to the first data node Data, and the level of the first data node Data is set to the second logic level.

[0189] The first transistor T1 of the data transmission circuit 6203 is turned on in response to the second logic level of the first data node Data, and the level of the power supply voltage node VDD is transmitted to the second data node Data_bar, and the level of the second data node Data_bar is set to the first logic level. The first logic level is higher than the second logic level. For example, the first logic level is VDD and the second logic level is VSS.

[0190] Meanwhile, the third transistor T3 of the control circuit 6204 is turned off in a non-enabled state in response to the set signal set, and the level of the second data node Data_bar is maintained at the first logic level.

[0191] In this way, the fifth transistor T5 of the latch transfer circuit 6202 is turned on in response to the second logic level of the first data node Data. Since the sixth transistor T6 is turned off in a non-enabled state in response to the transfer signal rd, the latch circuit 6223 is not connected to the sense node SO, and the sense node SO remains at the first logic level.

[0192] Based on the above operation process, the level of the sense node SO is the first logic level. The latch circuit 6223 is programmed through the bit line BL, and the latch circuit 6223 latches the target data. The data set in the reset stage P-RST is read in the subsequent read stage P-RD.

[0193] S200: In the read stage P-RD after the reset stage P-RST, the sense node SO is at the second logic level; and, in response to the transfer signal rd being in an enabled state, the latch transfer circuit 6202 connects the second data node Data_bar to the sense node SO, and transfers the first logic level of the second data node Data_bar to the sense node SO. The sense node SO changes from the second logic level to the first logic level.

[0194] Exemplarily, first, the level of the sense node SO is discharged to the second logic level.

[0195] Please continue to refer to Figure 16 and Figure 22A After S100, the first data node Data has the second logic level, and the second data node Data_bar has the first logic level. The fifth transistor T5 of the latch transfer circuit 6202 is turned on in response to the second logic level of the first data node Data, and the sixth transistor T6 is turned on in response to the transfer signal rd to connect the second data node Data_bar to the sense node SO. Thus, the first logic level of the second data node Data_bar is transferred to the sense node SO.

[0196] In this way, the sense node SO changes from the second logic level to the first logic level. That is to say, the data of the latch circuit 6223 is read through the bit line BL. Furthermore, the read data can be latched into other latch circuits 6223 through the bit line BL (such as the methods in S300 and S100 above).

[0197] In other examples, such as Figure 22B and Figure 24As shown, the operation process of the page buffer 622 includes a reset stage P-RST, a setup stage P-SET after the reset stage P-RST, and a read stage P-RD after the setup stage P-SET.

[0198] Exemplarily, as Figure 16 、 Figure 22B and Figure 24 shown, the operation method includes S100, S300, and S400.

[0199] S100: In the reset stage P-RST, in response to the enabled state of the reset signal rst, the latch configuration circuit 6201 initializes the first data node Data and the second data node Data_bar to the second logic level and the first logic level, respectively. The first logic level is higher than the second logic level.

[0200] Exemplarily, please continue to refer to Figure 16 and Figure 22B , the reset setup circuit 6205, in response to the enabled state of the reset signal rst, turns on the fourth transistor T4 of the reset control circuit 6205, transfers the level of the ground voltage node GND to the first data node Data, and sets the level of the first data node Data to the second logic level.

[0201] The first transistor T1 of the data transfer circuit 6203 turns on in response to the second logic level of the first data node Data, transfers the level of the power supply voltage node VDD to the second data node Data_bar, and sets the level of the second data node Data_bar to the first logic level. The first logic level is higher than the second logic level. For example, the first logic level is VDD and the second logic level is VSS.

[0202] Meanwhile, the third transistor T3 of the setup control circuit 6204 turns off in response to the non-enabled state of the setup signal set, and the level of the second data node Data_bar is maintained at the first logic level.

[0203] In this way, the fifth transistor T5 of the latch transfer circuit 6202 turns on in response to the second logic level of the first data node Data. Since the sixth transistor T6 turns off in response to the non-enabled state of the transfer signal rd, the latch circuit 6223 is not connected to the sense node SO, and the sense node SO remains at the first logic level.

[0204] S300: In the setup stage P-SET, in response to the enabled state of the setup signal set, the latch configuration circuit 6201 sets the first data node Data and the second data node Data_bar to the first logic level and the second logic level, respectively.

[0205] Exemplarily, please continue to refer toFigure 16 and Figure 22B The third transistor T3 of the control circuit 6204 is set to conduct in the enabled state in response to the set signal, coupling the ground voltage node GND to the second data node Data_bar, and transmitting the second logic level to the control electrode of the second transistor T2 in the data transmission circuit 6203. The second transistor T2 conducts, transmitting the first logic level of the power supply voltage node VDD to the first data node Data. At this time, the fourth transistor T4 of the reset control circuit 6205 is turned off in response to the reset signal rst, and the level of the first data node Data remains at the first logic level.

[0206] Meanwhile, the first transistor T1 in the data transmission circuit 6203 is turned off in response to the first logic level of the first data node Data, and the level of the second data node Data_bar remains at the second logic level.

[0207] In this way, the fifth transistor T5 of the latch transmission circuit 6202 is turned off in response to the level signal of the first data node Data. The latch circuit 6223 is not connected to the sense node SO, and the sense node SO remains at the first logic level.

[0208] Based on the above operation process, the level of the sense node SO is the first logic level. The latch circuit 6223 is programmed through the bit line BL, and the latch circuit 6223 latches the target data. The data set in the setup phase P-SET is read in the subsequent read phase P-RD.

[0209] S400: In the read phase P-RD after the setup phase P-SET, the sense node SO is at the second logic level; and the latch transmission circuit 6202 disconnects the second data node Data_bar from the sense node SO, and the level of the sense node SO remains at the second logic level.

[0210] Exemplarily, first, the level of the sense node SO is discharged to the second logic level.

[0211] Please continue to refer to Figure 16 and Figure 22B After S300, the first data node Data has the first logic level, and the second data node Data_bar has the second logic level. The fifth transistor T5 of the latch transmission circuit 6202 is turned off in response to the first logic level of the first data node Data.

[0212] Based on this, regardless of whether the transmission signal rd is in the enabled state (i.e., when the rd signal is a high-level signal, the sixth transistor T6 is turned off; or when the rd signal is a low-level signal, the sixth transistor T6 is in the conducting state), the second data node Data_bar is not connected to the sensing node SO, and the level of the sensing node SO remains at the second logic level. In this way, the bit line BL continuously reads the data of the latch circuit 6223 through the sensing node SO.

[0213] The operation method of the page buffer 622 provided by this application includes Figure 23 and Figure 24 the two processes shown. One is based on the level signals stored in the first data node Data and the second data node Data_bar during the reset stage P-RST. During the read stage P-RD, the latch transmission circuit 6202 is connected to the sensing node SO through the enabled state of the transmission signal rd, causing the level of the sensing node SO to change. The other is based on the level signals stored in the first data node Data and the second data node Data_bar during the setup stage P-SET. During the read stage P-RD, even in response to the enabled state of the transmission signal rd, the latch transmission circuit 6202 is not connected to the sensing node SO, and the level of the sensing node SO is maintained. These two processes are based on multiple latch circuits of different page buffers. Different latch circuits may have different states during the same time period, which is characterized in that the operation process of the page buffer 622 can be that the data read in the read stage P-RD is the data stored in the setup stage P-SET, or the data stored in the reset stage P-RST. In this way, during the read stage P-RD, the latch circuits 6223 of different page buffers 622 have different effects on the level of the sensing node SO, so that different data of different page buffers 622 can be obtained through the sensing node SO. The circuit structure of the page buffer 622 provided by this application can simultaneously implement the reading of data in different states of the storage unit.

[0214] It should be understood that "some embodiments" or "some examples" mentioned throughout the specification mean that specific features, structures, or characteristics related to the embodiments are included in at least one embodiment of this application. Therefore, the appearances of "in some embodiments" or "in some examples" throughout the specification do not necessarily refer to the same embodiments. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of this application, the magnitudes of the sequence numbers of the above processes do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this application. The sequence numbers of the embodiments of this application above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0215] It should be noted that in this text, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the presence of additional identical elements in the process, method, article or device including such element.

[0216] As described above, this is only the implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A page buffer, characterized in that, it includes: a plurality of latch circuits, each of the latch circuits includes: a latch configuration circuit connected to a first data node and a second data node, configured to, in response to a configuration signal, configure the first data node and the second data node to different logic levels respectively, wherein the logic levels of the first data node and the second data node are opposite; a latch transfer circuit connected to the first data node, the second data node and a sense node, configured to, in response to a transfer signal, couple the second data node to the sense node to transfer the configuration result of the latch configuration circuit to the sense node.

2. The page buffer according to claim 1, characterized in that, the latch configuration circuit is configured to, in response to a set signal being in an enabled state, set the first data node and the second data node to a first logic level and a second logic level respectively; in response to a reset signal being in an enabled state, initialize the first data node and the second data node to the second logic level and the first logic level respectively; the first logic level is higher than the second logic level; the latch transfer circuit is configured to, when the sense node is at the second logic level, in response to the transfer signal being in an enabled state and the first data node and the second data node being at the second logic level and the first logic level respectively, connect the second data node to the sense node, and the sense node changes from the second logic level to the first logic level.

3. The page buffer according to claim 2, characterized in that, the latch transfer circuit is further configured to, when the sense node is at the second logic level, in response to the transfer signal being in an enabled state and the first data node and the second data node being at the first logic level and the second logic level respectively, keep the sense node at the second logic level.

4. The page buffer according to claim 1, characterized in that, the latch configuration circuit includes: a data transfer circuit, a set control circuit and a reset control circuit; wherein, the data transfer circuit is connected to a power supply voltage node, the first data node and the second data node, configured to make the logic levels of the first data node and the second data node opposite; the set control circuit is connected to the second data node and a ground voltage node, configured to receive the set signal and control the connection or disconnection of the second data node and the ground voltage node according to the level of the set signal; the reset control circuit is connected to the first data node and the ground voltage node, configured to receive the reset signal and control the connection or disconnection of the first data node and the ground voltage node according to the level of the reset signal.

5. The page buffer according to claim 4, characterized in that, the data transfer circuit includes a first transistor and a second transistor; The control electrode of the first transistor is connected to the first data node, the first pole of the first transistor is connected to the power supply voltage node, and the second pole of the first transistor is connected to the second data node; The control electrode of the second transistor is connected to the second data node, the first pole of the second transistor is connected to the power supply voltage node, and the second pole of the second transistor is connected to the first data node.

6. The page buffer according to claim 4, wherein, The setting control circuit includes a third transistor, the control electrode of the third transistor receives the setting signal, the first pole of the third transistor is connected to the ground voltage node, and the second pole of the third transistor is connected to the second data node; The reset control circuit includes a fourth transistor, the control electrode of the fourth transistor receives the reset signal, the first pole of the fourth transistor is connected to the ground voltage node, and the second pole of the fourth transistor is connected to the first data node.

7. The page buffer according to claim 1, wherein, The latch transfer circuit includes a fifth transistor and a sixth transistor connected in series; the fifth transistor and the sixth transistor are P-type transistors.

8. The page buffer according to claim 7, wherein, The control electrode of the fifth transistor is connected to the first data node, the second pole of the fifth transistor is connected to the second data node, and the first pole of the fifth transistor is connected to the second pole of the sixth transistor; The control electrode of the sixth transistor receives the transfer signal, and the first pole of the sixth transistor is connected to the sense node.

9. The page buffer according to claim 1, wherein, The latch circuit further includes: A voltage stabilizing circuit, connected to the first data node and the second data node, and configured to stabilize the voltage difference between the first data node and the second data node.

10. The page buffer according to claim 9, wherein, The voltage stabilizing circuit includes a capacitor; The first electrode plate of the capacitor is connected to the first data node, and the second electrode plate of the capacitor is connected to the second data node.

11. The page buffer according to claim 9, wherein, The voltage stabilizing circuit includes a seventh transistor; The control electrode of the seventh transistor is connected to the second data node, and both the first pole and the second pole of the seventh transistor are connected to the first data node.

12. The page buffer according to claim 1, wherein, The page buffer further includes: A bit line control circuit, connected to the power supply voltage node, the bit line and the sense node, and configured to control the potential level of the sense node based on the current level of the bit line during a sensing operation; A bit line discharge circuit, connected between the bit line and the ground voltage node, and configured to discharge the potential level of the bit line in response to a discharge control signal.

13. A memory device, wherein, comprising: A memory cell array, connected to a plurality of bit lines; A plurality of page buffers as described in any one of claims 1 to 12, each of the page buffers being connected to one of the bit lines and configured to perform a sensing operation based on the current level of the bit line.

14. A memory system, characterized in that, the memory system comprises: one or more memory devices as described in claim 13; a memory controller, connected to the memory device and configured to control the memory device.

15. A method for operating a page buffer, characterized in that, the page buffer includes a plurality of latch circuits, each latch circuit including a latch configuration circuit disposed between a first data node and a second data node and a latch transfer circuit connected to the first data node, the second data node and a sense node; the operating method includes: in a reset phase, in response to the enable state of the reset signal, the latch configuration circuit initializes the first data node and the second data node to a second logic level and a first logic level respectively; the first logic level is higher than the second logic level; in a read phase after the reset phase, the sense node is at the second logic level; and, in response to the transfer signal being in an enabled state, the latch transfer circuit connects the second data node to the sense node and transfers the first logic level of the second data node to the sense node; the sense node changes from the second logic level to the first logic level.

16. The method for operating a page buffer according to claim 15, characterized in that, further comprising: in a setup phase, in response to the enable state of the setup signal, the latch configuration circuit sets the first data node and the second data node to a first logic level and a second logic level respectively; in a read phase after the setup phase, the sense node is at the second logic level; and the latch transfer circuit disconnects the second data node from the sense node, and the level of the sense node remains at the second logic level.

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