Memory comprising an ECC engine

Abstract

The invention relates to a memory including an ECC engine. A memory may include: a memory core; an error correction code (ECC) engine configured to: generate an error correction code by using the write data during an encoding operation, the error correction code to be stored in the memory core along with the write data; and correcting an error of read data read from the memory core using the error correction code read from the memory core during the decoding operation; and an error determination circuit configured to: during a decoding operation, determine that there is a 1-bit error when an upper index portion of a syndrome generated by the ECC engine has an odd weight; and determining that there is a correctable 2-bit error when the upper index portion of the syndrome is one of the predetermined even weight patterns.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0165898, filed on November 24, 2023, which is incorporated herein by reference in its entirety. Technical field

[0003] Embodiments of the present disclosure relate to a memory. Background art

[0004] In the early days of the semiconductor memory industry, in memory chips that had passed the semiconductor manufacturing process, multiple original good memory dies with defect - free memory cells were distributed on a wafer. However, as the memory capacity has gradually increased, it has become difficult to produce a memory with defect - free memory cells. Currently, it is impossible to manufacture such a memory. As a method of overcoming this situation, a method of using redundant memory cells to repair defective memory cells of a memory has been used.

[0005] As another method, an error - correcting code (ECC) engine that corrects errors in a memory is used to correct errors that occur in memory cells. Summary of the invention

[0006] In an embodiment of the present disclosure, a memory may include: a memory core; an error - correcting code (ECC) engine configured to: generate an error - correcting code by using write data during an encoding operation, and the error - correcting code will be stored in the memory core together with the write data; and use the error - correcting code read from the memory core to correct an error in read data read from the memory core during a decoding operation; and an error determination circuit configured to: during a decoding operation, determine that there is a 1 - bit error when an upper index part of a syndrome generated by the ECC engine has an odd weight; and determine that there is a correctable 2 - bit error when the upper index part of the syndrome is one of predetermined even - weight patterns.

[0007] In an embodiment of the present disclosure, a memory may include: a memory core; an error - correcting code (ECC) engine configured to: generate an error - correcting code by using write data during an encoding operation, and the error - correcting code will be stored in the memory core together with the write data; and use the error - correcting code read from the memory core to correct an error in read data read from the memory core during a decoding operation; and an error determination circuit configured to: during a decoding operation, determine that there is a 1 - bit error when an upper index part of a syndrome generated by the ECC engine has an odd weight; and determine that there is a 1 - bit error when the upper index part has a specific even weight and a lower index part matches one of predetermined first patterns.

[0008] During a decoding operation, when the upper index portion of a syndrome has an even weight that matches one of a predetermined second pattern, the error determination circuit determines that there is a correctable 2-bit error; and when the upper index portion of the syndrome is a predetermined third pattern and the lower index portion matches one of a predetermined fourth pattern, the error determination circuit determines that there is a correctable 2-bit error.

[0009] In one embodiment of the present disclosure, a memory may include: a memory core; an error correction code (ECC) engine configured to perform an encoding operation and a decoding operation; and an error determination circuit, wherein the ECC engine is configured to: during the encoding operation, receive write data, generate an error correction code using the write data, and provide the write data and the error correction code to the memory core for storage; during the decoding operation, read read data and an error correction code from the memory core, decode the read data using the error correction code, and generate a syndrome value for the decoded read data, the syndrome value including an upper portion and a lower portion, and wherein the error determination circuit is configured to determine whether the decoded read data includes a 1-bit error or a 2-bit error based on a combination of bit patterns and bit weights of the upper portion and the lower portion of the syndrome value. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a configuration diagram of an ECC engine according to an embodiment of the present disclosure.

[0011] Figure 2 is a diagram illustrating a parity check matrix used by an error correction code encoder and an error correction code decoder according to an embodiment of the present disclosure.

[0012] Figure 3 is a diagram expressing Equations 1 to 8 by using matrix operations according to an embodiment of the present disclosure.

[0013] Figure 4 is an illustration of an error correction code encoder according to an embodiment of the present disclosure by using Figure 2 to generate an error correction code ECC for data DATA(1,1,0,0,1,0,1,0).

[0014] Figure 5 is a diagram illustrating a process of an error correction code decoder generating syndromes S0 to S7 for error correction according to an embodiment of the present disclosure.

[0015] Figure 6 is a diagram illustrating how an error correction code decoder generates syndromes S0 to S7 when there is no error in data DATA' according to an embodiment of the present disclosure.

[0016] Figure 7It is a diagram illustrating how an error correction code decoder according to an embodiment of the present disclosure generates syndrome S0 to S7 when there is an error in data DATA'.

[0017] Figure 8 It is a configuration diagram of a memory according to an embodiment of the present disclosure.

[0018] Figure 9 It is an illustration of according to an embodiment of the present disclosure Figure 8 A diagram of the parity check matrix used by the error correction code encoder and the error correction code decoder of the ECC engine in

[0019] Figure 10 It is according to an embodiment of the present disclosure in which Figure 9 The columns of the parity check matrix in are reduced to a 2:1 matrix.

[0020] Figure 11 It is an illustration of according to an embodiment of the present disclosure when the ECC engine uses Figure 9 the parity check matrix in Figure 8 A diagram of the operation of the error determination circuit in

[0021] Figure 12 It is an illustration of according to an embodiment of the present disclosure Figure 8 Another diagram of the parity check matrix used by the error correction code encoder and the error correction code decoder of the ECC engine in

[0022] Figure 13 It is according to an embodiment of the present disclosure in which Figure 12 The columns of the parity check matrix in are reduced to a 2:1 matrix.

[0023] Figure 14 It is an illustration of according to an embodiment of the present disclosure when the ECC engine uses Figure 12 the parity check matrix in Figure 8 A diagram of the operation of the error determination circuit in

[0024] Figure 15 It is a configuration diagram of an error determination circuit operating as shown in according to an embodiment of the present disclosure Figure 14 Detailed Description

[0025] Various embodiments of the present disclosure are directed to providing a technique for determining an error that occurs in a memory.

[0026] Embodiments of the present disclosure can provide a technique for determining an error that occurs in a memory.

[0027] Hereinafter, embodiments according to the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

[0028] Figure 1 ​Configuration diagram of an error correction code (ECC) engine 100 according to an embodiment of the present disclosure.

[0029] Reference Figure 1 , the ECC engine 100 may include an error correction code encoder 110 and an error correction code decoder 120.

[0030] During a write operation, the error correction code encoder 110 may generate an error correction code ECC by using data DATA transmitted from outside the memory (e.g., a memory controller). That is, the error correction code encoder 110 may encode the data DATA and generate an error correction code ECC to correct errors in the data related to a read operation. The data DATA to be encoded during the process of generating the error correction code ECC is also referred to as a message. During a write operation, since the error correction code ECC is generated but no error correction operation is performed, the data DATA input to the error correction code encoder 110 and the data DATA' output from the error correction code encoder 110 may be the same.

[0031] During a write operation, the data DATA' and the error correction code ECC may be stored in a memory core (not shown). During a read operation, the data DATA' and the error correction code ECC may be read from the memory core and transmitted to the error correction code decoder 120.

[0032] During a read operation, the error correction code decoder 120 may correct errors in the data DATA' by using the error correction code ECC. Correcting an error may mean detecting an error in the data DATA' by using the error correction code ECC and correcting the error when the error is detected. The data DATA in which the error has been corrected by the error correction code decoder 120 may be output outside the memory. That is, the data DATA may be transmitted to the memory controller.

[0033] Figure 2 Is a diagram illustrating a parity check matrix used by the error correction code encoder 110 and the error correction code decoder 120 according to an embodiment of the present disclosure. In Figure 2 , the data DATA includes 8 bits D0 to D7, and the error correction code ECC includes 8 bits E0 to E7.

[0034] The parity check matrix may include a (number of bits of the error correction code) × (number of bits of the data + number of bits of the error correction code) matrix. Since the error correction code ECC includes 8 bits and the data DATA includes 8 bits, the parity check matrix may include an 8×16 matrix. The value of each element of the parity check matrix may be 1 or 0.

[0035] The column vectors of the parity check matrix may correspond to the bits D0 to D7 of the data DATA and the bits E0 to E7 of the error correction code ECC. From Figure 2It can be seen that D1 corresponds to the column vector with the value '01010100', and E1 corresponds to the column vector with the value '01000000'.

[0036] Next, how to use the parity-check matrix to generate the error-correcting code ECC will be introduced. The error-correcting code encoder 110 can multiply the column vectors of the parity-check matrix by the corresponding bit positions and then generate the error-correcting code ECC such that the sum of the rows becomes 0 (i.e., even).

[0037] That is to say, the bit positions E0 to E7 of the error-correcting code ECC can be generated to satisfy the following eight equations.

[0038] Equation 1

[0039] 1*D0 + 0*D1 + 1*D2 + 0*D3 + 1*D4 + 0*D5 + 1*D6 + 0*D7 + 1*E0 + 0*E1 + 0*E2 + 0*E3 + 0*E4 + 0*E5 + 0*E6 + 0*E7 = 0 (for the first row)

[0040] Equation 2

[0041] 0*D0 + 1*D1 + 0*D2 + 1*D3 + 0*D4 + 1*D5 + 0*D6 + 1*D7 + 0*E0 + 1*E1 + 0*E2 + 0*E3 + 0*E4 + 0*E5 + 0*E6 + 0*E7 = 0 (for the second row)

[0042] Equation 3

[0043] 1*D0 + 0*D1 + 0*D2 + 1*D3 + 1*D4 + 1*D5 + 1*D6 + 0*D7 + 0*E0 + 0*E1 + 1*E2 + 0*E3 + 0*E4 + 0*E5 + 0*E6 + 0*E7 = 0 (for the third row)

[0044] Equation 4

[0045] 0*D0 + 1*D1 + 1*D2 + 1*D3 + 1*D4 + 0*D5 + 0*D6 + 1*D7 + 0*E0 + 0*E1 + 0*E2 + 1*E3 + 0*E4 + 0*E5 + 0*E6 + 0*E7 = 0 (for the fourth row)

[0046] Equation 5

[0047] 1*D0 + 0*D1 + 1*D2 + 1*D3 + 0*D4 + 1*D5 + 0*D6 + 0*D7 + 0*E0 + 0*E1 + 0*E2 + 0*E3 + 1*E4 + 0*E5 + 0*E6 + 0*E7 = 0 (for the fifth row)

[0048] Equation 6

[0049] 0 * D0 + 1 * D1 + 1 * D2 + 0 * D3 + 1 * D4 + 1 * D5 + 0 * D6 + 0 * D7 + 0 * E0 + 0 * E1 + 0 * E2 + 0 * E3 + 0 * E4 + 1 * E5 + 0 * E6 + 0 * E7 = 0 (for the sixth row)

[0050] Equation 7

[0051] 0 * D0 + 0 * D1 + 0 * D2 + 0 * D3 + 0 * D4 + 0 * D5 + 1 * D6 + 0 * D7 + 0 * E0 + 0 * E1 + 0 * E2 + 0 * E3 + 0 * E4 + 0 * E5 + 1 * E6 + 0 * E7 = 0 (for the seventh row)

[0052] Equation 8

[0053] 0 * D0 + 0 * D1 + 0 * D2 + 0 * D3 + 0 * D4 + 0 * D5 + 0 * D6 + 1 * D7 + 0 * E0 + 0 * E1 + 0 * E2 + 0 * E3 + 0 * E4 + 0 * E5 + 0 * E6 + 1 * E7 = 0 (for the eighth row)

[0054] The addition in the above equations and the following description represents exclusive OR. Therefore, when the number of 1s is even, the result of the addition can be 0, and when the number of 1s is odd, the result of the addition can be 1. For example, 1 + 1 + 0 + 1 can be 1, and 0 + 1 + 1 + 0 can be 0.

[0055] Figure 3 is a diagram expressing Equations 1 to 8 by using matrix operations according to an embodiment of the present disclosure.

[0056] Reference Figure 3 , the following Equations 1 to 8 can be expressed as matrix multiplications of a parity-check matrix of an 8×16 matrix and data DATA (= D0 to D7) and an error correction code ECC (= E0 to E7) of a 16×1 matrix. The error correction code ECC (= E0 to E7) can be generated by such matrix multiplication operations.

[0057] When summarizing the following Equations 1 to 8 to obtain the error correction code ECC (= E0 to E7), Equations 1 to 8 can be simply expressed as the following Equations 1-1, 2-1, 3-1, 4-1, 5-1, 6-1, 7-1, and 8-1, respectively.

[0058] Equation 1-1

[0059] 1 * D0 + 0 * D1 + 1 * D2 + 0 * D3 + 1 * D4 + 0 * D5 + 1 * D6 + 0 * D7 = E0

[0060] Equation 2-1

[0061] 0*D0 + 1*D1 + 0*D2 + 1*D3 + 0*D4 + 1*D5 + 0*D6 + 1*D7 = E1

[0062] Equation 3-1

[0063] 1*D0 + 0*D1 + 0*D2 + 1*D3 + 1*D4 + 1*D5 + 1*D6 + 0*D7 = E2

[0064] Equation 4-1

[0065] 0*D0 + 1*D1 + 1*D2 + 1*D3 + 1*D4 + 0*D5 + 0*D6 + 1*D7 = E3

[0066] Equation 5-1

[0067] 1*D0 + 0*D1 + 1*D2 + 1*D3 + 0*D4 + 1*D5 + 0*D6 + 0*D7 = E4

[0068] Equation 6-1

[0069] 0*D0 + 1*D1 + 1*D2 + 0*D3 + 1*D4 + 1*D5 + 0*D6 + 0*D7 = E5

[0070] Equation 7-1

[0071] 0*D0 + 0*D1 + 0*D2 + 0*D3 + 0*D4 + 0*D5 + 1*D6 + 0*D7 = E6

[0072] Equation 8-1

[0073] 0*D0 + 0*D1 + 0*D2 + 0*D3 + 0*D4 + 0*D5 + 0*D6 + 1*D7 = E7

[0074] Figure 4 illustrates the process by which the error correction code encoder 110 according to an embodiment of the present disclosure generates an error correction code ECC for the data DATA(1, 1, 0, 0, 1, 0, 1, 0) by using Figure 2 in the check matrix.

[0075] Reference Figure 4 , it can be seen that (1, 1, 0, 0, 1, 0, 1, 0) is placed in the position of the data in the matrix multiplication of Figure 3 . When the values of the error correction code ECC(=E0 to E7) that satisfy the matrix multiplication equation of Figure 4 are obtained, the error correction code can be generated as (1, 1, 1, 0, 1, 0, 1, 0).

[0076] Figure 5FIG. is a diagram illustrating a process in which an error correction code decoder 120 according to an embodiment of the present disclosure generates syndrome S0 to S7 for error correction.

[0077] Referring to Figure 5 , the error correction code decoder 120 can generate syndromes S0 to S7 by performing matrix multiplication on the parity check matrix in Figure 2 and the read data DATA'(=D0' to D7') / read error correction code ECC(=E0 to E7). Figure 2 The parity check matrix in

[0078] Figure 5 is the same as the matrix used by the error correction code encoder 110.

[0079] 1*D0'+0*D1'+1*D2'+0*D3'+1*D4'+0*D5'+1*D6'+0*D7'+1*E0+0*E1+0*E2+0*E3+0*E4+0*E5+0*E6+0*E7 = S0 (for the first row)

[0080] 0*D0'+1*D1'+0*D2'+1*D3'+0*D4'+1*D5'+0*D6'+1*D7'+0*E0+1*E1+0*E2+0*E3+0*E4+0*E5+0*E6+0*E7 = S1 (for the second row)

[0081] 1*D0'+0*D1'+0*D2'+1*D3'+1*D4'+1*D5'+1*D6'+0*D7'+0*E0+0*E1+1*E2+0*E3+0*E4+0*E5+0*E6+0*E7 = S2 (for the third row)

[0082] 0*D0'+1*D1'+1*D2'+1*D3'+1*D4'+0*D5'+0*D6'+1*D7'+0*E0+0*E1+0*E2+1*E3+0*E4+0*E5+0*E6+0*E7 = S3 (for the fourth row)

[0083] 1*D0'+0*D1'+1*D2'+1*D3'+0*D4'+1*D5'+0*D6'+0*D7'+0*E0+0*E1+0*E2+0*E3+1*E4+0*E5+0*E6+0*E7 = S4 (for the fifth row)

[0084] 0*D0'+1*D1'+1*D2'+0*D3'+1*D4'+1*D5'+0*D6'+0*D7'+0*E0+0*E1+0*E2+0*E3+0*E4+1*E5+0*E6+0*E7 = S5 (for the sixth row)

[0085] 0 * D0'+ 0 * D1'+ 0 * D2'+ 0 * D3'+ 0 * D4'+ 0 * D5'+ 1 * D6'+ 0 * D7'+ 0 * E0 + 0 * E1 + 0 * E2 + 0 * E3 + 0 * E4 + 0 * E5 + 1 * E6 + 0 * E7 = S6 (for the seventh row)

[0086] 0 * D0'+ 0 * D1'+ 0 * D2'+ 0 * D3'+ 0 * D4'+ 0 * D5'+ 0 * D6'+ 1 * D7'+ 0 * E0 + 0 * E1 + 0 * E2 + 0 * E3 + 0 * E4 + 0 * E5 + 0 * E6 + 1 * E7 = S7 (for the eighth row)

[0087] Figure 6 is a diagram illustrating how the syndrome decoder 120 generates syndromes S0 to S7 when the data DATA' has no errors according to an embodiment of the present disclosure. In Figure 6 it Figure 4 the data (1, 1, 0, 0, 1, 0, 1, 0) and the error correction code (1, 1, 1, 0, 1, 0, 1, 0) shown are stored in the memory core and then read again as they are

[0088] Referring to Figure 6 , it can be seen that the syndromes S0 to S7 are generated as (0, 0, 0, 0, 0, 0, 0, 0) by performing matrix multiplication on the parity check matrix in Figure 2 and the read data DATA' (1, 1, 0, 0, 1, 0, 1, 0) / error correction code ECC (1, 1, 1, 0, 1, 0, 1, 0).

[0089] Figure 6 The generation of

[0090] 1 * 1 + 0 * 1 + 1 * 0 + 0 * 0 + 1 * 1 + 0 * 0 + 1 * 1 + 0 * 0 + 1 * 1 + 0 * 1 + 0 * 1 + 0 * 0 + 0 * 1 + 0 * 0 + 0 * 1 + 0 * 0 = 0

[0091] 0 * 1 + 1 * 1 + 0 * 0 + 1 * 0 + 0 * 1 + 1 * 0 + 0 * 1 + 1 * 0 + 0 * 1 + 1 * 1 + 0 * 1 + 0 * 0 + 0 * 1 + 0 * 0 + 0 * 1 + 0 * 0 = 0

[0092] 1 * 1 + 0 * 1 + 0 * 0 + 1 * 0 + 1 * 1 + 1 * 0 + 1 * 1 + 0 * 0 + 0 * 1 + 0 * 1 + 1 * 1 + 0 * 0 + 0 * 1 + 0 * 0 + 0 * 1 + 0 * 0 = 0

[0093] 0 * 1 + 1 * 1 + 1 * 0 + 1 * 0 + 1 * 1 + 0 * 0 + 0 * 1 + 1 * 0 + 0 * 1 + 0 * 1 + 0 * 1 + 1 * 0 + 0 * 1 + 0 * 0 + 0 * 1 + 0 * 0 = 0

[0094] 1 * 1 + 0 * 1 + 1 * 0 + 1 * 0 + 0 * 1 + 1 * 0 + 0 * 1 + 0 * 0 + 0 * 1 + 0 * 1 + 0 * 1 + 0 * 0 + 1 * 1 + 0 * 0 + 0 * 1 + 0 * 0 = 0

[0095] 0 * 1 + 1 * 1 + 1 * 0 + 0 * 0 + 1 * 1 + 1 * 0 + 0 * 1 + 0 * 0 + 0 * 1 + 0 * 1 + 0 * 1 + 0 * 0 + 0 * 1 + 1 * 0 + 0 * 1 + 0 * 0 = 0

[0096] 0 * 1 + 0 * 1 + 0 * 0 + 0 * 0 + 0 * 1 + 0 * 0 + 1 * 1 + 0 * 0 + 0 * 1 + 0 * 1 + 0 * 1 + 0 * 0 + 0 * 1 + 0 * 0 + 1 * 1 + 0 * 0 = 0

[0097] 0 * 1 + 0 * 1 + 0 * 0 + 0 * 0 + 0 * 1 + 0 * 0 + 0 * 1 + 1 * 0 + 0 * 1 + 0 * 1 + 0 * 1 + 0 * 0 + 0 * 1 + 0 * 0 + 0 * 1 + 1 * 0 = 0

[0098] When the values of syndrome S0 to S7 are all 0, it can indicate that there is no error in the read data DATA'. When the values of syndrome S0 to S7 are all 0, the error correction code decoder 120 can determine that there is no error in the data DATA' and output the data DATA' as it is (DATA' = DATA).

[0099] Figure 7 It is a diagram illustrating how the error correction code decoder 120 generates syndromes S0 to S7 when the data DATA' has an error according to an embodiment of the present disclosure. In Figure 7 In Figure 4 After the data DATA(1, 1, 0, 0, 1, 0, 1, 0) and the error correction code ECC(1, 1, 1, 0, 1, 0, 1, 0) shown are stored in the memory core, an error occurs in the D6 bit of the data. Therefore, the data DATA' is read as (1, 1, 0, 0, 1, 0, 0, 0), and the error correction code ECC is read as (1, 1, 1, 0, 1, 0, 1, 0) and input to the error correction code decoder 120.

[0100] Refer to Figure 7 It can be seen that by performing matrix multiplication on the parity check matrix in Figure 2 and the read data DATA'(1, 1, 0, 0, 1, 0, 0, 0) / error correction code ECC(1, 1, 1, 0, 1, 0, 1, 0), the syndromes S0 to S7 are generated as (1, 0, 1, 0, 0, 0, 1, 0).

[0101] Figure 7 The generation of

[0102] 1*1 + 0*1 + 1*0 + 0*0 + 1*1 + 0*0 + 1*0 + 0*0 + 1*1 + 0*1 + 0*1 + 0*0 + 0*1 + 0*0 + 0*1 + 0*0 = 1

[0103] 0*1 + 1*1 + 0*0 + 1*0 + 0*1 + 1*0 + 0*0 + 1*0 + 0*1 + 1*1 + 0*1 + 0*0 + 0*1 + 0*0 + 0*1 + 0*0 = 0

[0104] 1*1 + 0*1 + 0*0 + 1*0 + 1*1 + 1*0 + 1*0 + 0*0 + 0*1 + 0*1 + 1*1 + 0*0 + 0*1 + 0*0 + 0*1 + 0*0 = 1

[0105] 0*1 + 1*1 + 1*0 + 1*0 + 1*1 + 0*0 + 0*0 + 1*0 + 0*1 + 0*1 + 0*1 + 1*0 + 0*1 + 0*0 + 0*1 + 0*0 = 0

[0106] 1*1 + 0*1 + 1*0 + 1*0 + 0*1 + 1*0 + 0*0 + 0*0 + 0*1 + 0*1 + 0*1 + 0*0 + 1*1 + 0*0 + 0*1 + 0*0 = 0

[0107] 0*1 + 1*1 + 1*0 + 0*0 + 1*1 + 1*0 + 0*0 + 0*0 + 0*1 + 0*1 + 0*1 + 0*0 + 0*1 + 1*0 + 0*1 + 0*0 = 0

[0108] 0*1 + 0*1 + 0*0 + 0*0 + 0*1 + 0*0 + 1*0 + 0*0 + 0*1 + 0*1 + 0*1 + 0*0 + 0*1 + 0*0 + 1*1 + 0*0 = 1

[0109] 0*1 + 0*1 + 0*0 + 0*0 + 0*1 + 0*0 + 0*0 + 1*0 + 0*1 + 0*1 + 0*1 + 0*0 + 0*1 + 0*0 + 0*1 + 1*0 = 0

[0110] The values of the syndrome bits S0 to S7 (1, 0, 1, 0, 0, 0, 1, 0) indicate the position of the error. Refer to Figure 2 In the parity-check matrix, the column vector with the value (1, 0, 1, 0, 0, 0, 1, 0) is the column vector corresponding to D6. Therefore, the error-correction code decoder 120 can determine that there is an error in D6 and correct the error by inverting the value of D6 from 0 to 1. Due to such error correction, the data DATA output from the error-correction code decoder 120 can be (0, 1, 0, 0, 1, 0, 1, 0). That is, the error in the data DATA' input to the error-correction code decoder 120 can be corrected, and the error-corrected data DATA can be generated.

[0111] Figure 8Configuration diagram of a memory 800 according to an embodiment of the present disclosure.

[0112] Referring Figure 8 , the memory 800 may include a data transmission / reception circuit 810, an ECC engine 830, a memory core 870, an error determination circuit 890, and an error information transmission circuit 895.

[0113] The data transmission / reception circuit 810 may transmit and / or receive data DATA. The data transmission / reception circuit 810 may receive the data DATA transmitted from the memory controller during a write operation. In addition, the data transmission / reception circuit 810 may transmit the data DATA to the memory controller during a read operation. Figure 8 Illustrated is that the number of bits of the data DATA transmitted and received by the data transmission / reception circuit 810 during one write and read operation is 128 bits (D0 to D127).

[0114] The ECC engine 830 may include an error correction code encoder 831 and an error correction code decoder 833. During a write operation, the error correction code encoder 831 may generate 8-bit error correction codes E0 to E7 by using the 128-bit data D0 to D127 received via the data transmission / reception circuit 810. The error correction codes E0 to E7 are generated by the error correction code encoder 831 and no error correction operation is performed. Therefore, the data D0 to D127 input to the ECC engine 830 and the data D0' to D127' output from the ECC engine 830 may be the same.

[0115] The error correction code decoder 833 may correct errors in the data D0' to D127' from the memory core 870 by using the error correction codes E0 to E7 from the memory core 870. Error correction may refer to detecting errors in the data D0' to D127' by using the error correction codes E0 to E7 and / or correcting the errors when the errors are detected. The error correction code decoder 833 may generate syndrome bits S0 to S7 during the error correction process. The syndrome bits S0 to S7 may be transmitted to the error determination circuit 890. The data D0 to D127 corrected by the error correction code decoder 833 may be transmitted to the memory controller via the data transmission / reception circuit 810.

[0116] The ECC engine 830 is capable of correcting a 1-bit error occurring in the data D0 to D127 and a 2-bit error occurring in adjacent bits in the data D0 to D127. For example, when an error occurs in 1 bit (D83) of the 128-bit data D0 to D127, the ECC engine 830 may correct the error. When a 2-bit error occurs in two adjacent bits (D4 and D5) of the 128-bit data D0 to D127, the ECC engine 830 may correct the error.

[0117] The memory core 870 may include a cell array, a row decoder, a column decoder, and input / output circuitry, etc. The cell array includes memory cells arranged between a plurality of rows and a plurality of columns. The row decoder is used to activate and deactivate the rows of the cell array, and the column decoder is used to input data to and output data from the cell array. During a write operation, 128-bit data D0' to D127' and 8-bit error correction codes E0 to E7 may be stored in the memory core 870. During a read operation, 128-bit data D0' to D127' and 8-bit error correction codes E0 to E7 may be read from the memory core 870.

[0118] The error determination circuit 890 may determine an error in the data D0' to D127' by using the syndromes S0 to S7 and generate error information ERR_INF. The error information ERR_INF may include information indicating whether the data includes an error and how many errors the data includes. That is, the error determination circuit 890 may include a circuit that does not participate in the error correction operation of the error correction code decoder 833 but generates the error information ERR_INF by using the syndromes S0 to S7 generated during the error correction operation of the error correction code decoder 833. The error information ERR_INF may indicate whether an error has occurred in the data D0 to D127 and whether the error is a correctable error or an uncorrectable error. During each read operation, the error information ERR_INF may be transmitted to the memory controller through the error information transmission circuit 895. The error information ERR_INF may be output through a pad of the memory 800 that is not used during the read operation. For example, the data mask inversion (DMI) pad of the memory 800 is not used during the read operation, and the error information transmission circuit 895 may transmit the error information ERR_INF through the DMI pad.

[0119] As described below, the configuration of the parity check matrix and the error determination method of the error determination circuit 890 may be simple and fast.

[0120] Figure 9 illustrates the Figure 8 parity check matrix used by the error correction code encoder 831 and the error correction code decoder 833 of the ECC engine 830 in

[0121] The parity check matrix may include a (number of bits of the error correction code) × (number of bits of the error correction code + number of bits of the data) matrix. Since the error correction codes E0 to E7 include 8 bits and the data D0 to D127 include 128 bits, the parity check matrix may include an 8×136 matrix (= 8×(8 + 128) matrix). Hereinafter, in the parity check matrix, the part corresponding to CB0 to CB3 is referred to as the upper index, and the part corresponding to CB4 to CB7 is referred to as the lower index.

[0122] Reference Figure 9 As can be seen, all column vectors in the upper index part of data D0 to D127 in the parity check matrix have odd weights. It can be seen that the column vector in the upper index part of data D0 is '0001', whose weight is odd and has an odd number of 1s. The column vector in the upper index part of data D65 is '1011', whose weight is odd and has an odd number of 1s.

[0123] In the case where the ECC engine 830 uses the parity check matrix as shown in Figure 9 When an error occurs in data D36', the upper index parts S0 to S3 of the syndrome S0 to S7 are generated as '0100'. When an error occurs in data D64', the upper index parts S0 to S3 of the syndrome are generated as '1110'.

[0124] Figure 10 is a matrix in which the columns of the parity check matrix according to an embodiment of the present disclosure are reduced to 2:1. Figure 9 The matrix in

[0125] Figure 10 can be the sum of the column vectors of adjacent data in Figure 9 For example, Figure 10 the column vector '00110000' of D0D1 in Figure 9 can be the sum of the column vector '00010000' of D0 and the column vector '00100000' of D1 in Figure 10 The column vector '01010111' of D66D67 in Figure 9 can be the sum of the column vector '11101111' of D66 and the column vector '10111000' of D67 in

[0126] Reference Figure 10 In the case where the ECC engine 830 uses the parity check matrix as shown in Figure 9 As can be seen, when an error occurs in adjacent 2-bit data D4' and D5', the upper index parts S0 to S3 of the syndrome S0 to S7 are generated as the same '0011' as D4D5 in the matrix of Figure 10 In addition, when an error occurs in adjacent 2-bit data D34' and D35', the upper index parts S0 to S3 of the syndrome S0 to S7 are generated as the same '1100' as D34D35 in the matrix of Figure 10 It can also be seen that when an error occurs in adjacent 2-bit data D66' and D67', the upper index parts S0 to S3 of the syndrome S0 to S7 are generated as the same as Figure 10The same '0101' as D66D67 in the matrix of Figure 10 is generated for D104D105 in the matrix of

[0127] Figure 11 FIG. is an example of the operation of the error determination circuit 890 when the ECC engine 830 uses the Figure 9 parity check matrix in Figure 8 FIG.

[0128] When the ECC engine 830 uses the Figure 9 parity check matrix in FIG., the error determination circuit 890 can determine the occurrence of an error by using only the upper index portions S0 to S3 of the syndrome S0 to S7.

[0129] When S0 to S3 are '0000', the error determination circuit 890 can determine that there is no error in the data D0' to D127'. In this case, the error determination circuit 890 can generate the error information ERR_INF as no error (NE) indicating no error.

[0130] When S0 to S3 have an odd weight, that is, when the number of 1s in S0 to S3 is odd, the error determination circuit 890 can determine that a 1-bit error has occurred in the data D0' to D127'. Since Figure 9 all column vectors of the upper index portion of the data D0 to D127 in the parity check matrix of

[0131] have an odd weight, such a determination can be made. Figure 10

[0132] When S0 to S3 are one of '0011', '1100', '0101', and '1010', the error determination circuit 890 can determine that an error has occurred in two adjacent bits of the data D0' to D127'. It can be seen that '0011', '1100', '0101', and '1010' are the same as the

[0133] values of the upper index portion of the data in the matrix ofWhen the values of S0 to S3 are different from the cases mentioned above, since this means that an error has occurred in data D0' to D127' and the error is uncorrectable, the error determination circuit 890 can determine that an uncorrectable error has occurred in data D0' to D127'. Subsequently, the error determination circuit 890 can generate an error message ERR_INF as an uncorrectable error (UE) indicating that an uncorrectable error has occurred.

[0134] When the ECC engine 830 uses Figure 9 the parity check matrix in, there may be an advantage that the error determination circuit 890 can determine the error by using only the upper index part of the syndrome. When the form of the error correction codes E0 to E7 in the parity check matrix is an identity matrix, the operation of the ECC engine 830 can be simpler. However, in Figure 9 the parity check matrix in, since the form of the error correction codes E0 to E7 part is not in the form of an identity matrix, the operation of the ECC engine 830 may be difficult to simplify and may become more complex.

[0135] The following describes a parity check matrix that makes the error determination of the error determination circuit 890 more complex but enables the simplification of the operation of the ECC engine.

[0136] Figure 12 is a diagram illustrating another parity check matrix used by the error correction code encoder 831 and the error correction code decoder 833 of the ECC engine 830 in Figure 8 according to an embodiment of the present disclosure.

[0137] Referring to Figure 12 , it can be seen that most of the column vectors of the upper indices CB0 to CB3 of data D0 to D127 in the parity check matrix have an odd weight, but the column vectors of some data do not have an odd weight but an even weight. That is, the column vectors of the upper indices of data D2 to D31 and D34 to D127 have an odd weight, but the column vectors of the upper indices of data D0, D1, D32, and D33 have an even weight '0000'.

[0138] It can be seen that by allowing the column vectors of the upper indices of data D0, D1, D32, and D33 to have an even weight, Figure 12 the error correction codes E0 to E7 part of the parity check matrix in has the form of an identity matrix. When the error correction codes E0 to E7 part in the parity check matrix has the form of an identity matrix, the operation of the ECC engine 830 can be more simple.

[0139] Figure 12 The parity check matrix in can be configured such that the error correction codes E0 to E7 part has the form of an identity matrix, and the column vectors of the upper indices of data D0 to D127 have the maximum odd weight.

[0140] Figure 13 is a matrix in which the number of columns of the parity-check matrix according to an embodiment of the present disclosure is reduced by 2:1. Figure 12 The matrix in

[0141] Figure 13 can be the sum of column vectors of adjacent data in Figure 12 For example, Figure 13 the column vector '00001111' of D0D1 in Figure 12 can be the sum of the column vector '00001010' of D0 and the column vector '00000101' of D1 in Figure 13 The column vector '01010111' of the column vector D66D67 in Figure 12 can be the sum of the column vector '11101111' of D66 and the column vector '10111000' of D67 in

[0142] Refer to Figure 12 and Figure 13 , since the column vectors of the upper indices of the data D2 to D31 and D34 to D127 are the same as the column vectors in Figure 9 and Figure 10 , the error determination of the data D2' to D31' and D34' to D127' can be performed in the same manner as Figure 11 . That is, when the upper-index portions S0 to S3 of the syndromes S0 to S7 are '0000', it can be determined that there are no errors in at least the data D2' to D31' and D34' to D127'. When the upper-index portions S0 to S3 have an odd weight, it can be determined that a 1-bit error has occurred in the data D2' to D31' and D34' to D127'. When the upper-index portions S0 to S3 of the syndromes S0 to S7 have one of the values '0011', '1100', '0101', or '1010', it can be determined that two adjacent bits in the data D2' to D31' and D34' to D127' have an error.

[0143] However, in the parity-check matrix in Figure 12 , since the column vectors of the upper indices of the data D0, D1, D32, and D33 do not have an odd weight, it is difficult to simply determine the error only by checking the upper-index portions S0 to S3 of the syndromes S0 to S7 as described above when an error occurs in the data D0, D1, D32, and D33.

[0144] Figure 14 is a diagram illustrating the operation of the error determination circuit 890 when the ECC engine 830 uses the parity-check matrix in Figure 12 according to an embodiment of the present disclosure. Figure 8

[0145] In Figure 12 the parity check matrix of, all column vectors of the upper indices of data D0 to D127 do not have odd weights, and the column vectors of the upper indices of data D0, D1, D32, and D33 have even weights. Therefore, the error determination circuit 890 needs to use not only the upper index portions S0 to S3 of the syndrome S0 to S7 but also the lower index portions S4 to S7 of the syndrome S0 to S7.

[0146] When S0 to S7 is '00000000', the error determination circuit 890 can determine that there is no error in data D0' to D127'. In this case, the error determination circuit 890 can generate the error information ERR_INF as no error (NE) indicating no error.

[0147] When S0 to S3 have odd weights, that is, when the number of 1s in S0 to S3 is odd, the error determination circuit 890 can determine that a 1-bit error has occurred in data D2' to D31' and D34' to D127'. To determine that a 1-bit error has occurred in data D2' to D31' and D34' to D127', only S0 to S3 can be used, and S4 to S7 do not need to be used.

[0148] When S0 to S7 is one of '00001010', '00000101', '00001110', and '00000111', the error determination circuit 890 can determine that a 1-bit error has occurred in data D0', D1', D32', and D33'.

[0149] When S0 to S3 is one of '0011', '1100', '0101', and '1010', the error determination circuit 890 can determine that two adjacent bits in data D2' to D31' and D34' to D127' have an error. It can be seen that '0011', '1100', '0101', and '1010' are the same as the values of the upper index portions of data D2' to D31' and D34' to D127' in the matrix of Figure 13 To determine that two adjacent bits in data D2' to D31' and D34' to D127' have an error, only S0 to S3 can be used, and S4 to S7 do not need to be used.

[0150] When S0 to S7 is one of '00001111' and '00001001', the error determination circuit 890 can determine that two adjacent bits in data D0', D1', D32', and D33' have an error.

[0151] When the error determination circuit 890 determines that a 1-bit error has occurred in the data D0' to D127', and when the error determination circuit 890 determines that an error has occurred in two adjacent bits, the error determination circuit 890 may generate an error message ERR_INF as a correctable error (CE) indicating that a correctable error has occurred.

[0152] When the values of S0 to S7 are different from the previously mentioned cases, since this means that an error has occurred in the data D0' to D127' and the error is uncorrectable, the error determination circuit 890 may determine that an uncorrectable error has occurred in the data D0' to D127'. Subsequently, the error determination circuit 890 may generate an error message ERR_INF as an uncorrectable error (UE) indicating that an uncorrectable error has occurred.

[0153] Figure 15 is a configuration diagram of the error determination circuit 890 that operates as shown in Figure 14 accordance with an embodiment of the present disclosure.

[0154] Referring to Figure 15 , the error determination circuit 890 may include a first syndrome decoding circuit 1510, a second syndrome decoding circuit 1520, and an error message generation circuit 1530.

[0155] The first syndrome decoding circuit 1510 may generate a first preliminary 1-bit error signal 1b_ERR_PRE1 and a first preliminary 2-bit error signal 2b_ERR_PRE1 by decoding the upper index part S0 to S3 of the syndromes S0 to S7. When S0 to S3 have an odd weight, the first syndrome decoding circuit 1510 may activate the first preliminary 1-bit error signal 1b_ERR_PRE1. When S0 to S3 are one of Figure 14 '0011', '1100', '0101', and '1010' as shown, the first syndrome decoding circuit 1510 may activate the first preliminary 2-bit error signal 2b_ERR_PRE1. It can be said that the first syndrome decoding circuit 1510 determines the cases where a 1-bit error has occurred in the data D2' to D31', D34' to D127' and the cases where two adjacent bits in the data D2' to D31', D34' to D127' have an error.

[0156] The second syndrome decoding circuit 1520 may generate a second preliminary 1-bit error signal 1b_ERR_PRE2, a second preliminary 2-bit error signal 2b_ERR_PRE2, and a no-error signal No ERR by decoding the syndromes S0 to S7. When the syndromes S0 to S7 are as Figure 14When one of '00001010', '00000101', '00001110', and '00000111' as shown, the second syndrome decoding circuit 1520 can activate the second preliminary 1-bit error signal 1b_ERR_PRE2. When the syndromes S0 to S7 are one of '00001111' and '00001001' as shown in Figure 14 the second syndrome decoding circuit 1520 can activate the second preliminary 2-bit error signal 2b_ERR_PRE2. When the syndromes S0 to S7 are '00000000' as shown in Figure 14 the second syndrome decoding circuit 1520 can generate a no-error signal No ERR.

[0157] When the no-error signal No ERR is activated, the error information generation circuit 1530 can generate an error information as "no error" (ERR_INF = NE). When one or more of the first preliminary 1-bit error signal 1b_ERR_PRE1, the second preliminary 1-bit error signal 1b_ERR_PRE2, the first preliminary 2-bit error signal 2b_ERR_PRE1, and the second preliminary 2-bit error signal 2b_ERR_PRE2 are activated, the error information generation circuit 1530 can generate an error information as "correctable error" (ERR_INF = CE). When the no-error signal No ERR, the first preliminary 1-bit error signal 1b_ERR_PRE1, the second preliminary 1-bit error signal 1b_ERR_PRE2, the first preliminary 2-bit error signal 2b_ERR_PRE1, and the second preliminary 2-bit error signal 2b_ERR_PRE2 are all deactivated, the error information generation circuit 1530 can generate an error information as "uncorrectable error" (ERR_INF = UE).

[0158] Although embodiments according to the technical idea of the present disclosure have been described above with reference to the drawings, this is only for describing embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the above embodiments. Without departing from the technical idea of the present disclosure defined by the appended claims, those of ordinary skill in the art to which the present disclosure pertains can make various types of substitutions, modifications, and changes to the embodiments, and it should be understood that these substitutions, modifications, and changes belong to the scope of the present disclosure. In addition, these embodiments can also be combined to form additional embodiments.

Claims

1. A memory, comprising: Memory core; an ECC engine, which: generates an error correction code by using write data during an encoding operation, the error correction code to be stored in the memory core together with the write data; and corrects errors of read data read from the memory core using the error correction code read from the memory core during a decoding operation, the ECC referring to an error correction code; and An error determination circuit that: during the decoding operation, determines that a 1-bit error exists when an upper index portion of a syndrome generated by the ECC engine has an odd weight; and determines that a correctable 2-bit error exists when the upper index portion of the syndrome is one of a predetermined even weight pattern.

2. The memory according to claim 1, wherein: The ECC engine performs the encoding operation and the decoding operation by using a check matrix, wherein all upper index parts corresponding to the data in the check matrix have odd weights, and Wherein, the exclusive OR of the upper index parts of adjacent data pairs in the check matrix has one of the predetermined even weight patterns.

3. The memory according to claim 1, wherein: the error determination circuit generates error information by using a result of the determination, and The error information is transmitted to a memory controller.

4. The memory according to claim 1, wherein: When all upper index parts of the syndrome are 0, the error determination circuit determines that there is no error.

5. The memory according to claim 1, wherein: The syndrome includes the upper index part and the lower index part, and The upper index part is the high bit of the syndrome, and the lower index part is the low bit of the syndrome.

6. A memory comprising: Memory core; an ECC engine, which: generates an error correction code by using write data during an encoding operation, the error correction code to be stored in the memory core together with the write data; and corrects errors of read data read from the memory core using the error correction code read from the memory core during a decoding operation, the ECC referring to an error correction code; and An error determination circuit that: during the decoding operation, determines that a 1-bit error exists when an upper index portion of a syndrome generated by the ECC engine has an odd weight; and determines that a 1-bit error exists when the upper index portion of the syndrome has a specific even weight and a lower index portion matches one of the predetermined first patterns.

7. The memory according to claim 6, wherein: During the decoding operation, the error determination circuit determines that a correctable 2-bit error exists when the upper index portion of the syndrome has an even weight that matches one of the predetermined second patterns; And when the upper index portion of the syndrome is a predetermined third pattern and the lower index portion matches one of predetermined fourth patterns, the error determination circuit determines that a correctable 2-bit error exists.

8. The memory according to claim 6, wherein: The ECC engine performs the encoding operation and the decoding operation by using a check matrix, and Wherein, 90% or more of the upper index part corresponding to the data in the check matrix has odd weights, and the rest of the check matrix has the specific even weights.

9. The memory according to claim 7, wherein: the error determination circuit generates error information by using a result of the determination, and The error information is transmitted to a memory controller.

10. The memory according to claim 7, wherein: When all upper index parts and all lower index parts of the syndrome are 0, the error determination circuit determines that there is no error.

11. The memory according to claim 7, wherein: The upper index part is the high bit position of the syndrome, and the lower index part is the low bit position of the syndrome.

12. The memory according to claim 7, wherein: The error determination circuit comprises: A first syndrome decoding circuit, which: generates a first preliminary 1-bit error signal and a first preliminary 2-bit error signal by decoding the upper index portion of the syndrome; a second syndrome decoding circuit, which generates a second preliminary 1-bit error signal, a second preliminary 2-bit error signal, and a no-error signal by decoding the upper index portion of the syndrome and the lower index portion of the syndrome; and An error information generating circuit, which: generates the error information indicating "no error" when the no error signal is activated; generates the error information indicating "correctable error" when one or more of the first preliminary 1-bit error signal, the second preliminary 1-bit error signal, the first preliminary 2-bit error signal and the second preliminary 2-bit error signal are activated; and generates the error information indicating "uncorrectable error" when the no error signal, the first preliminary 1-bit error signal, the second preliminary 1-bit error signal, the first preliminary 2-bit error signal and the second preliminary 2-bit error signal are all deactivated.

13. A memory comprising: Memory core; An ECC engine that performs encoding operations and decoding operations, wherein the ECC refers to error correction code; as well as Error determination circuit, Wherein, the ECC engine: During the encoding operation, Receive write data; generating an error correction code using the write data; and providing the write data and the error correction code to the memory core for storage, During the decoding operation, Reading read data and the error correction code from the memory core; decoding the read data using the error correction code; and generating a syndrome value for the decoded read data, the syndrome value comprising an upper portion and a lower portion, and wherein the error determination circuit: Based on a combination of the bit patterns and bit weights of the upper portion and the lower portion of the syndrome value, it is determined whether the decoded read data includes a 1-bit error or a 2-bit error.

14. The memory according to claim 13, wherein: When the weight of the bits of the upper portion of the syndrome value is an odd number, the error determination circuit determines that the decoded read data includes the 1-bit error.

15. The memory according to claim 13, wherein: When the bits of the upper portion of the syndrome value have one of the patterns of (0011), (1100), (0101), (1010), the error determination circuit determines that the decoded read data includes the 2-bit error.

16. The memory according to claim 13, wherein: When the bits of the upper portion of the syndrome value have the pattern (0000) and the bits of the lower portion of the syndrome value have one of the patterns (1010), (0101), (1110), (0111), the error determination circuit determines that the decoded read data includes the 1-bit error.

17. The memory according to claim 13, wherein: When the bits of the upper portion of the syndrome value have the pattern (0000) and the bits of the lower portion of the syndrome value have one of the patterns (1111), (1001), the error determination circuit determines that the decoded read data includes the 2-bit error.

18. The memory according to claim 13, wherein: The error determination circuit generates error information based on the determination and transmits the error information to the memory controller.

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