Chip packaging method and chip packaging device
By welding grains on both sides of the substrate and welding the second grains using flip-flop process, the problem of difficult to miniaturize and apply smaller chips in traditional packaging technology is solved, and the miniaturization of the packaging structure and the improvement of product yield is achieved.
Patent Information
- Application Number
- CN202510196110.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-21
- Publication Date
- 2025-05-27
AI Technical Summary
Traditional chip packaging technology is difficult to achieve miniaturization, especially in smaller chip packaging, and surface mount technology has poor soldering effect on chips below 150um, affecting product yield.
By welding the first and second grains on both sides of the substrate, and welding the second grains using flip-flop process, the packaging area of the grains is reduced, and the packaging of smaller chips is suitable. At the same time, the chip is clamped by the clamp to maintain flatness, and the welding effect is optimized.
The packaging structure is miniaturized, suitable for packaging of smaller chips, improve product yield, and reduce the impact on substrate flatness through optimized welding process.
Smart Images
Figure CN120048749A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip packaging, and in particular, to a chip packaging method and a chip packaging device. Background Art
[0002] In traditional packaging, limited by the physical stacking limit of chips, electrical interconnection between SoC (System on Chip) chips and Memory (memory chips) needs to be achieved through long bonding leads and substrate traces. As the requirements for power consumption and electrical performance become higher and higher, new interconnection methods are needed to meet the performance requirements. As the product function requirements increase, the capacity of Memory chips becomes larger and the chip size becomes larger. The product thickness and area are positively correlated with the number of chips stacked inside the plastic package and the area of the chips laid flat, respectively. Placing one or more SoC chips in the limited space of the packaging plastic package and stacking Memory chips on it will increase the product thickness, and laying Memory chips beside it will increase the product area, seriously restricting the miniaturization development of the product.
[0003] To address the product miniaturization problem, the prior art is to solder the components inside the package to the back of the substrate through surface mount technology to reduce the package area and the volume of the package structure. However, the soldering effect of surface mount technology on chips / components with a size below 150um pitch is poor, resulting in the inability to solder chips / components with a size below 150um pitch, or seriously affecting the product yield. In addition, since the second soldering on the back of the substrate is affected by the first soldering process, the soldering effect on the back of the substrate is further deteriorated, affecting the product yield. Summary of the Invention
[0004] The purpose of this application is to provide a chip packaging method and a chip packaging device, which can achieve the miniaturization of the packaging structure while being applicable to the packaging of smaller-sized chips, and improve the product yield.
[0005] In a first aspect, an embodiment of this application provides a chip packaging method, including: clamping a target chip between a first clamping plate and a second clamping plate to improve the flatness of the target chip. The target chip includes a substrate, a first die soldered on the substrate, and a packaging layer covering the first die. The substrate includes a first substrate surface and a second substrate surface arranged opposite to each other. The first die and the packaging layer are arranged on the first substrate surface. The second clamping plate includes a main body portion and a hollow portion arranged on the main body portion. The second clamping plate abuts against the second substrate surface to clamp the target chip; soldering a second die at a position corresponding to the hollow portion on the second substrate surface based on the flip-chip process.
[0006] Compared with the related art, in the chip packaging method provided by the embodiments of the present application, for a target chip that has been welded and packaged with a first die, a second die is welded on a second substrate surface opposite to the first substrate surface where the first die is welded on the substrate, so as to realize welding the first die and the second die on two sides of the substrate respectively, reduce the packaging area of the first die and the second die, and the reduction of the packaging area can further reduce the volume of the entire packaging structure, realizing the miniaturization of the packaging structure; since the second die is welded on the second substrate surface based on the flip-chip process, the flip-chip process can be applied to the welding of smaller-sized dies, so that it can be applied to the packaging of smaller-sized chips; at the same time, when welding the second die, the target chip is clamped by a first clamping plate and a second clamping plate, so that the target chip can be kept flat, reducing the influence on the flatness of the substrate surface during the process of welding the first die on the substrate, making the second substrate surface flatter when welding the second die, and the flatter second substrate surface can further optimize the welding effect of the second die and improve the product yield.
[0007] In an optional embodiment, the second die includes a bump array welded to the second substrate surface. After the second die is welded to the position corresponding to the hollow part on the second substrate surface based on the flip-chip process, the chip packaging method further includes: arranging an insulating glue outside the bump array. Since the distance between the bumps in the bump array arranged on the die is extremely small, after the insulating glue is arranged outside the bump array, under the influence of capillary action, the insulating glue arranged outside the bump array will penetrate into the bump array to fill the gaps in the bump array, completing the packaging and protection of the bump array on the second die. Since the process of arranging the insulating glue outside the bump array does not directly contact the bump array on the second die, it will not cause direct damage to the bump array on the second die, reducing the influence of the packaging process on the second die, and can further improve the product yield.
[0008] In an optional embodiment, the chip packaging method further includes: clamping the substrate between a first clamping plate and a second clamping plate to improve the flatness of the substrate, the second clamping plate abuts against the first substrate surface, and the first clamping plate abuts against the second substrate surface to clamp the substrate; welding the first die to the position corresponding to the hollow part on the first substrate surface based on the flip-chip process; forming the packaging layer on the first substrate surface to form the target chip. During the process of welding the first die on the substrate, the substrate is also clamped between the first clamping plate and the second clamping plate, which can improve the flatness of the first substrate surface when welding the first die, improve the welding effect of the first die, and further improve the product yield.
[0009] In an alternative embodiment, forming the encapsulation layer on the first substrate surface includes: preparing an encapsulation body covering the first die on the first substrate surface; and planarizing a surface of the encapsulation body away from the substrate to form the encapsulation layer. Planarizing the surface of the encapsulation body away from the substrate can improve the stability of clamping the target chip by the first clamping plate and the second clamping plate during the subsequent welding of the second die, enhance the welding effect of the second die, and further improve the product yield.
[0010] In an alternative embodiment, forming the encapsulation layer on the first substrate surface includes: preparing an encapsulation body covering the first die on the first substrate surface; and grinding a surface of the encapsulation body away from the substrate until a surface of the first die away from the substrate is exposed outside the encapsulation body to form the encapsulation layer. Grinding the encapsulation body until the surface of the first die away from the substrate is exposed outside the encapsulation body can reduce the thickness of the encapsulation body, expose the first die, and improve the heat dissipation effect of the first die.
[0011] In an alternative embodiment, before welding the first die at a position corresponding to the hollow portion on the first substrate surface based on the flip-chip process, the chip packaging method further includes: drilling a hole in the substrate in a direction perpendicular to the first substrate surface to form a vertical through hole penetrating the first substrate surface and the second substrate surface; and filling a conductor in the vertical through hole, where the conductor forms a first welding point for welding with the first die on the first substrate surface and a second welding point for welding with the second die on the second substrate surface. Directly drilling a hole in the substrate to form a vertical through hole penetrating the first substrate surface and the second substrate surface, and filling a conductor in the through hole to form a first welding point for welding with the first die on the first substrate surface and a second welding point for welding with the second die on the second substrate surface can more conveniently realize the connection between the first die and the second die and reduce the packaging cost.
[0012] In a second aspect, an embodiment of the present application provides a chip packaging device, including: a first clamping plate and a second clamping plate, where the first clamping plate and the second clamping plate are used to clamp a target chip to improve the flatness of the target chip, the second clamping plate includes a main body portion and a hollow portion provided on the main body portion, the target chip includes a substrate, a first die welded on the substrate, and an encapsulation layer covering the first die, the substrate includes a first substrate surface and a second substrate surface arranged opposite to each other, the first die and the encapsulation layer are arranged on the first substrate surface, and when the first clamping plate and the second clamping plate are used to clamp the target chip, the second clamping plate abuts against the second substrate surface; and a welding member, where the welding member is used to hold a second die and weld the second die at a position corresponding to the hollow portion on the second substrate surface based on the flip-chip process.
[0013] Compared with the related art, in the chip packaging device provided by the embodiments of the present application, for a target chip that has been welded and packaged with a first die, a welding component is arranged to weld a second die on a second substrate surface opposite to the first substrate surface where the first die is welded on the substrate, so as to realize welding the first die and the second die on two sides of the substrate respectively, reduce the packaging area of the first die and the second die, and the reduction of the packaging area can further reduce the volume of the entire packaging structure, realizing the miniaturization of the packaging structure; since the welding component can weld the second die on the second substrate surface through the flip-chip process, and the flip-chip process is applicable to the welding of smaller-sized dies, so that it can be applicable to the packaging of smaller-sized chips; meanwhile, a first clamping plate and a second clamping plate are arranged, and the target chip is clamped by the first clamping plate and the second clamping plate when welding the second die, so that the target chip can be kept flat, reducing the influence on the flatness of the substrate surface during the process of welding the first die on the substrate, making the second substrate surface more flat when the welding component welds the second die, and the more flat second substrate surface can further optimize the welding effect of the second die and improve the product yield.
[0014] In an alternative embodiment, the second die includes a bump array welded to the second substrate surface, and the chip packaging device further includes: a glue coating structure for arranging an insulating glue outside the bump array. Since the distance between the bumps in the bump array arranged on the die is extremely small, after the glue coating structure arranges the insulating glue outside the bump array, under the influence of capillary action, the insulating glue arranged outside the bump array will penetrate into the bump array to fill the gaps in the bump array, completing the packaging and protection of the bump array on the second die. Since the process of arranging the insulating glue outside the bump array does not directly contact the bump array on the second die, it will not cause direct damage to the bump array on the second die, reducing the influence on the second die during the packaging process, and can further improve the product yield.
[0015] In an alternative embodiment, the chip packaging device further includes: a packaging component including a packaging member and a grinding member, the packaging member is used to prepare and form a package covering the first die on the first substrate surface, and the grinding member is used to grind a surface of the package away from the substrate to form the packaging layer. Arranging the grinding member to grind the surface of the package away from the substrate can, on the one hand, make the surface of the package away from the substrate more flat, improve the stability of clamping the target chip by the first clamping plate and the second clamping plate during the subsequent process of welding the second die, and improve the welding effect of the second die; on the other hand, it can also grind the package until the surface of the first die away from the substrate is exposed outside the package, reducing the thickness of the package, exposing the first die, and improving the heat dissipation effect of the first die.
[0016] In an alternative embodiment, the chip packaging device further includes a drilling assembly, which includes a punching member and a filling member. The punching member is configured to punch holes in the substrate in a direction perpendicular to the first substrate surface, forming vertical through-holes that penetrate the first substrate surface and the second substrate surface. The filling member is configured to fill conductors in the vertical through-holes to form a first welding point for welding with the first die on the first substrate surface and a second welding point for welding with the second die on the second substrate surface. By providing a punching member to directly punch holes in the substrate to form vertical through-holes that penetrate the first substrate surface and the second substrate surface, and providing a filling member to fill conductors in the through-holes to form a first welding point for welding with the first die on the first substrate surface and a second welding point for welding with the second die on the second substrate surface, the connection between the first die and the second die can be achieved more conveniently, reducing the packaging cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments. It should be understood that the following drawings only show some embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other relevant drawings can also be obtained based on these drawings.
[0018] Figure 1 It is a schematic flowchart of the chip packaging method provided in the first embodiment of the present application;
[0019] Figure 2 For Figure 1 it is a schematic cross-sectional structure diagram of the packaging structure corresponding to step S101;
[0020] Figure 3 For Figure 1 it is a schematic cross-sectional structure diagram of the packaging structure corresponding to step S102;
[0021] Figure 4 It is a schematic flowchart of preparing a target chip in the chip packaging method provided in the embodiments of the present application;
[0022] Figure 5 For Figure 4 it is a schematic cross-sectional structure diagram of the packaging structure corresponding to step S201;
[0023] Figure 6 For Figure 4 it is a schematic cross-sectional structure diagram of the packaging structure corresponding to step S202;
[0024] Figure 7 For Figure 4 it is a schematic cross-sectional structure diagram of the packaging structure corresponding to step S203;
[0025] Figure 8 is Figure 4 A schematic cross-sectional structure diagram of another encapsulation structure corresponding to step S203 in
[0026] Figure 9 A schematic flow diagram of the process of drilling holes on a substrate in the chip encapsulation method provided by an embodiment of the present application;
[0027] Figure 10 is Figure 9 A schematic cross-sectional structure diagram of the encapsulation structure corresponding to step S301 in
[0028] Figure 11 is Figure 9 A schematic cross-sectional structure diagram of the encapsulation structure corresponding to step S302 in
[0029] Figure 12 A schematic flow diagram of the chip encapsulation method provided by the second embodiment of the present application;
[0030] Figure 13 is Figure 12 A schematic cross-sectional structure diagram of the encapsulation structure corresponding to step S103 in
[0031] Figure 14 A schematic cross-sectional structure diagram of the encapsulation structure after ball planting;
[0032] Figure 15 A schematic structure diagram of the chip encapsulation device and the target chip provided by the third embodiment of the present application;
[0033] Figure 16 A schematic cross-sectional structure diagram of the glue coating structure in the chip encapsulation device provided by the third embodiment of the present application. Detailed implementation manners
[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and illustrated herein can be arranged and designed in various different configurations.
[0035] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application.
[0036] It should be noted that: Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.
[0037] In addition, terms such as "first" and "second" are only used for distinguishing descriptions and should not be construed as indicating or implying relative importance.
[0038] It should be noted that, without conflict, the features in the embodiments of the present application can be combined with each other.
[0039] Embodiment 1
[0040] Embodiment 1 of the present application provides a chip packaging method, which is applied to the chip packaging device provided in other embodiments of the present application, such as Figure 1 shown, the chip packaging method includes the following steps:
[0041] Step S101: Clamp the target chip between the first clamping plate and the second clamping plate to improve the flatness of the target chip.
[0042] Please refer to Figure 2 , in this step, the target chip 100 is a chip structure that has been welded with the first die and encapsulates the first die, and it includes a substrate 10, a first die 20 welded on the substrate 10, and an encapsulation layer 30 that covers the first die 20 and encapsulates the first die 20. Among them, the substrate 10 includes a first substrate surface 11 and a second substrate surface 12 that are oppositely arranged and used for welding dies. The first die 20 and the encapsulation layer 30 are arranged on the first substrate surface 11, and the second substrate surface 12 is used for welding the second die.
[0043] Furthermore, the chip packaging device includes a first clamping plate 40 and a second clamping plate 50. The first clamping plate 40 and the second clamping plate 50 are flat clamping plates, that is, the surfaces of the first clamping plate 40 and the second clamping plate 50 are both flat. In this step, after the target chip 100 is clamped between the two flat clamping plates of the first clamping plate 40 and the second clamping plate 50, under the action of the clamping force of the first clamping plate 40 and the second clamping plate 50, the warpage of the target chip 100 can be reduced, thereby improving the flatness of the target chip 100.
[0044] In this step, when the target chip 100 is clamped between the first clamping plate 40 and the second clamping plate 50, the second clamping plate 50 abuts against the second substrate surface 12, and the first clamping plate 40 abuts against the surface 13 on the side of the target chip 100 away from the second substrate surface 12. Among them, the second clamping plate 50 includes a main body portion 51 and a hollow portion 52 provided on the main body portion 51. The main body portion 51 abuts against the second substrate surface 12 and clamps the target chip 100, reducing the warpage of the target chip 100 and improving the flatness of the second substrate surface 12. The hollow portion 52 exposes a part of the surface of the second substrate surface 12, facilitating the subsequent welding of the second die on the second substrate surface 12.
[0045] Step S102: Weld the second die at the position corresponding to the hollow portion on the second substrate surface based on the flip-chip process.
[0046] In this step, the flip-chip process, i.e., the Flip Chip process, is a soldering process used to solder structures such as chips and dies. It places the active surface of the chip / die structure downward and directly connects the solder bumps on the chip / die to the corresponding pads on the substrate or package carrier, achieving electrical connection and mechanical fixation between the chip / die and the external circuit. Under this process, the chip / die can be directly connected to the substrate without occupying additional space for wire bonding, enabling more functions to be integrated within a smaller package area, achieving a smaller package size and higher integration density.
[0047] Please refer to Figure 3 , in this step when soldering the second die 60, the second die 60 is directly soldered onto the position on the second substrate surface 12 corresponding to the hollow portion 52 and exposed by the hollow portion 52 based on the flip-chip process.
[0048] Compared with the related art, in the chip packaging method provided by the first embodiment, for the target chip 100 that has been soldered and packaged with the first die 20, the second die 60 is soldered onto the second substrate surface 12 opposite to the first substrate surface 11 where the first die 20 is soldered on the substrate 10, realizing soldering of the first die 20 and the second die 60 on both sides of the substrate 10, reducing the packaging area of the first die 20 and the second die 60. The reduction in the packaging area can further reduce the volume of the entire packaging structure, achieving miniaturization of the packaging structure; since the second die 60 is soldered onto the second substrate surface 12 based on the flip-chip process, the flip-chip process can be applied to soldering of smaller-sized dies, thus enabling packaging of smaller-sized chips; meanwhile, when soldering the second die 60, the target chip 100 is clamped by the first clamping plate 40 and the second clamping plate 50, which can keep the target chip 100 flat, reducing the impact on the flatness of the surface of the substrate 10 during the process of soldering the first die 20 onto the substrate 10, making the second substrate surface 12 flatter when soldering the second die 60. The flatter second substrate surface 12 can further optimize the soldering effect of the second die 60 and improve the product yield.
[0049] Furthermore, in different embodiments of the present application, the target chip 100 for soldering the second die 60 in step S101 can specifically be a chip that has been fabricated in other processing technologies, and in step S101, secondary processing and packaging are directly performed on the fabricated target chip 100, or it can also be the target chip 100 obtained by soldering the substrate 10 and the first die 20 in the chip packaging method provided by the embodiments of the present application. In some embodiments of the present application, as Figure 4 shown, the preparation of the target chip 100 before step S101 can specifically include the following steps:
[0050] Step S201: Clamp the substrate between the first clamping plate and the second clamping plate.
[0051] Please refer to Figure 5 , in this step, the substrate 10 includes a first substrate surface 11 and a second substrate surface 12. When clamping the substrate 10 between the first clamping plate 40 and the second clamping plate 50, the second clamping plate 50 abuts against the first substrate surface 11, and the first clamping plate 40 abuts against the second substrate surface 12 to clamp the substrate 10. After the substrate 10 is clamped between the two clamping plates of the first clamping plate 40 and the second clamping plate 50, under the action of the clamping force of the first clamping plate 40 and the second clamping plate 50, the warping of the substrate 10 can be reduced, thereby improving the flatness of the substrate 10.
[0052] Step S202: Based on the flip-chip process, weld the first die at the position corresponding to the hollowed-out portion on the first substrate surface.
[0053] Please refer to Figure 6 , in this step of welding the first die 20, the first die 20 is directly welded on the first substrate surface 11 at a position corresponding to the hollowed-out portion 52 and exposed by the hollowed-out portion 52 based on the flip-chip process.
[0054] Step S203: Form a packaging layer on the first substrate surface to form a target chip.
[0055] Please refer to Figure 7 , in this step, after the first die 20 is welded, a package body 31 covering the first die 20 is preliminarily prepared on the first substrate surface 11 to realize the encapsulation of the first die 20. Subsequently, the package body 31 can be processed accordingly as needed to form the packaging layer 30, thereby preparing the target chip 100 in the foregoing step S101.
[0056] Specifically, forming the package body 31 on the first substrate surface 11 to cover the first die 20 can specifically be placing the substrate 10 welded with the first die 20 in a packaging mold and filling the packaging mold with a packaging material to form the package body 31.
[0057] It can be understood that the foregoing is only an example of a specific method for forming in some embodiments of the present application, and after removing the packaging mold, the target chip 10 in the foregoing step S101 can be formed. In some other embodiments of the present application, the package body 31 can also be formed in other ways.
[0058] Specifically, in some embodiments of the present application, subsequently processing the package body 31 as needed to form the packaging layer 30 can specifically be heating, baking, etc. the packaging layer 30, and further curing the package body 31 to form the packaging layer 30.
[0059] Alternatively, in some other embodiments of the present application, corresponding processing may be performed on the encapsulation body 31 as needed to form the encapsulation layer 30, which may also be planarizing the surface of the encapsulation body 31 away from the substrate 10. By planarizing the surface of the encapsulation body 31 away from the substrate 10, the stability of clamping the target chip 100 by the first clamping plate 40 and the second clamping plate 50 during the subsequent welding of the second die 60 can be improved, the welding effect of the second die 60 can be enhanced, and further the product yield can be improved.
[0060] Among them, planarizing the surface of the encapsulation body 31 away from the substrate 10 may specifically be grinding the surface of the encapsulation body 31 away from the substrate 10, so as to improve the flatness of the surface of the encapsulation body 31 away from the substrate 10 through grinding. In different embodiments of the present application, during the process of improving the flatness of the surface of the encapsulation body 31 away from the substrate 10 by grinding, the amount of the encapsulation body 31 ground away during the grinding of the encapsulation body 31 can also be controlled as needed. For example, in some embodiments of the present application, as Figure 8 shown, specifically, the surface of the encapsulation body 31 away from the substrate 10 may be ground until the surface 21 of the first die 20 away from the substrate 10 is exposed outside the encapsulation body 31. Grinding the encapsulation body 31 until the surface 21 of the first die 20 away from the substrate 10 is exposed outside the encapsulation body 31 can reduce the thickness of the encapsulation body 30, expose the first die 20, and the exposed first die 20 can dissipate heat better, improving the heat dissipation effect of the first die 20.
[0061] In the process of welding the first die 20 on the substrate 10 in the embodiments of the present application, the substrate 10 is also clamped between the first clamping plate 40 and the second clamping plate 50, which can improve the flatness of the first substrate surface 11 when welding the first die 20, enhance the welding effect of the first die 20, and further improve the product yield.
[0062] Furthermore, in some embodiments of the present application, if it is necessary to connect the first die 20 and the second die 60, as Figure 9 shown, before performing the foregoing step S201, the chip encapsulation method provided by the embodiments of the present application may further include:
[0063] Step S301: Punch holes in the substrate along a direction perpendicular to the first substrate surface to form vertical through holes penetrating the first substrate surface and the second substrate surface.
[0064] Please refer to Figure 10, in this step, when drilling a vertical through-hole 80 penetrating the first substrate surface 11 and the second substrate surface 12 in the substrate 10, since the subsequent vertical through-hole 80 needs to be used to connect the first die 20 and the second die 60, and the first die 20 and the second die 60 are welded corresponding to the hollowed-out portion 52, in this step, holes can be drilled at the position on the substrate 10 opposite to the hollowed-out portion 52 based on the hollowed-out portion 52, so as to facilitate the subsequent welding of the first die 20 and the second die 60.
[0065] Step S302: Fill the vertical through-hole with a conductor, and the conductor forms a first welding point for welding with the first die on the first substrate surface and a second welding point for welding with the second die on the second substrate surface.
[0066] Please refer to Figure 11 , in this step, the vertical through-hole 80 penetrates the first substrate surface 11 and the second substrate surface 12. Fill the vertical through-hole 80 with a conductor 90, and the conductor 90 can penetrate the first substrate surface 11 and the second substrate surface 12 to connect the first die 20 welded on the first substrate surface 11 and the second die 60 welded on the second substrate surface 12 respectively. Among them, the conductor 90 filled in the vertical through-hole 80 forms a first welding point 91 for welding with the first die 20 on the first substrate surface 11 and a second welding point 92 for welding with the second die 60 on the second substrate surface 12. The first welding point 91 is the surface of the conductor 90 close to the first substrate surface 11, and the second welding point 92 is the surface of the conductor 90 close to the second substrate surface 12.
[0067] In the embodiment of the present application, by directly drilling a vertical through-hole 80 penetrating the first substrate surface 11 and the second substrate surface 12 in the substrate 10 and filling the vertical through-hole 80 with a conductor 90, the conductor 90 forms a first welding point 91 for welding with the first die 20 on the first substrate surface 11 and a second welding point 92 for welding with the second die 60 on the second substrate surface 12, which can more conveniently realize the connection between the first die 20 and the second die 60 and reduce the packaging cost.
[0068] Embodiment Two
[0069] Embodiment Two of the present application provides a chip packaging method. As Figure 12 shown, the chip packaging method provided in Embodiment Two of the present application also includes the aforementioned step S101 and step S102. The difference is that in this Embodiment Two, the chip packaging method further includes:
[0070] Step S103: Set insulating glue outside the bump array.
[0071] Among them, please refer to Figure 3, the second die 60 includes a bump array soldered to the second substrate surface 12. The bump array is an array structure composed of all the bumps 61 (Bump) on the second die 60. The bump 61 (Bump) is a microscopic structure formed on the die surface during die manufacturing and packaging processes, usually made of metal materials, and plays a key role in aspects such as electrical connection and packaging of the die. Among them, the bumps are generally columnar or spherical, with a height usually ranging from dozens of micrometers to hundreds of micrometers, and a diameter of about dozens of micrometers. The specific dimensions will vary according to different processes and application requirements. The bumps are distributed in a regular or specific pattern on the active surface of the die to form a bump array, and each bump in the bump array is connected to a specific circuit node inside the die.
[0072] In this step, please refer to Figure 13 , and a flowable fluid insulating glue 70 is provided at a position with a preset distance from the second die 60 outside the bump array. Among them, the distance between the setting position of the insulating glue 70 and the second die 60 can be set according to actual physical quantities such as different sizes and different bump spacings. Since the distance between the bumps in the bump array provided on the die is extremely small, after the insulating glue is provided outside the bump array, under the influence of capillary action, the insulating glue 70 provided outside the bump array will penetrate into the bump array and fill the gaps in the bump array, completing the encapsulation and protection of the bump array on the second die.
[0073] Compared with the related technology, in the chip packaging method provided in the second embodiment, the insulating glue 70 is provided outside the bump array. Based on the influence of capillary action, the insulating glue 70 penetrates into the bump array and fills the gaps between the respective bumps 61 in the bump array, completing the encapsulation and protection of the bump array on the second die 60. Since the process of providing the insulating glue 70 outside the bump array does not directly contact the bump array on the second die 60, it will not cause direct damage to the bump array on the second die 60, reducing the influence on the second die 60 during the packaging process, and can further improve the product yield.
[0074] Furthermore, please refer to Figure 14 , after step S103, it is also possible to perform ball planting on the second substrate surface 12 and around the second die 60 to form a number of conductor balls 500, which is convenient for subsequent electrical connection with other structures.
[0075] Embodiment Three
[0076] Embodiment Three of the present application provides a chip packaging device, as Figure 15As shown in the figure, it includes: a first clamping plate 40, a second clamping plate 50, and a welding component 200. Among them, the first clamping plate 40 and the second clamping plate 50 are used to clamp the target chip 100 to improve the flatness of the target chip 100. The second clamping plate 50 includes a main body portion 51 and a hollow portion 52 provided on the main body portion 51. The target chip 100 includes a substrate 10, a first die 20 welded on the substrate 10, and a packaging layer 30 covering the first die 20. The substrate 10 includes a first substrate surface 11 and a second substrate surface 12 arranged opposite to each other. The first die 20 and the packaging layer 30 are provided on the first substrate surface 11. When the first clamping plate 40 and the second clamping plate 50 are used to clamp the target chip 100, the second clamping plate 50 abuts against the second substrate surface 12, and the first clamping plate 40 abuts against the surface 13 on the side of the target chip 100 away from the second substrate surface 12. The welding component 200 is used to hold the second die 60 and weld the second die 60 at a position corresponding to the hollow portion 52 on the second substrate surface 12 based on the flip-chip process.
[0077] Among them, as Figure 15 shown, the welding component 200 can be, for example, a suction nozzle. After the welding component 200 with a suction nozzle structure adsorbs the second die 60 by the pressure generated by suction, the bump array of the second die 60 is oriented towards the second substrate surface 12. After the second substrate surface 12 comes into contact with the bump array of the second die 60, the welding of the second substrate surface 12 and the bump array of the second die 60 is completed. It can be understood that the foregoing welding component 200 being a suction nozzle structure is only an example in some embodiments of the present application. In some other embodiments of the present application, the welding component 200 can also be, for example, a robotic arm, a mechanical clamp, etc.
[0078] Compared with the related art, in the chip packaging device provided by the embodiments of the present application, for the target chip 100 already welded and packaged with the first die 20, the welding member 200 is arranged to weld the second die 60 on the second substrate surface 12 opposite to the first substrate surface 11 where the first die 20 is welded on the substrate 10, so as to realize welding the first die 20 and the second die 60 on the two sides of the substrate 10 respectively, reducing the packaging area of the first die 20 and the second die 60. The reduction of the packaging area can further reduce the volume of the entire packaging structure, realizing the miniaturization of the packaging structure. Since the welding member 200 can weld the second die 60 on the second substrate surface 12 through the flip-chip process, the flip-chip process can be applied to the welding of smaller-sized dies, so that it can be applied to the packaging of smaller-sized chips. At the same time, the first clamping plate 40 and the second clamping plate 50 are arranged, and the target chip 100 is clamped by the first clamping plate 40 and the second clamping plate 50 when welding the second die 60, which can keep the target chip 100 flat, reduce the influence on the flatness of the surface of the substrate 10 during the process of welding the first die 20 on the substrate 10, make the second substrate surface 12 more flat when the welding member 200 welds the second die 60, and the more flat second substrate surface 12 can further optimize the welding effect of the second die 60 and improve the product yield.
[0079] Further, in some embodiments of the present application, as Figure 16 shown, the chip packaging device may further include: a glue application structure 300, and the glue application structure 300 is used to set an insulating glue outside the bump array. Among them, the glue application structure 300 may be, for example, a nozzle structure as Figure 16 shown, or in some other embodiments of the present application, the glue application structure 300 may also be a brush structure, etc., and can be specifically set according to actual needs.
[0080] Since the distance between the bumps in the bump array provided on the die is extremely small, after the glue application structure 300 sets the insulating glue outside the bump array, under the influence of capillary action, the insulating glue set outside the bump array will penetrate into the bump array, filling the gaps in the bump array, completing the packaging and protection of the bump array on the second die 60. Since the process of setting the insulating glue outside the bump array does not directly contact the bump array on the second die 60, it will not cause direct damage to the bump array on the second die 60, reducing the influence on the second die 60 during the packaging process, and can further improve the product yield.
[0081] Further, in some embodiments of the present application, the chip packaging device may further include: a packaging component, the packaging component includes a packaging member and a grinding member, the packaging member is used to prepare and form a package body 31 covering the first die 20 on the first substrate surface 11, and the grinding member is used to grind one side surface of the package body 31 away from the substrate 10 to form a packaging layer 30. Among them, the packaging member may be, for example, a box-shaped structure. When forming the package body 31, the substrate 10 can be placed inside the box-shaped packaging member, and then a packaging material is injected into the box-shaped packaging member to form the package body 31. The grinding member may be, for example, a grinding disc structure, and the grinding member of the grinding disc structure can grind the package body 31 by rotating on one side surface of the package body 31 away from the substrate 10.
[0082] Setting the grinding member to grind one side surface of the package body 31 away from the substrate 10 can, on the one hand, make the one side surface of the package body 31 away from the substrate 10 smoother, improve the stability of the first clamping plate 40 and the second clamping plate 50 when clamping the target chip 100 in the subsequent process of welding the second die 60, and enhance the welding effect of the second die 60; on the other hand, it can also grind the package body 31 until one side surface of the first die 20 away from the substrate 10 is exposed outside the package body 31, which can reduce the thickness of the package body 31, expose the first die 20, and improve the heat dissipation effect of the first die 20.
[0083] Further, in some embodiments of the present application, the chip packaging device may further include: a drilling component, the drilling component includes a punching member and a filling member, the punching member is used to punch holes in the substrate 10 along a direction perpendicular to the first substrate surface 11 to form a vertical through hole 80 penetrating the first substrate surface 11 and the second substrate surface 12, and the filling member is used to fill a conductor 90 in the vertical through hole 80 to form a first welding point 91 for welding with the first die 20 on the first substrate surface 11 and a second welding point 92 for welding with the second die 60 on the second substrate surface 12. Setting the punching member to directly punch holes in the substrate 10 to form a vertical through hole 80 penetrating the first substrate surface 11 and the second substrate surface 12, and setting the filling member to fill the conductor 90 in the through hole 80 to form a first welding point 91 for welding with the first die 20 on the first substrate surface 11 and a second welding point 92 for welding with the second die 60 on the second substrate surface 12 can more conveniently realize the connection between the first die 20 and the second die 60 and reduce the packaging cost.
[0084] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A chip packaging method, characterized in that: include: Clamping a target chip between a first clamping plate and a second clamping plate to improve the flatness of the target chip, the target chip comprising a substrate, a first crystal grain welded on the substrate, and a packaging layer covering the first crystal grain, the substrate comprising a first substrate surface and a second substrate surface arranged oppositely, the first crystal grain and the packaging layer being arranged on the first substrate surface, the second clamping plate comprising a main body and a hollowed-out portion arranged on the main body, the second clamping plate and the second substrate surface abutting against each other to clamp the target chip; A second die is welded at a position corresponding to the second substrate surface and the hollow portion based on a flip-chip process.
2. The chip packaging method according to claim 1, characterized in that: The second die includes a bump array welded to the second substrate surface. After the second die is welded at a position corresponding to the second substrate surface and the hollow portion based on the flip-chip process, the chip packaging method further includes: Insulating glue is disposed on the outer side of the bump array.
3. The chip packaging method according to claim 1, characterized in that: The chip packaging method further comprises: The substrate is clamped between a first clamping plate and a second clamping plate to improve the flatness of the substrate, wherein the second clamping plate abuts against the first substrate surface, and the first clamping plate abuts against the second substrate surface to clamp the substrate; Soldering the first die at a position corresponding to the first substrate surface and the hollow portion based on a flip-chip process; The packaging layer is formed on the first substrate surface to form the target chip.
4. The chip packaging method according to claim 3, characterized in that: The step of forming the encapsulation layer on the first substrate comprises: Forming a package covering the first die on the first substrate; A planarization process is performed on a surface of the package body which is away from the substrate to form the package layer.
5. The chip packaging method according to claim 3, characterized in that: The step of forming the encapsulation layer on the first substrate comprises: Forming a package covering the first die on the first substrate; The packaging body is ground at one side of the surface away from the substrate until the first crystal grain is exposed from the packaging body at one side of the surface away from the substrate to form the packaging layer.
6. The chip packaging method according to claim 3, characterized in that: Before welding the first die at a position corresponding to the first substrate surface and the hollow portion based on the flip-chip process, the chip packaging method further includes: Punching a hole on the substrate in a direction perpendicular to the first substrate surface to form a vertical through hole penetrating the first substrate surface and the second substrate surface; A conductor is filled in the vertical through hole, and the conductor forms a first welding point on the first substrate surface for welding with the first die, and forms a second welding point on the second substrate surface for welding with the second die.
7. A chip packaging device, characterized in that: include: A first clamping plate and a second clamping plate, wherein the first clamping plate and the second clamping plate are used to clamp a target chip to improve the flatness of the target chip, the second clamping plate comprises a main body and a hollow part arranged on the main body, the target chip comprises a substrate, a first crystal grain welded on the substrate, and a packaging layer covering the first crystal grain, the substrate comprises a first substrate surface and a second substrate surface arranged oppositely, the first crystal grain and the packaging layer are arranged on the first substrate surface, and when the first clamping plate and the second clamping plate are used to clamp the target chip, the second clamping plate and the second substrate surface abut against each other; A welding piece is used to hold the second crystal grain and weld the second crystal grain to a position corresponding to the second substrate surface and the hollow portion based on a flip-chip process.
8. The chip packaging device according to claim 7, characterized in that: The second die includes a bump array welded to the second substrate surface, and the chip packaging device further includes: a glue coating structure, and the glue coating structure is used to set an insulating glue on the outer side of the bump array.
9. The chip packaging device according to claim 7, characterized in that: The chip packaging device also includes: a packaging component, which includes a packaging piece and a grinding piece. The packaging piece is used to prepare a packaging body covering the first grain on the first substrate surface, and the grinding piece is used to grind the surface of the packaging body away from the substrate to form the packaging layer.
10. The chip packaging device according to claim 7, characterized in that: The chip packaging device also includes a drilling component, which includes a punching piece and a filling piece. The punching piece is used to punch a hole on the substrate in a direction perpendicular to the first substrate surface to form a vertical through hole that passes through the first substrate surface and the second substrate surface. The filling piece is used to fill a conductor in the vertical through hole to form a first welding point on the first substrate surface for welding with the first grain, and a second welding point on the second substrate surface for welding with the second grain.