Silicon process defect detection method
By removing the film layer on the surface of the silicon substrate in the semiconductor process and using scanning electron microscope to detect silicon process defects, the problem of silicon dislocation detection in the prior art needs to wait for the chip to be completed, and a faster and economical research and development process is achieved.
Patent Information
- Application Number
- CN202510246198.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-03
- Publication Date
- 2025-05-27
AI Technical Summary
The detection method of silicon dislocation in existing semiconductor processes is single, and it needs to be tested after the chip is manufactured, resulting in a long R&D time and increased cost.
By removing other film layers on the surface of the silicon substrate after ion implantation, scanning electron microscope is used to detect whether there are silicon process defects in the remaining silicon substrate, and avoiding detection after the chip is completed.
It saves time and cost in semiconductor process research and development, avoids the need to use Nannoprobe Test and TEM resources, and improves detection efficiency.
Smart Images
Figure CN120048754A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor processes, and in particular to a method for detecting silicon process defects. Background Art
[0002] Silicon dislocation is a silicon process defect that causes leakage in semiconductor devices. Currently, the detection methods for silicon dislocations in semiconductor processes are relatively single. Usually, after the chip is manufactured, the position where the device has leakage needs to be detected by Nannoprobe Test first, and then it is analyzed whether there are silicon dislocations by Transmission Electron Microscope (abbreviated as TEM). For the R & D stage, time is very precious, and testing can only be carried out after the chip is manufactured, which takes too long for the R & D of semiconductor processes, and the use of Nannoprobe Test and TEM resources also increases the R & D cost. Summary of the Invention
[0003] The technical problem to be solved by the present invention is to provide a method for detecting silicon process defects, which can save the R & D time and cost of the process.
[0004] To solve the above problem, an embodiment of the present invention provides a method for detecting silicon process defects, the method includes: providing a sample to be detected, the sample to be detected includes a silicon substrate, an active region is defined in the silicon substrate through an isolation structure, a well region is formed in the active region through ion implantation, an active source / drain region is formed in the well region through ion implantation, the sample to be detected further includes a gate structure formed on the silicon substrate and corresponding to the well region, the gate structure includes a polysilicon gate and sidewalls located on the sidewalls of the polysilicon gate; removing the sidewalls; oxidizing the polysilicon gate and the silicon substrate to form a silicon oxide film layer; removing the silicon oxide film layer; and detecting whether there are silicon process defects in the remaining silicon substrate.
[0005] In some embodiments, the silicon process defect includes a silicon dislocation defect caused by ion implantation in the silicon substrate. If there is such a silicon dislocation defect in the silicon substrate, the step of oxidizing the polysilicon gate and the silicon substrate to form a silicon oxide film layer can magnify the silicon dislocation defect.
[0006] In some embodiments, the step of removing the sidewalls specifically includes: removing the sidewalls by a wet etching process.
[0007] In some embodiments, the sidewall includes a silicon nitride layer attached to the sidewalls of the polysilicon gate and a silicon oxide layer covering the side of the silicon nitride layer away from the polysilicon gate. In the step of removing the sidewall by a wet etching process, a wet etching solution capable of removing both the silicon nitride layer and the silicon oxide layer is used.
[0008] In some embodiments, in the step of oxidizing the polysilicon gate and the silicon substrate to form a silicon oxide film layer, the oxidation includes a thermal oxidation process.
[0009] In some embodiments, the step of removing the silicon oxide film layer specifically includes: removing the silicon oxide film layer by a wet etching process.
[0010] In some embodiments, the step of detecting whether there are silicon process defects remaining in the silicon substrate specifically includes: scanning the surface of the silicon substrate with a scanning electron microscope to detect whether there are silicon process defects in the silicon substrate.
[0011] In some embodiments, in the step of providing a sample to be detected, source and drain regions are formed by ion implantation in the well region under the self-alignment of the sidewall.
[0012] In some embodiments, in the step of providing a sample to be detected, a metal silicide blocking layer covering the silicon substrate and the gate structure is further formed on the silicon substrate; before the step of removing the sidewall, it further includes: removing the metal silicide blocking layer.
[0013] In some embodiments, the material of the metal silicide blocking layer includes tetraethylsilane. The step of removing the metal silicide blocking layer specifically includes: removing the metal silicide blocking layer by an etching process; and removing the remaining metal silicide blocking layer by a wet etching process.
[0014] The above technical solution removes other film layers on the surface of the silicon substrate by a process after ion implantation, and then performs silicon process defect detection, without waiting for the completion of chip manufacturing for detection, saving the R & D time and cost of the process. And the silicon process defect detection in this embodiment can be detected by scanning the surface of the silicon substrate remaining after removing the silicon oxide film layer with a scanning electron microscope, without using Nannoprobe Test and TEM resources, further saving time and cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.
[0016] Figure 1 Schematic diagram of the steps of the silicon process defect detection method provided by an embodiment of the present invention;
[0017] Figure 2 Schematic diagram of the device structure of the sample to be detected provided by the first embodiment of the present invention;
[0018] Figure 3 Schematic diagram of the device structure after removing the sidewall provided by an embodiment of the present invention;
[0019] Figure 4 Schematic diagram of the device structure after forming the silicon oxide film layer provided by an embodiment of the present invention;
[0020] Figure 5 Schematic diagram of the device structure after removing the silicon oxide film layer provided by an embodiment of the present invention;
[0021] Figure 6 Schematic diagram of the device structure of the sample to be detected provided by the second embodiment of the present invention.
[0022] Explanation of reference numerals:
[0023] 20 Sample to be detected 21 Silicon substrate
[0024] 22 Isolation structure 23 Well region
[0025] 24 Source / drain region 25 Gate structure
[0026] 251 Polysilicon gate 252 Sidewall
[0027] 2521 Silicon nitride layer 2522 Silicon oxide layer
[0028] 253 Gate oxide layer
[0029] 40 Silicon oxide film layer 60 Metal silicide barrier layer Detailed implementation manners
[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.
[0031] An embodiment of the present invention provides a method for detecting silicon process defects. After ion implantation, other film layers on the surface of the silicon substrate are removed through a process, and then silicon process defect detection is performed. It is not necessary to wait until the chip manufacturing is completed for detection, saving the R & D time and cost of the process. Moreover, the detection in this embodiment does not require the use of Nannoprobe Test and TEM resources, further saving time and cost.
[0032] Please refer to Figures 1 to 5 together, where Figure 1 is a schematic diagram of the steps of the method for detecting silicon process defects provided by an embodiment of the present invention; Figure 2 is a schematic diagram of the device structure of the sample to be detected provided by the first embodiment of the present invention; Figure 3 is a schematic diagram of the device structure after removing the sidewall provided by an embodiment of the present invention; Figure 4 is a schematic diagram of the device structure after forming a silicon oxide film layer provided by an embodiment of the present invention; Figure 5 is a schematic diagram of the device structure after removing the silicon oxide film layer provided by an embodiment of the present invention.
[0033] As Figure 1 shown, the method for detecting silicon process defects in this embodiment includes the following steps: S1. Provide a sample to be detected, where the sample to be detected includes a silicon substrate, an active region is defined in the silicon substrate through an isolation structure, a well region is formed in the active region through ion implantation, an active source / drain region is formed in the well region through ion implantation, the sample to be detected further includes a gate structure formed on the silicon substrate and corresponding to the well region, and the gate structure includes a polysilicon gate and sidewalls located on the sidewalls of the polysilicon gate; S2. Remove the sidewalls; S3. Oxidize the polysilicon gate and the silicon substrate to form a silicon oxide film layer; S4. Remove the silicon oxide film layer; and S5. Detect whether there are silicon process defects in the remaining silicon substrate.
[0034] Please refer to step S1 and Figure 2 together. Provide a sample to be detected 20, where the sample to be detected 20 includes a silicon substrate 21, an active region is defined in the silicon substrate 21 through an isolation structure 22, a well region 23 is formed in the active region through ion implantation, an active source / drain region 24 is formed in the well region 23 through ion implantation, the sample to be detected further includes a gate structure 25 formed on the silicon substrate 21 and corresponding to the well region 23, and the gate structure 25 includes a polysilicon gate 251 and sidewalls 252 located on the sidewalls of the polysilicon gate 251.
[0035] In some embodiments, the silicon substrate 21 can be a single-layer structure or a multi-layer structure. For example, the silicon substrate 21 can be a single-layer silicon (Si) substrate or a multi-layer structure substrate including silicon, silicon germanium (SiGe), silicon carbide (SiC), silicon-on-insulator (SOI), or silicon germanium-on-insulator. In this embodiment, the silicon substrate 21 is described as a single-layer silicon substrate for illustration purposes.
[0036] In some embodiments, the isolation structure 22 can adopt a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) structure. Compared with the local oxidation of silicon isolation structure, the shallow trench isolation structure occupies a smaller area of the silicon substrate and can improve the integration of devices on a unit silicon substrate.
[0037] In this embodiment, the gate structure 25 further includes a gate oxide layer 253 located between the polysilicon gate 251 and the silicon substrate 21; the sidewall 252 also covers the sidewalls of the gate oxide layer 253.
[0038] In some embodiments, in the step of providing the sample to be detected 20, the source-drain regions 24 are formed by ion implantation in the well region 23 under the self-alignment of the sidewall 252. In some embodiments, the step of providing the sample to be detected 20 further includes: forming a lightly doped drain (LDD) by ion implantation in the well region 23 under the self-alignment of the polysilicon gate 251.
[0039] Taking the P-well as an example of the well region, the specific formation method of the sample to be detected 20 is as follows: an active region is defined in the silicon substrate through the isolation structure, and a P-well is formed by ion implantation in the active region; a gate structure including a polysilicon gate and sidewalls located on the sidewalls of the polysilicon gate is formed in the region corresponding to the P-well on the silicon substrate; a lightly doped drain (LDD) is formed by ion implantation in the P-well under the self-alignment of the polysilicon gate, and N+ (NPS, full name NPLUS, N-type heavily doped) is formed as the source-drain regions (source region and drain region) by ion implantation with extremely high concentration in the P-well under the self-alignment of the sidewall. Specifically, the ions implanted in the P-well can be Al ions or B ions, the ions implanted in the lightly doped drain + can be P ions or N ions, and the ions implanted in the N+ can be P ions or N ions with extremely high concentration.
[0040] Please refer to step S2 and Figure 3 , remove the sidewall 252.
[0041] In this embodiment, the step of removing the sidewall 252 specifically includes: removing the sidewall 252 by using a wet etching (WET) process.
[0042] In this embodiment, the sidewall 252 includes a silicon nitride layer 2521 attached to the sidewalls of the polysilicon gate 251 and a silicon oxide layer 2522 covering the side of the silicon nitride layer 2521 away from the polysilicon gate 251; that is, the sidewall 252 is a double-layer sidewall, as Figure 2 shown. In the step of removing the sidewall 252 by a wet etching process, a wet etching solution capable of removing both the silicon nitride layer and the silicon oxide layer is used. For example, a hot phosphoric acid etching solution is used for wet etching to remove the silicon nitride layer and the silicon oxide layer. Hot phosphoric acid has good uniformity and a high selectivity ratio for etching silicon nitride and silicon oxide. In other embodiments, the sidewall 252 may also be a single-layer sidewall composed of a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer, and a corresponding wet etching solution is used for wet etching to remove it.
[0043] Please refer to step S3 and Figure 4 , oxidize the polysilicon gate 251 and the silicon substrate 21 to form a silicon oxide film layer 40. The main silicon process defects detected in this embodiment include whether there are silicon dislocation defects caused by ion implantation in the silicon substrate. If there are such silicon dislocation defects in the silicon substrate, the step of oxidizing the polysilicon gate 251 and the silicon substrate 21 to form the silicon oxide film layer 40 can magnify the silicon dislocation defects. That is, during the oxidation process, the silicon dislocation defects at the defect sites will be magnified.
[0044] In this embodiment, in the step of oxidizing the polysilicon gate 251 and the silicon substrate 21 to form the silicon oxide film layer 40, the oxidation includes a thermal oxidation process. By performing the thermal oxidation process, thermal oxygen reacts with the polysilicon gate to generate silicon oxide and thermal oxygen reacts with the silicon substrate to generate silicon oxide, which together form the silicon oxide film layer 40.
[0045] Please refer to step S4 and Figure 5 , remove the silicon oxide film layer 40. There are differences between the surface of the silicon substrate at the position with silicon dislocation defects and the surface of a conventional silicon substrate without silicon dislocation defects. Therefore, after removing the silicon oxide film layer 40, it is convenient to detect silicon process defects.
[0046] In this embodiment, the step of removing the silicon oxide film layer 40 specifically includes: using a wet etching process to remove the silicon oxide film layer 40. A smooth surface is formed on the remaining surface of the silicon substrate 21, which is convenient for detecting silicon process defects.
[0047] Regarding step S5, detect whether there are silicon process defects in the remaining silicon substrate 21. Specifically, a scanning electron microscope (SEM) can be used to scan the surface of the silicon substrate to detect whether there are silicon process defects in the silicon substrate.
[0048] In the above embodiments of the present invention, after ion implantation, other film layers on the surface of the silicon substrate are removed by a process, and then silicon process defect detection is performed. It is not necessary to wait until the chip manufacturing is completed for detection, saving the R & D time and cost of the process. Moreover, the silicon process defect detection in this embodiment can be performed by scanning the remaining silicon substrate surface after removing the silicon oxide film layer with a scanning electron microscope, without using Nannoprobe Test and TEM resources, further saving time and cost.
[0049] Please refer to Figure 6 , which is a schematic diagram of the device structure of the sample to be detected provided by the second embodiment of the present invention. Different from the Figure 2 embodiment shown, in this embodiment, in the step of providing the sample to be detected, a metal silicide barrier layer 60 covering the silicon substrate 21 and the gate structure 25 is further formed on the silicon substrate 21. Correspondingly, Figure 1 before the step of removing the sidewall described in the silicon process defect detection method shown, it further includes: removing the metal silicide barrier layer 60. By forming the metal silicide barrier layer 60 on the silicon substrate 21, element diffusion after ion implantation can be prevented, ensuring the accuracy of subsequent silicon process defect detection.
[0050] In Figure 6 the embodiment shown, the material of the metal silicide barrier layer 60 includes tetraethyl orthosilicate (TEOS). The step of removing the metal silicide barrier layer 60 specifically includes: removing the metal silicide barrier layer 60 by an etching (ET) process; and removing the remaining metal silicide barrier layer by a wet etching (WET) process. The wet etching process can further remove the remaining metal silicide barrier layer and reduce the pollutant index. In the conventional process flow, after the deposition process of the metal silicide barrier layer, a metal silicide barrier layer photolithography (PH) and an etching (ET) process are performed to facilitate the subsequent formation of the source-drain contact structure; while in this embodiment, after the deposition process of the metal silicide barrier layer, the operation of removing the metal silicide barrier layer 60 is directly performed without performing the metal silicide barrier layer photolithography (PH) operation. To avoid the problem that the etching residue of the metal silicide barrier layer causes the pollutant index to exceed the standard and affects the accuracy of silicon process defect detection, this embodiment further adds a wet etching (WET) process after the etching (ET) process.
[0051] It should be noted that the terms "comprising" and "having" and their variants in the documents of the present invention are intended to cover non-exclusive inclusion. The terms "first", "second", etc. are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. The term "one or more" depends at least in part on the context and can be used to describe a feature, structure, or property in the singular sense, or can be used to describe a combination of features, structures, or features in the plural sense. The term "based on" can be understood as not necessarily intended to express a set of exclusive factors, but rather, alternatively, and also at least in part depending on the context, allows for the existence of other factors that are not necessarily explicitly described. Additionally, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. Furthermore, in the above description, the description of well-known components and technologies is omitted to avoid unnecessarily confusing the concepts of the present invention. In each of the above embodiments, the key point of each embodiment is to illustrate the differences from other embodiments. For the same / similar parts among the embodiments, reference can be made to each other.
[0052] The above are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.
Claims
1. A silicon process defect detection method, characterized in that: The method comprises: A sample to be tested is provided, wherein the sample to be tested includes a silicon substrate, an active region is defined in the silicon substrate by an isolation structure, a well region is formed in the active region by ion implantation, a source-drain region is formed in the well region by ion implantation, and the sample to be tested also includes a gate structure formed on the silicon substrate and corresponding to the well region, wherein the gate structure includes a polysilicon gate and a sidewall located on a sidewall of the polysilicon gate; removing the side wall; Oxidizing the polysilicon gate and the silicon substrate to form a silicon oxide film layer; removing the silicon oxide film layer; and The remaining silicon substrate is inspected for silicon process defects.
2. The method according to claim 1, characterized in that The silicon process defects include silicon dislocation defects caused by ion implantation in the silicon substrate. If the silicon substrate has the silicon dislocation defects, the steps of oxidizing the polysilicon gate and forming a silicon oxide film layer on the silicon substrate can amplify the silicon dislocation defects.
3. The method according to claim 1, characterized in that The step of removing the side wall specifically includes: The sidewalls are removed by a wet etching process.
4. The method according to claim 3, characterized in that: The side wall includes a silicon nitride layer attached to the side wall of the polysilicon gate and a silicon oxide layer covering the side of the silicon nitride layer away from the polysilicon gate. In the step of removing the side wall by using a wet etching process, a wet etching solution that can simultaneously remove the silicon nitride layer and the silicon oxide layer is used.
5. The method according to claim 1, characterized in that In the step of oxidizing the polysilicon gate and the silicon substrate to form a silicon oxide film layer, the oxidation includes a thermal oxidation process.
6. The method according to claim 1, characterized in that The step of removing the silicon oxide film layer specifically includes: The silicon oxide film layer is removed by a wet etching process.
7. The method according to claim 1, characterized in that The step of detecting whether the remaining silicon substrate has silicon process defects specifically includes: A scanning electron microscope is used to scan the surface of the silicon substrate to detect whether there are silicon process defects on the silicon substrate.
8. The method according to claim 1, characterized in that: In the step of providing the sample to be detected, the source and drain regions are formed in the well region by ion implantation under the self-alignment of the sidewalls.
9. The method according to claim 1, characterized in that: In the step of providing the sample to be tested, a metal silicide barrier layer covering the silicon substrate and the gate structure is formed on the silicon substrate; and before the step of removing the sidewall, the step further includes: The metal silicide barrier layer is removed.
10. The method according to claim 9, characterized in that The material of the metal silicide barrier layer includes tetraethylsilane, and the step of removing the metal silicide barrier layer specifically includes: removing the metal silicide barrier layer by an etching process; and The remaining metal silicide barrier layer is removed by a wet etching process.