Shallow trench isolation structure and preparation method thereof

Abstract

The invention provides a shallow trench isolation structure and a preparation method thereof. The preparation method comprises the steps that a semiconductor substrate is provided, a patterned shielding layer is formed on the upper surface of the semiconductor substrate, and the bottom of the shielding layer at least comprises a sacrificial layer with a preset thickness; based on the patterned shielding layer, an opening part is formed in the upper surface layer of the semiconductor substrate, a groove is formed in the semiconductor substrate, and a preset distance is formed between the bottom surface of the groove and the bottom surface of the semiconductor substrate; forming an isolation layer for filling the opening part and the groove, and except the shielding layer; after a protection layer is formed on the side wall of the isolation layer, the sacrificial layer is removed; and removing the protective layer. The protection layer is arranged on the side wall of the isolation layer before the sacrificial layer is removed, so that when the sacrificial layer is removed, corrosion to the side wall of the isolation layer can be reduced, the defect of sinking on the isolation layer is reduced, and the process yield of subsequent steps is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a shallow trench isolation structure and a preparation method thereof. Background Art

[0002] With the continuous development of large-scale integrated circuits and the reduction of semiconductor feature sizes, the isolation area between devices must also be reduced accordingly. STI (Shallow Trench Isolation) has outstanding isolation performance and is used in deep submicron and nano-sized integrated circuit manufacturing, becoming the mainstream isolation technology.

[0003] STI is to etch grooves on the semiconductor substrate and fill the grooves with oxides, thereby effectively isolating the device and preventing leakage. However, with the continuous miniaturization of the key dimensions of integrated circuits and the continuous increase in integration density, STI technology has significantly reduced the area of ​​the isolation region, and there is local stress concentration at the interface between the filled oxide layer and the active area of ​​the semiconductor substrate, which can easily over-corrode the filled isolation layer to form a depression (as shown in the figure), generally called a "Divot". These defects will affect the isolation performance of the STI structure.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the invention

[0005] In view of the problems in the prior art, the purpose of the present invention is to provide a shallow trench isolation structure and a preparation method thereof, so as to reduce the recessed defects on the isolation layer when removing the sacrificial layer, prevent the residues during the subsequent etching of the gate polysilicon, avoid the problem of parasitic leakage current, improve the production yield, reduce the difficulty of the semiconductor device processing process, reduce the cost, and save energy and reduce consumption.

[0006] An embodiment of the present invention provides a method for preparing a shallow trench isolation structure, comprising the steps of:

[0007] Providing a semiconductor substrate, forming a patterned shielding layer on the upper surface of the semiconductor substrate, wherein the bottom of the shielding layer at least includes a sacrificial layer with a preset thickness;

[0008] Based on the patterned shielding layer, an opening is formed on the upper surface of the semiconductor substrate and a groove is formed in the semiconductor substrate, the bottom surface of the groove is spaced apart from the bottom surface of the semiconductor substrate by a preset distance, and the semiconductor substrate region between two adjacent grooves is an active region;

[0009] forming an isolation layer filling the opening and the trench and removing the shielding layer;

[0010] After forming a protective layer on the sidewall of the isolation layer, removing the sacrificial layer;

[0011] The protective layer is removed.

[0012] In some embodiments, the shielding layer includes a first film layer and a second film layer, and the first film layer and the second film layer are sequentially stacked on the sacrificial layer.

[0013] In some embodiments, the material of the first film layer includes silicon nitride; the material of the second film layer includes silicon oxynitride.

[0014] In some embodiments, the shielding layer is a photoresist layer.

[0015] In some embodiments, the bottom of the shielding layer further includes a stop layer, and the stop layer is disposed between the sacrificial layer and the shielding layer.

[0016] In some embodiments, the method of removing the sacrificial layer comprises wet etching.

[0017] In some embodiments, the method of forming a trench in a substrate of the semiconductor substrate comprises plasma etching.

[0018] In some embodiments, the isolation layer includes a buffer layer covering the inner wall and bottom surface of the trench and a filling layer filling the remaining gap of the trench, and the buffer layer wraps the sidewall and bottom of the filling layer.

[0019] In some embodiments, the buffer layer includes a silicon nitride layer, and the filling layer is a silicon dioxide layer.

[0020] An embodiment of the present invention further provides a shallow trench isolation structure, which is prepared by the above-mentioned preparation method, and includes:

[0021] Semiconductor substrate;

[0022] A groove is provided inside the semiconductor substrate, and a bottom surface of the groove is spaced apart from a bottom surface of the semiconductor substrate by a preset distance;

[0023] An active region is a semiconductor region disposed between two adjacent trenches;

[0024] An isolation layer fills the trench.

[0025] The shallow trench isolation structure and the preparation method thereof provided by the present invention have the following advantages:

[0026] By forming a protective layer on the side wall of the isolation layer before removing the sacrificial layer, the amount of corrosion on the isolation layer when removing the sacrificial layer can be reduced, thereby reducing the generation of concave defects on the isolation layer. Reducing the concave defects generated on the isolation layer when removing the sacrificial layer can reduce the residual polysilicon at the isolation structure during the subsequent etching of the gate polysilicon, avoid the generation of parasitic leakage current problems, improve the production yield of the shallow trench isolation structure, and reduce the gate sidewall protective layer Residue in the isolation structure, improve the isolation performance of the shallow trench isolation structure. In addition, the preparation method of the present application is simple, and can also reduce the difficulty of the semiconductor device processing process, reduce costs, and save energy and reduce consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objectives and advantages of the present invention will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following accompanying drawings.

[0028] Figures 1 to 9 It is a schematic diagram of an intermediate structure for preparing a shallow trench isolation structure in the prior art;

[0029] Fig.10 and Fig.11 is a schematic diagram of preparing a polysilicon layer;

[0030] Fig.12 and Fig.13 is a schematic diagram of preparing a gate sidewall protection layer;

[0031] Fig.14 is a flow chart of a method for preparing a shallow trench isolation structure provided by an embodiment of the present invention;

[0032] Figures 15 to 21 It is a schematic diagram of a partial intermediate structure of a shallow trench isolation structure prepared according to an embodiment of the present invention.

[0033] Reference numerals:

[0034] 10' Semiconductor substrate in the prior art 10 Semiconductor substrate

[0035] 20' Sacrificial layer in the prior art 20 Sacrificial layer

[0036] 30' Stop layer in the prior art 30 Stop layer

[0037] 40' Buffer layer in the prior art 40 Buffer layer

[0038] 50' Filling layer in the prior art 50 Filling layer

[0039] 51' recessed portion 80 shielding layer

[0040] 60' Polysilicon layer 90 Protective layer in the prior art

[0041] 70' The gate sidewall protection layer 1 groove in the prior art

[0042] 1' Opening of groove 23 in the prior art

[0043] 23' Opening in the prior art DETAILED DESCRIPTION

[0044] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. In the figures, the same reference numerals represent the same or similar structures, and thus their repeated description will be omitted. "or" and "or" in the specification may both mean "and" or "or".

[0045] In the representations of the present application, the representations with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the represented specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples represented in the present application and the features of the different embodiments or examples, unless they contradict each other.

[0046] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the representation of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0047] It should be further understood that the terms "comprises" and "includes" indicate the presence of features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way.

[0048] Figures 1 to 9The schematic diagram shows an intermediate structure obtained when a shallow trench isolation structure is prepared using an existing shallow trench isolation structure preparation method.

[0049] like Figure 1 As shown, the first step of preparing the shallow trench isolation structure is to sequentially grow a sacrificial layer 20' and a stop layer 30' on the surface of a semiconductor substrate 10';

[0050] like Figure 2 As shown, the second step of preparing the shallow trench isolation structure is: etching the film layer (sacrificial layer 20' and stop layer 30') on the surface of the semiconductor substrate 10' and the semiconductor substrate 10', forming an opening 23' on the surface film layer of the semiconductor substrate 10' and forming a trench 1' on the semiconductor substrate 10';

[0051] like Figure 3 As shown, the third step of preparing the shallow trench isolation structure is: expanding the opening 23' so that the width of the opening 23' is greater than the width of the trench 1';

[0052] like Figure 4 As shown, the fourth step of preparing the shallow trench isolation structure is: growing a buffer layer 40' in the trench 1' to repair the damage to the side wall of the semiconductor substrate 10' caused by etching;

[0053] like Figure 5 As shown, the fifth step of preparing the shallow trench isolation structure is to form a filling layer 50' to fill the opening 23' and the trench 1' and cover the surface of the stop layer 30';

[0054] like Figure 6 As shown, the sixth step of preparing the shallow trench isolation structure is to remove the filling layer 50' beyond the stop layer 30' by chemical mechanical polishing;

[0055] like Figure 7 As shown, the seventh step of preparing the shallow trench isolation structure is to remove part of the filling layer 50' by wet etching;

[0056] like Figure 8 As shown, the eighth step of preparing the shallow trench isolation structure is to remove the stop layer 30' by wet etching;

[0057] like Fig. 9 As shown, the ninth step of preparing the shallow trench isolation structure is to remove the sacrificial layer 20' by wet etching, thereby completing the preparation of the shallow trench isolation structure.

[0058] But if Fig. 9 As shown, in the ninth step of the conventional shallow trench isolation structure preparation, due to the local stress concentration between the sacrificial layer 20' and the active area of ​​the semiconductor substrate 10', it is easy to over-corrode the filling layer 50', and a concave portion 51' will appear on the filling layer 50'. Fig.10and Fig.11 As shown, when preparing a semiconductor device, after the shallow trench isolation structure is formed, a polysilicon layer 60' is prepared in the active area of ​​the semiconductor substrate 10' to form a gate, and when the polysilicon layer 60' in the non-active area is etched, part of the polysilicon layer 60' will remain in the recessed portion 51'. The polysilicon layer 60' remaining in the recessed portion 51' will generate parasitic capacitance, thereby affecting the turn-on voltage of the semiconductor device.

[0059] Furthermore, when preparing the semiconductor device, a sidewall protection layer needs to be formed on the sidewall of the gate. Fig.12 and Fig.13 As shown, a gate sidewall protection layer 70' is formed on the gate sidewall of the active region of the semiconductor substrate 10'. Since part of the gate sidewall protection layer 70' is formed in the recessed portion 51', this will affect the isolation performance of the shallow trench isolation structure. Therefore, it is usually chosen to extend the etching time to remove the gate sidewall protection layer 70' remaining in the recessed portion 51', and extending the etching time will damage the filling layer 50', which will also affect the isolation performance of the shallow trench isolation structure.

[0060] In order to solve the problem that when preparing a shallow trench isolation structure using the above-mentioned existing preparation method, a recessed portion is generated on the filling layer, which affects the isolation performance of the shallow trench structure and the turn-on voltage of the semiconductor device, an embodiment of the present invention provides a preparation method for a shallow trench isolation structure. Fig.14 FIG. 1 is a schematic diagram showing a process for preparing a shallow trench isolation structure according to an embodiment of the present invention. Fig.14 As shown, the method for preparing the shallow trench isolation structure includes the steps of:

[0061] S100: providing a semiconductor substrate, forming a patterned shielding layer on the upper surface of the semiconductor substrate, wherein the bottom of the shielding layer at least includes a sacrificial layer having a preset thickness;

[0062] S200: Based on the patterned shielding layer, an opening is formed on the upper surface layer of the semiconductor substrate and a groove is formed in the semiconductor substrate, wherein the bottom surface of the groove is spaced apart from the bottom surface of the semiconductor substrate by a preset distance, and the semiconductor substrate region between two adjacent grooves is an active region;

[0063] S300: forming an isolation layer filling the trench and removing the shielding layer;

[0064] S400: forming a protective layer on the sidewall of the isolation layer and removing the sacrificial layer;

[0065] S500: removing the protective layer.

[0066] In the present technical solution, by forming a protective layer on the side wall of the isolation layer before removing the sacrificial layer, the amount of corrosion on the isolation layer when removing the sacrificial layer can be reduced, thereby reducing the generation of recess defects on the isolation layer. Reducing the recess defects generated on the isolation layer when removing the sacrificial layer can reduce the residual polysilicon in the isolation structure during the subsequent etching of the gate polysilicon, avoid the generation of parasitic leakage current problems, improve the production yield of the shallow trench isolation structure, and reduce the gate sidewall protective layer Remaining in the isolation structure, improve the isolation performance of the shallow trench isolation structure. In addition, the preparation method of the present application is simple, and can also reduce the difficulty of the semiconductor device processing process, reduce costs, and save energy and reduce consumption.

[0067] The following will further describe the method for preparing the shallow trench isolation structure provided by the present invention in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments shown are not intended to limit the scope of protection of the present invention. Figures 15 to 21 A schematic diagram of an intermediate structure when preparing a shallow trench isolation structure provided by an embodiment of the present invention is shown.

[0068] For details, please refer to Fig.15 , perform step S100, provide a semiconductor substrate 10, form a patterned shielding layer 80 on the upper surface of the semiconductor substrate 10, and the bottom of the shielding layer 80 includes at least a sacrificial layer 20 with a preset thickness. In this embodiment, the bottom of the shielding layer 80 also includes a stop layer 30, and the stop layer 30 is arranged between the sacrificial layer 20 and the shielding layer 80. The number of film layers arranged below the specific shielding layer 80 can be set according to actual needs, and is not specifically limited here.

[0069] Specifically, the material of the semiconductor substrate 10 may be silicon, germanium, silicon germanium, silicon carbide or other suitable semiconductor materials. The semiconductor substrate 10 may also be silicon on insulator or germanium on insulator.

[0070] Under the condition that the performance of the shallow trench isolation structure is met, the shape and size of the semiconductor substrate 10 can be selected according to actual conditions, and no specific limitation is made here.

[0071] Furthermore, in some embodiments, the shielding layer 80 is a hard mask, such as a silicon nitride layer or a silicon oxide layer.

[0072] Further, when the shielding layer 80 is a hard mask, a patterned shielding layer 80 is formed by a photolithography process and a wet etching process. The shielding layer 80 may include a single or multiple hard mask layers. Exemplarily, in one embodiment, the shielding layer 80 includes a first film layer and a second film layer, and the first film layer and the second film layer are sequentially stacked on the stop layer 30. Specifically, the material of the first film layer may be the same as or different from the material of the second film layer. For example, the material of the first film layer and the material of the second film layer are both silicon nitride or silicon oxynitride; or, the material of the first film layer is silicon nitride, and the material of the second film layer is silicon oxynitride.

[0073] Specifically, the method of forming the shielding layer 80 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0074] In other embodiments, the shielding layer 80 may be a soft mask. For example, the shielding layer 80 may be a photoresist. The photoresist is disposed on the upper surface of the stop layer 30 by coating, and then a patterned shielding layer 80 is formed on the photoresist by exposure and development. It should be noted that, since a photoresist is also required when forming a patterned hard mask, when the performance of the shallow trench structure is met, only a photoresist is used as a mask, which can simplify the process of forming the patterned shielding layer 80.

[0075] Specifically, the material of the sacrificial layer 20 may be silicon dioxide, silicon nitride or other suitable materials.

[0076] Specifically, the method of forming the sacrificial layer 20 may include thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0077] Specifically, under the condition that the performance of the shallow trench isolation structure is met, the thickness of the sacrificial layer 20 can be selected according to actual needs, and no specific limitation is made here.

[0078] Specifically, the material of the stop layer 30 may be silicon nitride or other suitable materials.

[0079] Specifically, the stop layer 30 may be formed by chemical vapor deposition or other suitable methods.

[0080] Specifically, under the condition that the performance of the shallow trench isolation structure is met, the thickness of the stop layer 30 can be selected according to actual needs, and no specific limitation is made here.

[0081] For further information, see Fig.16, step S200 is performed, based on the patterned shielding layer 80, an opening 23 is formed on the upper surface of the semiconductor substrate 10 and a groove 1 is formed in the semiconductor substrate 10, the bottom surface of the groove 1 is separated from the bottom surface of the semiconductor substrate 10 by a preset distance, and the area of ​​the semiconductor substrate 10 between two adjacent grooves is the active area. The area of ​​the stop layer 30, the sacrificial layer 20 and the semiconductor substrate 10 not covered by the shielding layer 80 is the etched area, the required opening 23 is formed on the etched stop layer 30 and the sacrificial layer 20, and the required groove 1 is formed on the etchable semiconductor substrate 10.

[0082] Specifically, the method of forming the opening 23 includes dry etching and wet etching, and the method of etching the groove 1 includes plasma etching or other suitable methods.

[0083] The process parameters for forming the opening 23 can be set according to actual needs and are not specifically limited here. At the same time, the shape and depth of the groove 1 can be selected according to actual conditions and are not specifically limited here.

[0084] For further information, see Fig.17 , perform step S300: remove the shielding layer 80 to form an isolation layer filling the opening 23 and the trench 1 and remove the shielding layer 80. In this embodiment, the isolation layer includes a buffer layer 40 covering the inner wall and bottom surface of the trench 1 and a filling layer 50 filling the remaining gap of the trench, and the buffer layer 40 wraps the sidewall and bottom of the filling layer 50.

[0085] Specifically in the formation Fig.17 The structure shown can be referred to Figure 5 and Figure 6 For example, first remove the shielding layer 80; then grow the buffer layer 40 on the sidewall and bottom of the trench 1; then grow the filling layer 50, the height of the filling layer 50 exceeds the height of the stop layer 30; further use the chemical mechanical polishing technology to remove the filling layer 50' that exceeds the stop layer 30'; finally, use dry etching or wet etching to remove the stop layer 30, and obtain the following Fig.17 The structure shown.

[0086] Furthermore, the material of the buffer layer 40 includes silicon dioxide or other suitable materials.

[0087] Specifically, the method of forming the buffer layer 40 includes thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0088] Specifically, the material of the filling layer 50 includes silicon dioxide or other suitable materials.

[0089] Specifically, the method of forming the filling layer 50 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0090] Furthermore, the method of removing the shielding layer 80 includes etching or other suitable methods.

[0091] For further information, see Figures 18 to 20 , performing step S400: forming a protection layer 90 on the sidewall of the filling layer 50 and removing the sacrificial layer 20 .

[0092] Specifically, first Fig.17 A protective layer 90 is formed on the entire intermediate structure, and the protective layer 90 covers the surface of the sacrificial layer 20, the surface and the sidewall of the filling layer 50. Further, the protective layer 90 covering the surface of the sacrificial layer 20 and the surface of the filling layer 52 is removed by photolithography and etching techniques, so that the protective layer 90 covering only the sidewall of the filling layer 50 is obtained.

[0093] Since a protective layer 90 is provided on the side wall of the filling layer 50 when the sacrificial layer 20 is removed, the provision of the protective layer 90 can reduce the amount of corrosion on the filling layer 50. Therefore, the recessed defect formed on the filling layer 50 when the sacrificial layer 20 is removed can be improved, the isolation performance of the shallow trench isolation structure can be enhanced, and the yield of the semiconductor device can be improved.

[0094] Specifically, the protective layer 90 may be silicon nitride or other suitable materials. The method of forming the protective layer 90 includes chemical atomic layer deposition (ALD), chemical vapor deposition, physical vapor deposition or other suitable methods.

[0095] For further information, see Fig.21 , execute step S500: remove the protective layer 90.

[0096] Specifically, wet etching may be used to remove the protective layer 90 .

[0097] Furthermore, based on the above-mentioned shallow trench isolation structure, the active area can be subsequently prepared with a well region (not shown in the figure), a source (not shown), a drain (not shown), a gate oxide layer (not shown) and a gate (not shown) to obtain a corresponding semiconductor device.

[0098] The embodiment of the present invention further provides a shallow trench isolation structure, which is prepared by the preparation method as described above. Fig.21 A schematic diagram of a shallow trench isolation structure prepared using the shallow trench isolation structure provided by an embodiment of the present invention is shown. Fig.21 As shown, the shallow trench isolation structure includes:

[0099] A semiconductor substrate 10;

[0100] The trench 1 is located inside the semiconductor substrate 10, and the bottom surface of the trench 1 is spaced apart from the bottom surface of the semiconductor substrate 10 by a preset distance;

[0101] An active region 11, a semiconductor region disposed between two adjacent trenches 1;

[0102] The isolation layer fills the trench 1. In this embodiment, the isolation layer includes a buffer layer 40 and a filling layer 50.

[0103] Furthermore, based on the obtained shallow trench isolation structure, the existing technology is used to continue to prepare the well region (not shown in the figure), the source (not shown in the figure), the source (not shown in the figure), the gate oxide layer (not shown in the figure) and the gate (not shown in the figure) in the active area to obtain the corresponding semiconductor device.

[0104] The shallow trench isolation structure obtained by the method for preparing the shallow trench isolation structure provided by the present invention can achieve all the technical effects achieved by the preparation method, that is, it can reduce the formation of recessed defects formed on the isolation layer and improve the isolation performance of the device.

[0105] In summary, the shallow trench isolation structure and the preparation method thereof provided by the present invention have the following beneficial effects:

[0106] By forming a protective layer on the side wall of the isolation layer before removing the sacrificial layer, the amount of corrosion on the isolation layer when removing the sacrificial layer can be reduced, thereby reducing the generation of recess defects on the isolation layer. Reducing the recess defects generated on the isolation layer when removing the sacrificial layer can reduce the residual polysilicon at the isolation structure during the subsequent etching of the gate polysilicon, avoid the generation of parasitic leakage current problems, improve the production yield of the shallow trench isolation structure, and reduce the gate sidewall protective layer remaining in the isolation structure, thereby improving the isolation performance of the shallow trench isolation structure. In addition, the preparation method of the present application is simple, and can also reduce the difficulty of the semiconductor device processing process, reduce costs, and save energy and reduce consumption.

[0107] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for preparing a shallow trench isolation structure, characterized in that: Includes steps: Providing a semiconductor substrate, forming a patterned shielding layer on the upper surface of the semiconductor substrate, wherein the bottom of the shielding layer at least includes a sacrificial layer with a preset thickness; Based on the patterned shielding layer, an opening is formed on the upper surface of the semiconductor substrate and a groove is formed in the semiconductor substrate, the bottom surface of the groove is spaced apart from the bottom surface of the semiconductor substrate by a preset distance, and the semiconductor substrate region between two adjacent grooves is an active region; forming an isolation layer filling the opening and the trench and removing the shielding layer; After forming a protective layer on the sidewall of the isolation layer, removing the sacrificial layer; The protective layer is removed.

2. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: The shielding layer includes a first film layer and a second film layer, and the first film layer and the second film layer are sequentially stacked on the sacrificial layer.

3. The method for preparing a shallow trench isolation structure according to claim 2, characterized in that: The material of the first film layer includes silicon nitride; the material of the second film layer includes silicon oxynitride.

4. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: The shielding layer is a photoresist layer.

5. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: The bottom of the shielding layer also includes a stop layer, and the stop layer is arranged between the sacrificial layer and the shielding layer.

6. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: The method of removing the sacrificial layer includes wet etching.

7. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: The method of forming a trench in a substrate of the semiconductor substrate includes plasma etching.

8. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: The isolation layer includes a buffer layer covering the inner wall and bottom surface of the groove and a filling layer filling the remaining gap of the groove, and the buffer layer wraps the side wall and bottom of the filling layer.

9. The method for preparing a shallow trench isolation structure according to claim 8, characterized in that: The buffer layer includes a silicon nitride layer, and the filling layer is a silicon dioxide layer.

10. A shallow trench isolation structure, characterized in that: Prepared by the preparation method according to any one of claims 1 to 9, comprising: Semiconductor substrate; A groove is provided inside the semiconductor substrate, and a bottom surface of the groove is spaced apart from a bottom surface of the semiconductor substrate by a preset distance; An active region is a semiconductor region disposed between two adjacent trenches; An isolation layer fills the trench.

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