Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof, and the method comprises the following steps: providing a substrate which is provided with a process region and a monitoring region; a process groove is formed in the substrate in the process area, a detection groove is formed in the substrate in the monitoring area, and the opening area of the detection groove is gradually reduced in the direction that the detection groove sinks towards the interior of the substrate; forming a target structure for filling the process groove and a detection structure for filling the detection groove; synchronously etching the detection structure and the target structure; and monitoring a signal of the substrate exposed in the monitoring area after etching to obtain the etching depth of the target structure. According to the semiconductor structure and the preparation method thereof, the etching stop control of the target etching layer in the process area is more controllable, the condition of over-etching or insufficient etching is avoided, and the precision and uniformity of the etching process of a semiconductor device are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] As the chip manufacturing process size continues to shrink, the semiconductor industry has entered the nanotechnology process node.

[0003] In this context, the accuracy requirements for the etching process are getting higher and higher, and it is often necessary to control the remaining amount of the target layer to be etched accurately to the angstrom (Å) level. However, this high-precision etching process is extremely difficult. For example, in advanced processes, the feature size of transistors continues to shrink, from 28nm, 14nm to the current 5nm, 3nm, and even 2nm. This means that the etching process must have extremely high precision and resolution to ensure that key micro-nano structures are not damaged when removing materials. And to precisely control the etching depth, an etching stop layer is usually required. This stop layer can stop the etching process when the etching reaches a predetermined depth, thus avoiding over-etching. However, this method increases the complexity of the process and also places higher requirements on the materials and manufacturing processes of the etching stop layer. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a method for manufacturing the same to address the problems in the prior art that the process of the etching stop layer is complex and difficult to meet the high-precision requirements of the semiconductor etching process.

[0005] To achieve the above object, on the one hand, this application provides a method for manufacturing a semiconductor structure, including the following steps:

[0006] Provide a substrate, on which a process area and a monitoring area are provided;

[0007] Form a process groove in the substrate in the process area, and form a detection groove in the substrate in the monitoring area, and the opening area of the detection groove gradually decreases along the direction in which the detection groove depresses into the substrate;

[0008] Form a target structure filling the process groove and a detection structure filling the detection groove;

[0009] Etch the detection structure and the target structure synchronously;

[0010] Monitor the signal of the substrate exposed in the monitoring area after etching to obtain the etching depth of the target structure.

[0011] In one embodiment, forming a process groove in the substrate in the process area and forming a detection groove in the substrate in the monitoring area includes:

[0012] Form an initial process groove in the substrate in the process area;

[0013] Form an initial detection groove in the substrate in the monitoring area. Along the direction in which the initial detection groove is recessed into the substrate, the opening area of the initial detection groove first increases and then decreases;

[0014] Etch and thin the substrate in the process area and the monitoring area to form the process groove and the detection groove.

[0015] In one embodiment, forming the initial detection groove in the substrate in the monitoring area includes:

[0016] Perform dry etching on the substrate in the monitoring area to form an etching groove;

[0017] Perform wet etching on the substrate in the monitoring area based on the etching groove to form the initial detection groove.

[0018] In one embodiment, before performing wet etching on the substrate in the monitoring area based on the etching groove to form the initial detection groove, it further includes:

[0019] Form a patterned hard mask layer on the substrate. Among them, the hard mask layer on the substrate in the process area covers the substrate, and the hard mask layer on the substrate in the monitoring area has a mask opening.

[0020] In one embodiment, the hard mask layer is formed before performing dry etching on the substrate in the monitoring area to form the etching groove.

[0021] In one embodiment, before etching and thinning the substrate in the process area and the monitoring area to form the process groove and the detection groove, it further includes:

[0022] Remove the hard mask layer.

[0023] In one embodiment, forming the initial process groove in the substrate in the process area includes:

[0024] Form a patterned first photoresist layer above the substrate in the monitoring area;

[0025] Perform etching on the substrate in the process area based on the first photoresist layer to form the initial process groove in the substrate in the process area;

[0026] Remove the first photoresist layer.

[0027] In one embodiment, the depth of the detection groove is the same as the depth of the process groove.

[0028] In one embodiment, forming the target structure filling the process groove and the detection structure filling the detection groove includes:

[0029] Forming an etchable structure material layer covering the substrate and filling the detection groove and the process groove;

[0030] Etching the etchable structure material layer until the substrate in the monitoring area is exposed. After etching, the etchable structure material layer filling the detection groove serves as the detection structure, and the etchable structure material layer filling the process groove serves as the target structure.

[0031] In a second aspect, the present application further provides a semiconductor structure, which is prepared by using the preparation method of the semiconductor structure described in any one of the above.

[0032] In the above semiconductor structure and its preparation method, by providing a process area and a monitoring area on the substrate, forming a detection groove in the monitoring area, and the opening area of the detection groove gradually decreases along the direction in which the detection groove depresses into the substrate. Therefore, during the synchronous etching process of the target structure in the process area and the detection structure in the monitoring area, the area of the substrate exposed in the monitoring area gradually increases. Then, based on the change in the signal of the substrate in the monitoring area, the etching depth of the target structure in the process area can be accurately judged, making the etching stop control of the target etched layer in the process area more controllable, avoiding over-etching or under-etching situations, not only improving the accuracy and uniformity of the etching process of semiconductor devices, reducing process deviation and cost, but also optimizing the performance and reliability of semiconductor devices, and significantly improving the stability and production efficiency of the process. Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0034] Figure 1 It is a flowchart of the preparation method of the semiconductor structure provided in an embodiment;

[0035] Figure 2 It is a cross-sectional structure schematic diagram after forming a patterned first photoresist layer in the preparation method of the semiconductor structure provided in an embodiment;

[0036] Figure 3Schematic cross-sectional structure diagram after forming an initial process groove in a method for preparing a semiconductor structure provided in an embodiment;

[0037] Figure 4 Schematic cross-sectional structure diagram after removing a first photoresist layer in a method for preparing a semiconductor structure provided in an embodiment;

[0038] Figure 5 Schematic cross-sectional structure diagram after forming a hard mask material layer in a method for preparing a semiconductor structure provided in an embodiment;

[0039] Figure 6 Schematic cross-sectional structure diagram after forming a patterned second photoresist layer in a method for preparing a semiconductor structure provided in an embodiment;

[0040] Figure 7 Schematic cross-sectional structure diagram after forming an initial detection groove in a method for preparing a semiconductor structure provided in an embodiment;

[0041] Figure 8 Schematic cross-sectional structure diagram after removing a second photoresist layer in a method for preparing a semiconductor structure provided in an embodiment;

[0042] Figure 9 Schematic cross-sectional structure diagram after forming an initial detection groove in a method for preparing a semiconductor structure provided in an embodiment;

[0043] Figure 10 Schematic cross-sectional structure diagram after removing a hard mask layer in a method for preparing a semiconductor structure provided in an embodiment;

[0044] Figure 11 Schematic cross-sectional structure diagram after forming a detection groove and a process groove in a method for preparing a semiconductor structure provided in an embodiment;

[0045] Figure 12 Schematic cross-sectional structure diagram after forming an etched structure material layer in a method for preparing a semiconductor structure provided in an embodiment;

[0046] Figure 13 Schematic cross-sectional structure diagram after forming a target structure and a detection structure in a method for preparing a semiconductor structure provided in an embodiment.

[0047] Explanation of reference numerals:

[0048] 1 - Substrate, 11 - Process region, 12 - Monitoring region, 2 - Process groove, 21 - Initial process groove, 3 - Detection groove, 31 - Initial detection groove, 311 - Etching groove, 4 - Target structure, 5 - Detection structure, 6 - First photoresist layer, 7 - Hard mask layer, 71 - Mask opening, 72 - Hard mask material layer, 8 - Second photoresist layer, 9 - Etched structure material layer. Detailed implementation manners

[0049] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the description of this application in this specification are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0051] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type or part discussed below may be referred to as the second element, component, region, layer or part.

[0052] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. can be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It should be understood that, in addition to the orientation shown in the drawings, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the drawings is flipped, an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0053] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / have" etc. specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0054] Please refer to Figure 1 , in an embodiment of the present application, a method for preparing a semiconductor structure is provided, including the following steps:

[0055] Step S1: Provide a substrate 1, on which a process region 11 and a monitoring region 12 are provided;

[0056] Step S2: Form a process groove 2 in the substrate 1 of the process region 11, and form a detection groove 3 in the substrate 1 of the monitoring region 12, and the opening area of the detection groove 3 gradually decreases along the direction in which the detection groove 3 depresses into the substrate 1;

[0057] Step S3: Form a target structure 4 filling the process groove 2 and a detection structure 5 filling the detection groove 3;

[0058] Step S4: Synchronously etch the detection structure 5 and the target structure 4;

[0059] Step S5: Monitor the signal of the substrate 1 exposed in the monitoring region 12 after etching to obtain the etching depth of the target structure 4.

[0060] In the above method for preparing a semiconductor structure, by providing a process region 11 and a monitoring region 12 on the substrate 1, and forming a detection groove 3 in the monitoring region 12, and the opening area of the detection groove 3 gradually decreases along the direction in which the detection groove 3 depresses into the substrate 1, during the synchronous etching of the target structure 4 in the process region 11 and the detection structure 5 in the monitoring region 12, the area of the substrate 1 exposed in the monitoring region 12 gradually increases, then the etching depth of the target structure 4 in the process region 11 can be accurately judged based on the change of the signal of the substrate 1 in the monitoring region 12, making the etching stop control of the target structure 4 in the process region 11 more controllable, avoiding over-etching or under-etching, not only improving the accuracy and uniformity of the etching process of semiconductor devices, reducing process deviation and cost, but also optimizing the performance and reliability of semiconductor devices, and significantly improving the stability and production efficiency of the process.

[0061] Execute step S1 to provide a substrate 1, on which a process region 11 and a monitoring region 12 are provided.

[0062] During the semiconductor manufacturing process, process area 11 refers to a specific area on the wafer for manufacturing various semiconductor devices (such as transistors, diodes, capacitors, etc.). The design and manufacturing of process area 11 are the core of the entire semiconductor process, and its purpose is to achieve specific electrical functions through precise patterning and material processing.

[0063] Exemplarily, substrate 1 can be the bottom substrate structure of the semiconductor device. At this time, the material of substrate 1 includes silicon, silicon carbide, silicon germanium, or other suitable semiconductor materials, which are easy to process and have high process compatibility. It also provides stable physical support for the semiconductor device, ensuring that it can withstand various process steps (such as lithography, etching) without deformation during the process. In this embodiment, substrate 1 is a silicon substrate.

[0064] In addition, substrate 1 can also be a structure with a semiconductor device formed structure layer, which can be set according to actual conditions.

[0065] Please refer to Figures 2 to 11 , perform step S2, form process groove 2 in substrate 1 of process area 11, and form detection groove 3 in the substrate of monitoring area 12. The opening area of detection groove 3 gradually decreases along the direction in which detection groove 3 depresses into substrate 1.

[0066] Among them, forming process groove 2 in substrate 1 of process area 11 and forming detection groove 3 in substrate 1 of monitoring area 12 includes:

[0067] Step S21: Form initial process groove 21 in substrate 1 of process area 11;

[0068] Among them, as Figures 2 to 4 shown, forming initial process groove 21 in substrate 1 of process area 11 includes:

[0069] Step S211: Form a patterned first photoresist layer 6 above substrate 1 of monitoring area 12; the method of forming the first photoresist layer 6 includes coating or other suitable methods;

[0070] Step S212: Etch substrate 1 of process area 11 based on the first photoresist layer 6 to form initial process groove 21 in substrate 1 of process area 11; the method of etching substrate 1 of process area 11 includes wet etching, dry etching, or other suitable methods; the formation of initial process groove 21 prepares for the subsequent formation of target structure 4 and the precise monitoring and control of the etching amount of target structure 4, ensuring the smooth progress of subsequent process steps;

[0071] Step S213: Remove the first photoresist layer 6; the method of removing the first photoresist layer 6 includes wet etching, dry etching, chemical mechanical polishing, or other suitable methods;

[0072] Step S22: An initial detection groove 31 is formed in the substrate 1 of the monitoring area 12. Along the direction in which the initial detection groove 31 depresses into the substrate 1, the opening area of the initial detection groove 31 first increases and then decreases.

[0073] Among them, as Figures 5 to 11 shown, forming the initial detection groove 31 in the substrate 1 of the monitoring area 12 includes:

[0074] Step S221: The substrate 1 of the monitoring area 12 is dry-etched to form an etching groove 311; the etching groove 311 obtained by dry etching can achieve relatively flat vertical sidewalls.

[0075] Step S222: The etching groove 311 is wet-etched to form the initial detection groove 31; wet etching has high selectivity and can precisely selectively remove specific materials to obtain the initial detection groove 31 with the required shape. When the etching groove 311 is etched by wet etching, the etching solution used includes tetramethylammonium hydroxide.

[0076] And before wet-etching the substrate 1 of the monitoring area 12 based on the etching groove 311 to form the initial detection groove 31, it further includes:

[0077] A patterned hard mask layer 7 is formed on the substrate 1. Among them, the hard mask layer 7 on the substrate 1 in the process area 11 covers the substrate 1, and the hard mask layer 7 on the substrate 1 in the monitoring area 12 is formed with a mask opening 71. Wet-etching the substrate 1 of the monitoring area 12 based on the etching groove 311 is formed based on the hard mask layer 7 with a mask opening 71 formed on the substrate 1 in the monitoring area 12. The hard mask layer 7 usually has higher chemical stability and can better resist the erosion of the etching solution in wet etching, thereby increasing the selectivity ratio between the hard mask layer 7 and the material to be etched and enabling high-precision pattern etching.

[0078] Exemplarily, the hard mask layer 7 is formed before dry-etching the substrate 1 of the monitoring area 12 to form the etching groove 311. That is, the hard mask layer 7 formed on the substrate 1 in the process area 11 covers the substrate 1, which can prevent the substrate 1 in the process area 11 from being damaged during subsequent processing and ensure the smooth progress of subsequent processes.

[0079] Among them, forming the patterned hard mask layer 7 on the substrate 1 includes:

[0080] A hard mask material layer 72 is formed on the substrate 1; among them, the method of forming the hard mask material layer 72 includes chemical vapor deposition or other suitable methods, and the material of the hard mask material layer 72 includes silicon nitride or other suitable materials.

[0081] Etch the hard mask material layer 72 on the substrate 1 in the monitoring area 12 to form a mask opening 71, so as to form a patterned hard mask layer 7.

[0082] At this time, dry-etch the substrate 1 in the monitoring area 12 to form an etch groove 311, including:

[0083] Form a patterned second photoresist layer 8 on the hard mask material layer 72; the method of forming the second photoresist layer 8 includes coating or other suitable methods;

[0084] Based on the patterned second photoresist layer 8, etch the hard mask material layer 72 and the substrate 1 in the monitoring area 12, and form an etch groove 311 in the substrate 1 in the monitoring area 12;

[0085] Remove the patterned second photoresist layer 8; the method of removing the patterned second photoresist layer 8 includes dry etching, wet etching or other suitable methods. After removing the patterned second photoresist layer 8, it further includes a step of etching and deepening the etch groove 311 so that the etch groove 311 can meet the requirements of subsequent processes;

[0086] Step S23: Etch and thin the substrate 1 in the process area 11 and the monitoring area 12 to form a process groove 2 and a detection groove 3. Among them, the method of etching and thinning the substrate 1 in the process area 11 and the monitoring area 12 includes dry etching or other suitable methods. The opening area of the initial detection groove 31 first increases and then decreases along the direction in which the initial detection groove 31 depresses into the substrate 1. After etching and thinning the substrate 1 in the monitoring area 12, the opening area of the remaining part of the initial detection groove 31 decreases along the direction in which the initial detection groove 31 depresses into the substrate 1, and the required detection groove 3 can be formed. By etching and thinning the substrate 1 in the process area 11, the depth of the detection groove 3 can be controlled to be the same as the depth of the process groove 2. The area change of the substrate 1 in the monitoring area 12 revealed during the subsequent etching process can directly reflect the etching depth, ensuring the synchronization of the target structure 4 in the subsequent process area 11 and the detection structure 5 in the monitoring area 12 during the etching process. The etching non-uniformity caused by the initial height difference is reduced, and the control of the etching process becomes simpler. More accurate monitoring and control are achieved during the etching process of the target structure, and at the same time, the consistency of the target structure 4 in the process area 11 and the detection structure 5 in the monitoring area 12 in the process is ensured, so that the etching state of the process area 11 can be more accurately inferred through the signal in the monitoring area 12.

[0087] In addition, before etching and thinning the substrate 1 in the process area 11 and the monitoring area 12 to form a process groove 2 and a detection groove 3, it further includes: removing the hard mask layer 7. The method of removing the hard mask layer 7 includes wet etching, dry etching, chemical mechanical polishing or other suitable methods.

[0088] Please refer to Figures 12 to 13 , perform step S3 to form the target structure 4 in the filling process trench 2 and the detection structure 5 in the filling detection trench 3.

[0089] Among them, forming the detection structure 5 in the filling detection trench 3 and the target structure 4 in the filling process trench 2 includes:

[0090] Step S31: Form an etchable structure material layer 9 covering the substrate 1 and filling the detection trench 3 and the process trench 2; the method for forming the etchable structure material layer 9 includes chemical vapor deposition, physical vapor deposition, or other suitable methods;

[0091] Step S32: Etch the etchable structure material layer 9 and etch until the substrate 1 in the monitoring area 12 is exposed. Among them, the etchable structure material layer 9 in the detection trench 3 after etching serves as the detection structure 5, and the etchable structure material layer 9 in the process trench 2 after etching serves as the target structure 4. The methods for etching the etchable structure material layer 9 include dry etching, wet etching, and chemical mechanical polishing.

[0092] Among them, in semiconductor manufacturing, the etchable structure material layer 9 can be multiple material layers, specifically depending on the device design and process requirements. For example, the etchable structure material layer 9 includes the active area, gate structure, dielectric layer, interconnect layer, and other functional layers in semiconductor devices. Such as polycrystalline silicon (Poly-Si) that can be used as the active area and gate, oxides (such as SiO 2 ), nitrides (such as Si 3 N 4 ) that can be used as the isolation protection layer, silicon-rich nitride (SiON) that can be used as the gate dielectric layer, and metal layers (such as aluminum and copper) that can be used as the interconnect layer. By precisely controlling the etching process of the above-mentioned etchable structure material layer 9, high-precision patterning and device manufacturing can be achieved.

[0093] The thinned etchable structure material layer 9 is flush with the upper surface of the substrate 1 in the monitoring area 12. That is, during the subsequent etching process of the target structure in the process area, the etching amount of the target structure can be effectively monitored.

[0094] Perform steps S4 to S5 to synchronously etch the detection structure 5 and the target structure 4; monitor the signal of the substrate 1 exposed in the monitoring area 12 after etching to obtain the etching depth of the target structure 4.

[0095] Exemplarily, the method for detecting the signal change of the substrate 1 revealed in the monitoring area 12 after etching the detection structure 5 includes optical emission spectroscopy, white light interference, or other suitable detection methods. The opening area of the detection groove 3 gradually decreases along the direction in which the detection groove 3 depresses into the substrate 1. During the etching process of the detection structure 5 in the detection groove 3, the area of the substrate 1 in the revealed monitoring area 12 increases, and the stronger the signal of the substrate 1 in the detected monitoring area 12, which can ensure that the etching depth of the target structure 4 in the process area 11 can be effectively monitored based on the detected signal of the substrate 1 in the monitoring area 12.

[0096] By monitoring the signal change of the substrate 1 revealed in the monitoring area 12 to obtain the etching depth of the target structure 4, the etching depth of the target structure 4 can be further regulated based on the monitoring result. For example, if the etching depth does not reach the required amount, the target structure 4 can be continuously etched to ensure that the etching depth of the target structure 4 reaches the required amount, realizing precise control and optimization of the etching process, not only improving the accuracy and uniformity of etching, but also reducing process deviation and cost, significantly improving the yield and reliability of the device. This monitoring method is particularly suitable for the high-precision etching requirements in advanced semiconductor manufacturing, and can significantly improve the stability and production efficiency of the process.

[0097] In some embodiments, the present application also provides a semiconductor structure, which is prepared by the preparation method of the semiconductor structure described above.

[0098] The semiconductor structure prepared by the preparation method of the semiconductor structure described above improves the yield and reliability of the device and meets the process requirements of the nanotechnology process node.

[0099] In the description of this specification, the description with reference to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials, or features described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0100] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0101] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The steps include: Providing a substrate, wherein a process area and a monitoring area are provided on the substrate; Forming a process groove in the substrate of the process area, and forming a detection groove in the substrate of the monitoring area, wherein the opening area of ​​the detection groove gradually decreases along the direction in which the detection groove is recessed into the substrate; forming a target structure filling the process slot and a detection structure filling the detection slot; performing synchronous etching on the detection structure and the target structure; The signal of the substrate exposed in the monitoring area after etching is monitored to obtain the etching depth of the target structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of forming a process slot in the substrate in the process area and forming a detection slot in the substrate in the monitoring area comprises: forming an initial process groove in the substrate of the process zone; An initial detection groove is formed in the substrate of the monitoring area, and along the direction in which the initial detection groove is sunken into the substrate, the opening area of ​​the initial detection groove increases first and then decreases; The substrate located in the process area and the monitoring area is etched and thinned to form the process groove and the detection groove.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The forming of an initial detection groove in the substrate of the monitoring area comprises: Dry etching the substrate in the monitoring area to form an etching groove; The substrate of the monitoring area is wet-etched based on the etching groove to form the initial detection groove.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: Before wet etching the substrate of the monitoring area based on the etching groove to form the initial detection groove, the method further includes: A patterned hard mask layer is formed on the substrate, wherein the hard mask layer on the substrate in the process area covers the substrate, and the hard mask layer on the substrate in the monitoring area is formed with a mask opening.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that: The hard mask layer is formed before the substrate in the monitoring area is dry-etched to form the etching groove.

6. The method for preparing a semiconductor structure according to claim 4, characterized in that: Before etching and thinning the substrate located in the process area and the monitoring area to form the process slot and the detection slot, the method further includes: The hard mask layer is removed.

7. The method for preparing a semiconductor structure according to claim 2, characterized in that: The forming of an initial process groove in the substrate in the process zone comprises: forming a patterned first photoresist layer above the substrate in the monitoring area; Etching the substrate in the process area based on the first photoresist layer to form the initial process groove; The first photoresist layer is removed.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: The depth of the detection groove is the same as the depth of the process groove.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that: The forming of the target structure filling the process slot and the detection structure filling the detection slot comprises: forming a layer of structural material to be etched that covers the substrate and fills the detection groove and the process groove; The structural material layer to be etched is etched until the substrate in the monitoring area is exposed, and the structural material layer to be etched that fills the detection groove after etching is used as the detection structure, and the structural material layer to be etched that fills the process groove after etching is used as the target structure.

10. A semiconductor structure, characterized in that: The semiconductor structure is prepared by using the method for preparing a semiconductor structure as claimed in any one of claims 1 to 9.

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