BEOL manufacturing method including dummy line removal

Abstract

A method of forming a back-end-of-line (BEOL) region of an integrated circuit (IC) device is provided. A method of forming a BEOL region of an IC device includes converting non-full-track standard cells designed for the BEOL region to full-track standard cells by adding dummy metal lines to the non-full-track standard cells. The method includes removing the dummy metal line. Further, the method includes forming a top via after removing the dummy metal line.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 602,946, filed on November 27, 2023, entitled “Integrated Circuit Device Including Recessed Metal Lines and Methods of Forming the Same,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to the field of integrated circuit (IC) devices, and more particularly, to metal lines in a back-end-of-line (BEOL) region of an IC device. Background Art

[0004] The BEOL region of an IC device may include multiple vertical levels of metal lines (e.g., interconnect wiring). An upper metal line in the BEOL region may be coupled to a lower metal line in the BEOL region through a metal via. When forming a standard cell in the BEOL region, using a full track design in which all signal line regions are filled with metal may increase process margins (e.g., metal patterning process margins) relative to a non-full track design in which at least one signal line region has an opening therein. However, a full track design may result in higher capacitance than a non-full track design (due to the increased amount of metal). Summary of the invention

[0005] According to some embodiments of the present invention, a method of forming a BEOL region of an IC device may include converting a non-full track standard cell designed for the BEOL region into a full track standard cell by adding a dummy metal line to the non-full track standard cell. The method may include performing metal patterning based on the full track standard cell. The method may include removing the dummy metal line after performing the metal patterning. In addition, the method may include forming a top via after removing the dummy metal line.

[0006] According to some embodiments of the present invention, a method for forming a BEOL region of an IC device may include designing non-dummy metal lines in corresponding signal line regions of the BEOL region. The method may include designing dummy metal lines in openings in at least some of the signal line regions after designing the non-dummy metal lines. The method may include performing metal patterning on the signal line regions after designing the dummy metal lines. The method may include removing the dummy metal lines after performing the metal patterning. In addition, the method may include forming a top via in at least one of the signal line regions after removing the dummy metal lines.

[0007] According to some embodiments of the present invention, a method for forming a BEOL region of an IC device may include forming a non-full track standard cell design for the BEOL region. The method may include converting the non-full track standard cell design to a full track standard cell design by adding a dummy metal line to the non-full track standard cell design. Adding the dummy metal line may include designing metal in all openings in a signal line region of the non-full track standard cell design. The method may include removing the dummy metal line by performing a subtractive metal etch of the dummy metal line. In addition, the method may include forming a top via after removing the dummy metal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a schematic block diagram of an IC device according to some embodiments herein.

[0009] Figure 1B yes Figure 1A An example plan view of a non-full track standard cell in the BEOL region of an IC device.

[0010] Figure 1C yes Figure 1B Cross-sectional view of a non-full track standard unit along line A-A'.

[0011] Figure 1D yes Figure 1B Cross-sectional view of a non-full track standard unit along line B-B'.

[0012] Figure 2A-2C is a plan view, and Figure 2D-Figure 2N is a cross-sectional view showing the formation of some embodiments according to the present invention Figure 1B-Figure 1D operation of the standard cell.

[0013] Figure 3A and Figure 3B is a cross-sectional view illustrating an operation of removing a dummy metal line according to some embodiments herein.

[0014] Figure 3C and Figure 3D According to some embodiments of the present invention, Figure 3A and Figure 3B The operation shown in FIG. 1 is a plan view of a signal line area from which a dummy metal line is removed.

[0015] Figure 4 is corresponding to Figure 2A-2N Flowchart of the operations shown in . DETAILED DESCRIPTION

[0016] According to an embodiment of the present invention, a method for forming a BEOL region of an IC device is provided, the method including forming a dummy metal line that is subsequently removed. For example, the dummy metal line can be designed to convert a non-full track standard cell of the BEOL region into a full track standard cell of the BEOL region, and the dummy metal line can be physically removed after performing metal patterning based on the full track standard cell (e.g., based on a digital design of the full track standard cell). Removing the dummy metal line can convert the full track standard cell back to a non-full track standard cell. Process margin can be increased by performing metal patterning based on the full track standard cell (rather than the non-full track standard cell), and capacitance can be reduced by converting the full track standard cell back to a non-full track standard cell (which has less metal than the full track standard cell) after performing metal patterning. Therefore, the method including adding and removing dummy metal lines can advantageously benefit from the higher process margin of the full track design without suffering from capacitance loss that may be caused by the increased metal in the full track design.

[0017] Example embodiments will be described in more detail with reference to the accompanying drawings.

[0018] Figure 1A 1 is a schematic block diagram of an IC device 100 according to some embodiments. The IC device 100 may be, for example, a semiconductor memory device for storing data and / or a semiconductor logic device for processing data. The IC device 100 includes a substrate (e.g., a semiconductor substrate) 110, a BEOL region 130 on the substrate 110, and a front-end-of-line (FEOL) and / or middle-end-of-line (MEOL) region 120 between the BEOL region 130 and the substrate 110 (in a vertical direction Z). As an example, the FEOL / MEOL region 120 may include devices such as transistors, capacitors, and / or resistors. In addition, the BEOL region 130 may include interconnects, vias, and dielectric structures.

[0019] Figure 1B1 is an example plan view of a non-full track standard cell 160 of the BEOL region 130. The non-full track standard cell 160 includes signal lines 134a-134e (e.g., metal signal lines 134a-134e, collectively referred to as signal lines 134) in corresponding signal line regions 132a-132e (collectively referred to as signal line regions 132). In addition, some signal line regions 132 include openings 136 (including openings 136a-136f) without metal. For example, signal line region 132b includes openings 136a and 136b, signal line region 132c includes opening 136c, signal line region 132d includes opening 136d, and signal line region 132e includes openings 136e and 136f. Therefore, the signal lines 134b-134e do not completely fill the signal line regions 132b-132e, respectively (e.g., do not extend continuously in the horizontal direction X between the opposite ends of the signal line regions 132b-132e). The openings 136 distinguish the non-full-track standard cell 160 from the full-track standard cell in which each signal line region 132 is filled with metal and has no openings 136 therein.

[0020] The signal lines 134 may extend longitudinally parallel to each other in a direction X. The signal line regions 132 are spaced apart from each other by spacings (e.g., metal-free gaps) 142 in another horizontal (i.e., lateral) direction Y that intersects (e.g., is perpendicular to) the directions X and Z. According to some embodiments, the signal lines 134a-134e may have a spacing 140 in the Y direction, and the spacing 140 may be a constant spacing. Furthermore, as used herein, the term "signal line region" refers to a portion of a standard cell of the BEOL region 130 that will be completely filled with the signal lines 134 if the standard cell is a full-track standard cell.

[0021] The signal lines 134b and 134e have corresponding metal vias 138a and 138b (collectively referred to as vias 138) thereon. The vias 138 can couple the signal line 134 to the upper layer of the metal line. Figure 1B For example, signal line 134 may be a lower metal line of BEOL region 130, and via 138 may couple the lower metal line to the upper metal line of BEOL region 130. Thus, BEOL region 130 may include various BEOL elements, including various metal lines (e.g., metal / interconnect wiring) and metal vias.

[0022] Figure 1C It is along Figure 1B A cross-sectional view of a non-full track standard unit 160 along line AA'. Figure 1CAs shown, the signal lines 134 are at the same vertical level in the direction Z. For example, the signal lines 134 may be BEOL regions 130 ( Figure 1A ) of the metal lines, each of which is a lower metal line at a low (eg, lowest) level.

[0023] Signal line 134b ( Figure 1B ) Not in Figure 1C As shown in FIG. 1 , since line AA′ passes through the signal line region 132 b ( Figure 1B ) in the opening 136a ( Figure 1B ). The opening 136a may include the first insulating layer 156 therein and may be free of metal. As an example, the opening 136a may be filled with the first insulating layer 156 or a combination of the first insulating layer 156 and another insulating layer. The first insulating layer 156 may also be on the sidewalls and uppermost surfaces of the signal lines 134a and 134c-134e.

[0024] According to some embodiments, the first metal adhesion layer 152 may be on the lowermost surface of the signal line 134. In addition, the signal line 134 may be on the second insulating layer 150, and the first metal adhesion layer 152 may be located between the signal line 134 and the second insulating layer 150 in the vertical direction Z. The first metal adhesion layer 152 may enhance adhesion between the signal line 134 and the second insulating layer 150.

[0025] In some embodiments, the second metal adhesion layer 154 may be between the first insulating layer 156 and the sidewalls and uppermost surfaces of the signal lines 134a and 134c-134e. For example, the second metal adhesion layer 154 may be a thin conformal layer, and the first insulating layer 156 may fill the gaps between the signal lines 134. In some embodiments, the second metal adhesion layer 154 may have a thickness similar to (or equal to) that of the first metal adhesion layer 152. The second metal adhesion layer 154 may enhance the adhesion between the signal lines 134 and the first insulating layer 156.

[0026] In some embodiments, the second insulating layer 150 and the first insulating layer 156 (collectively referred to as the insulating layer) may each include different insulating materials. Example materials of the first metal adhesion layer 152, the second metal 154 (collectively referred to as the adhesion layer), and the insulating layers 150 and 156 are relatively Figure 2D , Figure 2E , Figure 2M and Figure 2N describe.

[0027] Figure 1D It is a non-full track standard unit 160 along Figure 1B A cross-sectional view of the line B-B'. Figure 1DAs shown, the vias 138 are at the same vertical level in the direction Z, and the level is above the vertical level of the signal line 134. For example, the vias 138 can each be at the BEOL region 130 ( Figure 1A ). The intermediate level may be between the level of the signal line 134 and the level of the upper metal line in the direction Z. For simplicity of description, Figure 1D The levels of the upper metal lines are omitted from the view in FIG. As an example, the upper metal lines may be at a high (eg, highest) level of the BEOL region 130 .

[0028] In addition, the adhesion layer 154 and the insulating layer 156 may be on the sidewalls of the through hole 138. Figure 1B ) Not in Figure 1D As shown in FIG. 1 , since line BB′ passes through signal line regions 132c, 132d ( Figure 1B ) in the openings 136c, 136d ( Figure 1B ). The openings 136 c , 136 d may include the insulating layer 156 therein and may be free of metal. For example, the openings 136 c , 136 d may be filled with the insulating layer 156 or a combination of the insulating layer 156 and the adhesion layer 154 .

[0029] Figure 2A-2C is a plan view, Figure 2D-Figure 2N is a cross-sectional view showing the formation of some embodiments according to the present invention Figure 1B-Figure 1D The operation of the standard cell 160. Figure 4 is corresponding to Figure 2A-2N Flowchart of the operations shown in .

[0030] like Figure 2A and Figure 4 As shown, the BEOL region 130 ( Figure 1A ) designs / forms (block 410) a non-full track standard cell 260. For example, a human circuit designer may provide a digital design 268 of a standard cell 260. The standard cell 260 includes a signal line region 132 (including signal line regions 132a-132e) having openings 236 (including openings 236a-236f) therein. Thus, the signal line region 132 is not completely filled with metal. For example, signal line region 132b may include openings 236a and 236b, signal line region 132c may include opening 236c, signal line region 132d may include opening 236d, and signal line region 132e may include openings 236e and 236f. ​​Signal line regions 132a-132e include metal lines 234a-234e (collectively referred to as metal lines 234), respectively. In order to align metal lines 234 with dummy metal lines 276 ( Figure 2B) (including open dummy metal lines 276a-276f), metal lines 234 may be referred to herein as “non-dummy” metal lines, which may be IC device 100 ( Figure 1A ) are required for operation. Furthermore, although dummy metal lines 276 include metal, IC device 100 does not require them to operate, and thus may be referred to herein as “dummy” metal lines.

[0031] like Figure 2B and Figure 4 As shown, a dummy metal line 276 can be added to the standard cell 260. Figure 2A The non-full track standard cell 260 is converted (block 412) to a full track standard cell 262 (eg, its digital design 264). For example, the signal line region 132 may be filled with metal to form all openings 236 ( Figure 2A ) to design / form the dummy metal line 276. Figure 2B As shown, dummy metal lines 276a-276f may be added to (eg, may fill) openings 236a-236f, respectively. Figure 2A ). The ends of dummy metal lines 276 may contact the ends of metal lines 234 , and signal line regions 132 may thus be continuous metal between opposite ends of each signal line region 132 .

[0032] In some embodiments, metal line 234 and dummy metal line 276 may each include the same metal. As an example, metal line 234 and dummy metal line 276 may each include ruthenium (Ru). In other examples, metal line 234 and dummy metal line 276 may each include rhodium (Rh) or iridium (Ir). Therefore, there is no visible interface between metal line 234 and dummy metal line 276. However, in order to distinguish metal line 234 from dummy metal line 276, Figure 2B The interface between metal line 234 and dummy metal line 276 is shown in FIG.

[0033] According to some embodiments, metal line 234 and dummy metal line 276 may each have the same height in direction Z. Therefore, the uppermost surface of metal line 234 may be coplanar with the uppermost surface of dummy metal line 276. However, in order to indicate that metal via 138 ( Figure 1B ) location, Figure 2A and Figure 2B Via locations 238a, 238b are shown. Figure 2A and Figure 2B Also shown are spaces 142 by which the signal line regions 132 are separated from each other in the direction Y.

[0034] In some embodiments, the operations of forming (block 410) a non-full track standard cell 260 and converting it (block 412) to a full track standard cell 262 by adding dummy metal lines 276 may be performed digitally rather than physically. For example, a human circuit designer may perform these operations using software (e.g., design tool software). As an example, by filling all openings 236 ( Figure 2A ) to design / form dummy metal line 276 may include digitally (rather than physically) filling opening 236 in the digital design of full track standard cell 262. Thus, Figure 2A and Figure 2B The non-full track standard cell 260 and the full track standard cell 262 shown in the figure may be digital designs 268 and 264, respectively (i.e., designs that exist in digital data). In contrast, subsequent operations (e.g., blocks 414-420) may be performed physically (e.g., by physical patterning of metal) based on the digital design 264 (of the full track standard cell 262 with dummy metal lines 276) created by the designer.

[0035] like Figure 2C-2E and Figure 4 As shown, the full track standard unit 262 (e.g., based on its digital design 264 ( Figure 2B )) metal patterning is performed (block 414). As an example, the metal patterning can include performing Ru patterning on the Ru block / layer to form the full track standard cell 262 (e.g., to form the Ru metal line 234 and / or the Ru dummy metal line 276). The metal patterning can provide a physical (rather than digital) structure 266 of the full track standard cell 262. Figure 2D It is along Figure 2C A cross-sectional view of line A-A', and Figure 2E It is along Figure 2C Cross-sectional view along line BB'. Figure 2D and Figure 2E It is shown that metal line 234 and dummy metal line 276 can have coplanar uppermost surfaces. Figure 2E Via location 238a and via location 238b are shown, with via location 238a being where metal via 138 ( Figure 1B ) is a portion of metal line 234b, and via location 238b is a portion of metal line 234e that will subsequently form another metal via 138. In some embodiments, metal patterning may include performing self-aligned universal patterning (SAUP) on full track standard cell 262 (e.g., to form physical structure 266 ( Figure 2C)). According to some embodiments, the metal patterning may include performing lithography-etch-lithography-etch (LELE) patterning on the full track standard cell 262 (e.g., to form the physical structure 266 of the full track standard cell 262). As an example, the metal patterning may be SA-LELE, which is a type of SAUP.

[0036] Figure 2D and Figure 2E It is also shown that metal line 234 and dummy metal line 276 may be on metal adhesion layer 252 (also referred to as adhesion layer 252). For example, adhesion layer 252 may be formed on insulating layer 150, and then metal line 234 and dummy metal line 276 may be formed on metal adhesion layer 252. Adhesion layer 252 may include a metal that improves adhesion of metal line 234 and dummy metal line 276 to insulating layer 150. As an example, adhesion layer 252 may include aluminum (Al) or chromium (Cr). In addition, adhesion layer 252 may include a nitride (e.g., metal nitride) layer. Adhesion layer 252 is then patterned / etched to form adhesion layer 152 ( Figure 1C ). The insulating layer 150 may include, for example, an oxide layer or a nitride layer.

[0037] As described herein, the operations of forming (block 410) the non-full track standard cell 260 and converting (block 412) it to the full track standard cell 262 may be performed digitally rather than physically. Thus, performing metal patterning based on the full track standard cell 262 may include performing metal patterning based on the digital design 264 ( Figure 2B ) The metal block is patterned to form the spacer 142, the metal line 234, and the dummy metal line 276. Therefore, the spacer 142, the metal line 234, and the dummy metal line 276 may not physically exist (in the physical structure 266 ( Figure 2C ) until metal patterning is performed.

[0038] like Figure 2F-Figure 2I and Figure 4 As shown, metal patterning can be performed ( Figure 2C ) and then remove (block 416) the dummy metal line 276. The dummy metal line 276 is removed in the signal line area 132 ( Figure 2A ) are formed in at least some (eg, at least two, but not necessarily all) of the plurality of openings 236 ( Figure 2A ), and thereby converting the full track standard cell 262 back to a non-full track standard cell 260 ( Figure 2A ). Figure 2F and Figure 2H is a graph showing the metal patterning along line A-A' ( Figure 2C ) a cross-sectional view of the operations taking place. Figure 2G and2I is a graph showing the metal patterning along line BB' ( Figure 2C ) a cross-sectional view of the operations taking place.

[0039] In some embodiments, removing dummy metal line 276 may include forming barrier pattern 280 that vertically overlaps all (non-dummy) metal lines 234 of full-track standard cell 262 and does not vertically overlap dummy metal line 276 , such as Figure 2F and Figure 2G As shown. Therefore, when the uppermost surface of the metal line 234 is covered by the blocking pattern 280, the uppermost surface of the dummy metal line 276 is exposed by the blocking pattern 280. The blocking pattern 280 may be an insulating material having an etching selectivity with respect to the dummy metal line 276 and with respect to the adhesion layer 252. In addition, the blocking pattern 280 may not exist in the sidewalls of the metal line 234 and the sidewalls of the dummy metal line 276. As a result, a relatively small amount of material of the blocking pattern 280 may be used, which may reduce costs. According to some embodiments, the blocking pattern 280 may include a plurality of spaced-apart portions, each of which is narrower than the pitch of the metal line 234 in the direction Y.

[0040] When barrier pattern 280 vertically overlaps metal line 234 , removal of dummy metal line 276 may be performed by subtractive metal (eg, subtractive Ru) etching of dummy metal line 276 . Figure 2H Dummy metal line 276a is shown having been removed from between metal lines 234a, 234c. Fig.2I Dummy metal lines 276c, 276d are shown having been removed from between metal lines 234b, 234e.

[0041] like Figure 2J-2L and Figure 4 As shown, after removing the dummy metal line 276, the signal line region 132 ( Figure 1B ) and forming (block 418 ) a top through hole 138 in at least one of the plurality of through holes. Figure 2K is a diagram showing the structure of the circuit along line AA' ( Figure 2C ) a cross-sectional view of the operations taking place. Figure 2J and Figure 2L 276c and 276d after the dummy metal lines 276c and 276d are removed. Figure 2C ) a cross-sectional view of the operations that take place. Figure 2J As shown, the blocking pattern 282 is formed on the uppermost surface of the through hole positions 238a, 238b of the metal lines 234b, 234e. The blocking pattern 282 may be an insulating material having an etching selectivity with respect to the metal line 234 and with respect to the adhesion layer 252. Figure 2J-2LAs shown, the top vias 138a, 138b may be formed by subtractive top via patterning, which may include recessing (e.g., performing subtractive metal etching) the top portion of the metal line 234 that does not vertically overlap the barrier pattern 282. The recessed metal line 234 includes the metal signal line 134. For example, after removing the dummy metal line 276, the signal line 134c may be formed by recessing the top portion of the metal line 234c, and the signal line 134d may be formed by recessing the top portion of the metal line 234d.

[0042] The vias 138a, 138b are top portions of the metal lines 234b, 234e (i.e., via locations 238a, 238b) that are blocked and recessed by the blocking pattern 282. In contrast, the top portion (e.g., the uppermost surface) of the metal line 234 exposed by the blocking pattern 282 is recessed. The via 138a is spaced apart from the via 138b in the y direction. In addition, the signal line 134c is located in the signal line region 132c ( Figure 1B ), the signal line region 132c includes an opening 136c ( Figure 1B ), the opening 136c is located between the through holes 138a and 138b in the Y direction. In addition, the signal line 134d is located in the signal line area 132d ( Figure 1B ), the signal line area 132d ( Figure 1B ) includes opening 136d ( Figure 1B ), the opening 136d is located between the through holes 138a and 138b in the direction Y. The opening 136 existing after the signal line 134 and the through hole 138 are formed may be separated from the opening 236 ( Figure 2A ) are the same (i.e., can be in the same location and have the same size).

[0043] After (i) performing metal patterning, (ii) removing dummy metal line 276, and (iii) forming via 138, signal line 134 may have a pitch 140 ( Figure 1B ). The spacing 140 can be constant because no signal line 134 is wider than any other signal line 134 in the direction Y. In contrast, if the non-full track standard cell 260 ( Figure 2A ) performs metal patterning, some of the signal lines 134 may be wider than other signal lines.

[0044] For example, to address the large spacing between the metal lines 234 of the non-full track standard cell 260 (e.g., due to the opening 236 in the metal line 234), optical proximity correction (OPC) may be used, and the width of the metal line in the direction Y in the metal line 234 adjacent to the opening 236 in the direction Y may be reduced (or reduced / prevented from increasing). As an example, when the non-full track standard cell 260 is metal patterned using the LELE process, OPC (e.g., catastrophic OPC) may be used to increase the patterning margin at the wide spacing area. Without OPC, the metal may expand / bulge in the wide spacing area. Similarly, when the metal patterning of the non-full track standard cell 260 is performed using the SAUP (e.g., SA-LELE) process, the width of the metal line 234 (e.g., a mandrel-free metal line) adjacent to the wide spacing (e.g., a wide gap between the metal lines 234) may be enlarged relative to the width of the metal line 234 (e.g., another mandrel-free metal line) adjacent to the narrow spacing. However, performing metal patterning based on the design of full-track standard cells 262 (which have no openings 236 and thus no wide spacing areas between metal lines 234 ) may avoid metal expansion regardless of whether a LELE process or a SAUP process is used for metal patterning.

[0045] like Figure 2M , Figure 2N and Figure 4 As shown, it can be Figure 2K , Figure 2L An insulating layer 156 is formed (block 420 ) over the structure as shown. Figure 2M is a diagram showing the top through hole 138 after forming the line AA' ( Figure 2C ) a cross-sectional view of the operations taking place. Figure 2N is a diagram showing the area along line BB′ ( Figure 2C ) a cross-sectional view of the operations that take place. Figure 2M and Figure 2N As shown, insulating layer 156 may be formed on the sidewalls of signal line 134, the sidewalls of via 138, and the uppermost surface of signal line 134. For example, insulating layer 156 may be formed to fill the spaces between the sidewalls of signal line 134 and the sidewalls of via 138.

[0046] In some embodiments, the insulating layer 156 may be formed by filling the signal line 134 and the via 138 with a low-k material. As used herein, the term "low-k" refers to a material having a dielectric constant less than that of silicon dioxide. The low-k material may include, for example, fluorine-doped silicon dioxide, organic silicate glass, carbon-doped oxide, porous silicon dioxide, porous organic silicate glass, spin-on organic polymer dielectrics, or spin-on silicon-based polymer dielectrics. In addition, the insulating layer 156 may include a nitride layer.

[0047] Before forming insulating layer 156, metal adhesion layer 154 may be conformally formed on signal line 134 and via 138. For example, adhesion layer 154 may be formed on the sidewalls of via 138 and the sidewalls and uppermost surface of signal line 134. In some embodiments, adhesion layer 154 may include nitride (e.g., metal nitride) and may be formed by conformal nitride deposition. Then, insulating layer 156 may be formed on adhesion layer 154.

[0048] Before forming adhesion layer 154 and insulating layer 156 , adhesion layer 252 may be patterned / etched to form metal adhesion layer 152 including segments spaced apart from each other in direction Y. Adhesion layer 152 may contact the lowermost surface of signal line 134 and the uppermost surface of insulating layer 150 .

[0049] After forming the adhesion layer 154 and the insulating layer 156, a Figure 1B-Figure 1D In order to simplify the description, the non-full track standard unit 160 is shown in FIG. Figure 1B Adhesion layer 154 and insulating layer 156 are omitted in the view of FIG.

[0050] Figure 3A and Figure 3B is a diagram showing removal of dummy metal line 276 ( Figure 2D and Figure 2E ). In some embodiments, the Figure 3A and Figure 3B Instead of the operation shown in Figure 2F and Figure 2G Therefore, Figure 3A and Figure 3B The operation shown in is one example of how dummy metal line 276 may be removed, and Figure 2F and Figure 2G The operation shown in is another example of how dummy metal line 276 may be removed.

[0051] Figure 3A It is along Figure 2C The cross section of the line A-A', and Figure 3B It is along Figure 2C The cross section of the line B-B'. Figure 3A and Figure 3B As shown, the insulating material 390 may be formed on Figure 2D and Figure 2E392 is formed on the sidewalls and uppermost surfaces of the metal structures (e.g., metal line 234 and dummy metal line 276) shown. The uppermost surface of dummy metal line 276 can then be exposed by forming an opening in insulating material 390 (e.g., by etching a trench). Next, when insulating material 390 is on the uppermost surface and sidewalls of metal line 234, dummy metal line 276 can be removed through opening 392 (e.g., by subtractive metal etching), and insulating material 390 can then be removed, thereby producing Figure 2H and Fig.2I The structure shown in .

[0052] Figure 3C and Figure 3D According to some embodiments of the present invention, Figure 3A and Figure 3B The operation shown in FIG. 1 is a plan view of a signal line region 132 c from which a dummy metal line 276 is removed. Figure 3B and Figure 3C as well as Figure 2C , insulating material 390 may be formed on metal line 234c and on dummy metal line 276c. Then, while insulating material 390 remains on metal line 234c, opening 392 is formed in insulating material 390 to expose the uppermost surface of dummy metal line 276c.

[0053] like Figure 3C As shown, the opening 392 may be wider than the signal line region 132c in the direction Y. In addition, the end of the opening 392 may have a curved shape 394 that borders the metal line 234c. For example, the curved shape 394 may be convex. After the uppermost surface of the dummy metal line 276c is exposed through the opening 392, the dummy metal line 276c is removed through the opening 392 (for example, by subtractive metal etching). For simplicity of description, the dummy metal line 276c is not Figure 3C , and insulating material 390 is not shown on metal line 234c.

[0054] like Figure 3D As shown, the dummy metal line 276c is removed through the opening 392 to form an opening 236c in the signal line region 132c. The end of the opening 236c may also have a curved shape that is the same as the curved shape 394 of the opening 392. Before removing the insulating material 390, the opening 392 vertically overlaps with the opening 236c. In addition, the end of the opening 392 may vertically overlap with the adjacent end of the metal line 234c, and the removal of the dummy metal line 276c through the opening 392 may thus form a curved (e.g., concave) surface 396 in the end of the metal line 234c, wherein the shape of the curved surface 396 is defined by the curved shape 394 of the opening 392. Therefore, using Figure 3A and Figure 3BThe removal of dummy metal line 276 by the operation shown in FIG. 2 may result in the bent end of metal line 234 bordering opening 236, while using Figure 2F and Figure 2G The removal of dummy metal line 276 by the operation shown in FIG. 2 may result in a planar end of metal line 234 bordering opening 236 .

[0055] According to the embodiments herein, the IC device 100 ( Figure 1A ) can provide several advantages. These advantages include combining the BEOL region 130 ( Figure 1A ) benefits from two different standard cell designs. The first design is a non-full track standard cell 260 ( Figure 2A ), and the second design is a full track standard cell 262 formed by adding a dummy metal line 276 to a non-full track standard cell 260 ( Figure 2B By performing metal patterning using full track standard cells 262 (rather than non-full track standard cells 260), metal patterning margin may be increased. However, full track standard cells 262 may reduce performance of IC device 100 by increasing capacitance (due to the increased amount of metal in full track standard cells 262).

[0056] Embodiments herein can integrate the two designs by converting the non-full track standard cell 260 into a full track standard cell 262 before performing metal patterning, and then converting the full track standard cell 262 back into a non-full track standard cell 260 by removing the dummy metal line 276 after performing metal patterning. Removing the dummy metal line 276 can improve the performance of the IC device 100 by reducing capacitance. This can help increase the metal signal line 134 ( Figure 1B ) manufacturability.

[0057] Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the teachings of the present disclosure, and therefore the present disclosure should not be construed as being limited to the example embodiments set forth herein. On the contrary, these example embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present invention will be conveyed to those skilled in the art. In the accompanying drawings, the size and relative size of layers and regions may be exaggerated for clarity. The same reference numerals always refer to the same elements.

[0058] Example embodiments are described herein with reference to cross-sectional illustrations that are schematic diagrams of idealized embodiments and intermediate structures of example embodiments. Thus, variations from the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, the embodiments herein should not be construed as limited to the particular shapes shown herein, but may include deviations in shapes that result, for example, from manufacturing.

[0059] It should also be noted that in some alternative implementations, the function / action indicated in the flowchart frame of this paper may not occur in the order indicated in the flowchart. For example, two frames shown in succession can actually be performed substantially simultaneously, or frames can sometimes be performed in reverse order, depending on the function / action involved. In addition, the function of a given frame of a flowchart and / or block diagram can be divided into multiple frames and / or the function of two or more frames of a flowchart and / or block diagram can be integrated at least in part. Finally, without departing from the scope of the present invention, other frames can be added / inserted between the frames shown, and / or frames / operations can be omitted.

[0060] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0061] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprises", "comprising", "includes" and / or "including" specify the presence of the features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups thereof.

[0062] It should be understood that when an element is referred to as being "coupled," "connected," or "responsive to" another element or "on" another element, it may be directly coupled, connected, or responsive to another element or on another element, or there may be intermediate elements. In contrast, when an element is referred to as being "directly coupled," "directly connected," or "directly responsive to" another element or "directly on" another element, there are no intermediate elements. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. In addition, the symbol " / " (for example, when used in the term "source / drain") will be understood to be equivalent to the term "and / or."

[0063] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teaching of the present embodiment, the first element may be referred to as the second element.

[0064] For ease of description, spatially relative terms, such as "below," "below," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another or more elements or features as shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is turned over, elements described as being "below" or "beneath" other elements or features will be oriented as being "above" the other elements or features. Thus, the term "below" can cover both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0065] Many different embodiments have been disclosed herein in conjunction with the above description and accompanying drawings. It will be understood that literally describing and illustrating every combination and subcombination of these embodiments would be overly repetitive and obfuscating. Therefore, this specification (including the accompanying drawings) should be interpreted as constituting a complete written description of all combinations and subcombinations of the embodiments described herein, as well as the manner and process of making and using them, and should support claims directed to any such combination or subcombination.

[0066] The subject matter disclosed above is considered to be illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the scope of the invention. Therefore, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims

1. A method for forming a back-end-of-line (BEOL) region of an integrated circuit device, the method comprising: converting the non-full-track standard cell into a full-track standard cell by adding a dummy metal line to the non-full-track standard cell designed for the BEOL region; performing metal patterning based on the full track standard cell; removing the dummy metal line after performing the metal patterning; and A top via is formed after removing the dummy metal line.

2. The method according to claim 1, wherein: Removing the dummy metal line includes performing a subtractive metal etch of the dummy metal line.

3. The method according to claim 2, in, Removing the dummy metal line further comprises forming a blocking pattern, the blocking pattern vertically overlapping with the non-dummy metal line of the full track standard cell and not vertically overlapping with the dummy metal line, wherein the blocking pattern does not exist on the sidewall of the dummy metal line, and Wherein, the subtractive metal etching of the dummy metal line is performed when the barrier pattern vertically overlaps the non-dummy metal line.

4. The method according to claim 2, in, Removing the dummy metal line further includes: forming an insulating material on the uppermost surface and sidewalls of the dummy metal line and on the uppermost surface and sidewalls of the non-dummy metal line of the full-track standard cell; and etching the insulating material to form an opening in the insulating material exposing the uppermost surface of the dummy metal line, and Wherein, the subtractive metal etching of the dummy metal line is performed through the opening when the insulating material is on the uppermost surface and the sidewalls of the non-dummy metal line.

5. The method according to claim 4, wherein: The subtractive metal etch forms a concave end portion of one of the non-dummy metal lines.

6. The method according to claim 2, wherein: The subtractive metal etching includes a subtractive ruthenium (Ru) etching of the dummy metal line.

7. The method according to claim 1, wherein: Forming the top via includes performing subtractive top via patterning after removing the dummy metal line.

8. The method according to claim 7, wherein: Performing the subtractive top via patterning includes: After removing the dummy metal line, forming a first metal signal line and a second metal signal line by respectively recessing a top portion of the first non-dummy metal line and a top portion of the second non-dummy metal line; and A first top via and a second top via are formed by the recesses that block top portions of the third and fourth non-dummy metal lines, respectively.

9. The method according to claim 8, in, The first top through hole is spaced apart from the second top through hole in a lateral direction, and The first metal signal line is in a signal line region including an opening between the first top via and the second top via in the lateral direction.

10. The method according to claim 1, wherein: Removing the dummy metal line converts the full-track standard cell back to the non-full-track standard cell.

11. The method according to claim 10, wherein: After the dummy metal lines are removed, the signal lines of the non-full-track standard cell have a constant pitch.

12. The method according to claim 1, further comprising designing the non-full track standard cell before adding the dummy metal line; in, Adding the dummy metal line includes designing metal in all openings in the signal line region of the non-full track standard cell, wherein designing the non-full track standard cell and adding the dummy metal line are performed digitally, and Wherein, performing the metal patterning based on the full track standard cell includes physically forming the full track standard cell.

13. The method according to claim 1, wherein: Performing the metal patterning based on the full-track standard cell includes performing self-aligned universal patterning (SAUP) to form the full-track standard cell.

14. The method according to claim 1, wherein: Performing the metal patterning based on the full-track standard cell includes performing lithography-etch-lithography-etch (LELE) patterning to form the full-track standard cell.

15. The method according to claim 1, wherein: Performing the metal patterning based on the full track standard cell includes performing ruthenium Ru patterning to form the full track standard cell.

16. A method for forming a back-end-of-line (BEOL) region of an integrated circuit device, the method comprising: designing a non-dummy metal line in a corresponding signal line region of the BEOL region; After designing the non-dummy metal lines, designing dummy metal lines in openings in at least some of the signal line regions; After designing the dummy metal line, performing metal patterning on the signal line region; removing the dummy metal line after performing the metal patterning; as well as After removing the dummy metal line, a top via is formed in at least one of the signal line regions.

17. The method according to claim 16, in, Removing the dummy metal line includes performing a subtractive Ruthenium (Ru) etch on the dummy metal line, and The performing of the metal patterning on the signal line region includes performing self-aligned universal patterning (SAUP) on the signal line region.

18. The method according to claim 16, in, The signal line region is part of a standard cell of the BEOL region, and Wherein, after the dummy metal line is removed, the standard cell is a non-full-track standard cell.

19. A method for forming a back-end-of-line (BEOL) region of an integrated circuit device, the method comprising: Providing a non-full track standard cell design for the BEOL area; converting the non-full-track standard cell design into a full-track standard cell design by adding dummy metal lines to the non-full-track standard cell design, wherein adding the dummy metal lines includes designing metal in all openings in a signal line region of the non-full-track standard cell design; removing the dummy metal line by performing a subtractive metal etch on the dummy metal line; and A top via is formed after removing the dummy metal line.

20. The method according to claim 19, further comprising: Before removing the dummy metal line, metal patterning is performed based on the full-track standard cell design, wherein performing the metal patterning includes forming the dummy metal line.

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