Electronic device and operating method thereof
By introducing a delay circuit into the electronic device, the power-up signal is delayed by different times, the problem of unstable supply voltage during startup is solved, the power supply voltage is stabilized, and the normal operation of the device is ensured.
Patent Information
- Application Number
- CN202410364154.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-27
- Filing Date
- 2024-03-28
- Publication Date
- 2025-05-27
AI Technical Summary
When the electronic device is started, the supply voltage is unstable, resulting in incorrect power-up sequence, affecting the normal operation of the device.
An electronic device is designed, including a power-up circuit, a delay circuit and a plurality of power supply circuits. The power-up circuit controls the power-up signal according to the power-up voltage. The delay circuit provides multiple enable signals by delaying the power-up signal for different times. The power supply circuit is enabled by these enable signals respectively.
The delay circuit delays the power-up signal for different times, avoiding all power supply circuits being enabled at the same time, thus maintaining the stability of the power supply voltage and ensuring the normal start-up and operation of the electronic device.
Smart Images
Figure CN120049866A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure generally relates to a device and a method, and more particularly to an electronic device and an operating method thereof. Background Art
[0002] When starting an electronic device, keeping the supply voltage stable can ensure the correct power-up sequence and thus maintain the normal operation of the electronic device. Summary of the Invention
[0003] Therefore, the present disclosure relates to an electronic device and an operating method that can keep the supply voltage stable during startup.
[0004] The electronic device of the present disclosure includes a power-on circuit, a delay circuit, and a plurality of power supply circuits. The power-on circuit is configured to control a power-on signal according to a power supply voltage. The delay circuit is configured to provide a plurality of enable signals by delaying the power-on signal by different delay times. The plurality of power supply circuits are configured to be enabled respectively through the plurality of enable signals.
[0005] The operating method of the present disclosure includes: controlling a power-on signal by a power-on circuit according to a power supply voltage; providing a plurality of enable signals by a delay circuit by delaying the power-on signal by different delay times; and enabling the plurality of power supply circuits respectively through the plurality of enable signals.
[0006] To make the above content easier to understand, several embodiments accompanied by drawings will be elaborated in detail below. Brief Description of the Drawings
[0007] This document includes drawings to provide further understanding of the present disclosure, and the drawings are incorporated into this specification and form a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and are used together with the description to explain the principles of the present disclosure.
[0008] Figure 1 An electronic device according to some embodiments of the present disclosure is shown;
[0009] Figure 2A A schematic diagram of a delay circuit according to some embodiments of the present disclosure is shown;
[0010] Figure 2B A schematic diagram of a delay circuit according to some embodiments of the present disclosure is shown;
[0011] Figures 3A to 3C Various configurations of a unit delay cell according to some embodiments of the present disclosure are shown;
[0012] Figure 4Shows the current curve of a power supply circuit drawn from a node supplying a power supply voltage VDD according to some embodiments of the present disclosure;
[0013] Figure 5 Shows a flowchart of an operation method according to some embodiments of the present disclosure.
[0014] Explanation of reference numerals in the drawings
[0015] 1: Electronic device
[0016] 11: Power-on circuit
[0017] 12, 12a, 12b: Delay circuit
[0018] 121, 122, 123, 124: Delay chain
[0019] 131, 132, 133: Power supply circuit
[0020] C1: Capacitor
[0021] MN1, MN2, MP1, MP2: Transistor
[0022] R1: Resistor
[0023] S51, S52, S53: Steps
[0024] UD1, UD2, UD3: Unit delay cell
[0025] VDC1, VDC2, VDC3: Power supply voltage
[0026] VDD: Power supply voltage
[0027] VEn1, Ven2, VEn3: Enable signal
[0028] VP: Power-on signal Detailed description of the embodiments
[0029] Figure 1An electronic device 1 according to some embodiments of the present disclosure is shown. The electronic device 1 includes a power-on circuit 11, a delay circuit 12, and power supply circuits 131 to 133. Briefly, the power supply circuits 131 to 133 are configured to convert a power voltage VDD into a plurality of power supply voltages. When starting the electronic device 1, the power voltage VDD gradually rises from the ground voltage. As the power voltage VDD rises, the power-on circuit 11 keeps monitoring the power voltage VDD, so that the power-on circuit 11 can notify the power supply circuits 131 to 133 through a power-on signal VP that the power voltage VDD is ready and reaches a predetermined voltage level. The power supply circuits 131 to 133 can be enabled accordingly to convert the power voltage VDD into corresponding power supply voltages. However, in order to keep the power voltage VDD stable (especially in the startup phase of the electronic device 1) and to avoid the power supply circuits 131 to 133 drawing a large current simultaneously, a delay circuit 12 is added between the power-on circuit 11 and the power supply circuits 131 to 133. Specifically, the delay circuit 12 is configured to delay the power-on signal VP by different delay times, so that the delay circuit 12 can generate enable signals VEn1 to VEn3 to enable the power supply circuits 131 to 133 at different time points, thereby avoiding the power supply circuits 131 to 133 being turned on simultaneously.
[0030] Specifically, the power-on circuit 11 is configured to perform a power-on sequence and compare the power voltage VDD with a predetermined voltage level. In some embodiments, the predetermined voltage level can be a voltage level selected from the range between 0.5V and 0.9V. When the power-on circuit 11 senses that the power voltage VDD rises to be greater than the predetermined voltage, which means that the power voltage VDD can be supplied to certain specific circuits in the electronic device 1 to perform the power-on sequence, the power-on circuit 11 can accordingly pull up the power-on signal VP to an enable voltage level to notify these circuits.
[0031] The delay circuit 12 is coupled to the power-on circuit 11 and is configured to generate enable signals VEn1 to VEn3 by delaying the power-on signal VP by different delay times. By applying different delay times to the power-on signal VP to generate the enable signals VEn1 to VEn3, the rising edges of the enable signals VEn1 to VEn3 can be properly separated. In some embodiments, the delay times inserted by the delay circuit 12 can be in the nanosecond scale (e.g., 20ns, 50ns, 100ns) according to the system requirements and design concepts of the electronic device 1, or in the microsecond scale (e.g., 15μs, 20μs), or other appropriate time lengths.
[0032] Power supply circuits 131 to 133 are configured to be enabled by enable signals VEn1 to VEn3 respectively to convert a power supply voltage VDD into power supply voltages VDC1 to VDC3. In some embodiments, power supply circuits 131 to 133 are coupled to the same node supplying the power supply voltage VDD and are respectively configured to convert the power supply voltage VDD into power supply voltages at appropriate voltage levels such that corresponding circuit components inside the electronic device 1 can be supplied by these converted power supply voltages for operation. Specifically, since the enable signals VEn1 to VEn3 are delayed by different delay times, the rising edges of the enable signals VEn1 to VEn3 are separated, and thus the power supply circuits 131 to 133 are correspondingly enabled at different time points according to the rising edges of the enable signals VEn1 to VEn3. In this way, the power supply voltage VDD can be effectively stabilized by sequentially and individually turning on the power supply circuits 131 to 133 to avoid all the power supply circuits 131 to 133 drawing current together from the node of the power supply voltage VDD. In some embodiments, each of the power supply circuits 131 to 133 can be a low-dropout (LDO) circuit or a direct-current (DC)-DC converter, and the DC-DC converter can be used to convert one voltage level into another voltage level, such as raising or lowering the voltage level to another appropriate voltage level and stabilizing the voltage.
[0033] Figure 2A Schematic diagram showing a delay circuit 12a according to some embodiments of the present disclosure. Figure 2A The delay circuit 12a in can be applied to Figure 1 the electronic device 1 in to replace the delay circuit 12. The delay circuit 12a is configured to delay a power-on signal VP by different delay times and generate enable signals VEn1 to VEn3. Specifically, the delay circuit 12a includes delay chains 121, 122. In addition, the delay circuit 12a couples the power-on circuit 11 to the power supply circuit 131 through metal wiring and couples the power-on circuit 11 to the power supply circuits 132, 133 through the delay chains 121, 122. The metal wiring between the power-on circuit 11 and the power supply circuit 131 provides little or negligible delay time compared to the delay times of the delay chains 121, 122, and the delay chain 121 provides a shorter delay time than the delay chain 122. In this way, the delay circuit 12a can appropriately delay the power-on signal VP by different delay times and generate the enable signals VEn1 to VEn3.
[0034] In addition, each of the delay chains 121 and 122 includes at least one unit delay cell serially coupled between the power-on circuit 11 and the corresponding power supply circuits 132 and 133 of the respective delay chains 121 and 122. Each unit delay cell is configured to delay an input signal by a predetermined delay time and output the delayed signal. The number of unit delay cells in each delay chain can be determined according to the structure of the deployed unit delay cells and the length of the delay time required by the electronic device 1.
[0035] Figure 2B Schematic diagram showing a delay circuit 12b according to some embodiments of the present disclosure. Figure 2B The delay circuit 12b in Figure 1 can be applied to the electronic device 1 in Figure 2B to replace the delay circuit 12. Figure 2A The delay circuit 12b in Figure 2A is functionally similar to the delay circuit 12a in Figure 2B The delay circuit 12a in can delay the power-on signal VP by different delay times to generate enable signals VEn1 to VEn3. More specifically, the delay circuit 12b includes delay chains 123 and 124 serially coupled after the power-on circuit 11. In some aspects, the delay circuit 12b can be regarded as a huge delay chain receiving the power-on signal VP, and the enable signals VEn1 to VEn3 can be output by the unit delay cells at different levels in the delay chain formed by the delay chains 123 and 124. In the exemplary embodiment of
[0036] Figures 3A to 3C shows various configurations of unit delay cells UD1 to UD3 according to some embodiments of the present disclosure. In Figure 3AAmong them, the unit delay cell UD1 may include a resistor R1 and a capacitor C1. The resistor R1 is coupled between the input terminal and the output terminal of the unit delay cell UD1, and the capacitor C1 is coupled between the output terminal of the unit delay cell UD1 and the ground voltage, such that the delay time provided by the unit delay cell UD1 can be determined based on the resistance of the resistor R1 and the capacitance of the capacitor C1.
[0037] More specifically, when the unit delay cell UD1 is adopted in the delay chains 121 and 122 in Figure 2A , since the unit delay cell UD1 can provide different delay times by modifying the resistance of the resistor R1 and / or the capacitance of the capacitor C1, each delay chain may include only one unit delay cell UD1. However, the delay chains 121 and 122 may also internally have more than one unit delay cell UD1, which enables each unit delay cell UD1 to have the same structure and generate the same length of delay time, thereby reducing the design difficulty of the delay circuit 12a. Similarly, when the unit delay cell UD1 is adopted in the delay chains 123 and 124 in Figure 2B , the same concept can be applied, such that the delay chains 123 and 124 may include the same number or different numbers of unit delay cells UD1 to generate the required delay time.
[0038] In Figure 3B , the unit delay cell UD2 may include transistors MP1, MP2, MN1, and MN2, thereby forming two inverters connected in series between the input terminal and the output terminal of the unit delay cell UD2. The delay time of the unit delay cell UD2 can be determined according to the transistor size. Therefore, when the unit delay cell UD2 is utilized in the delay chains 121 to 124, the delay chains 121 to 124 with only one unit delay cell UD2 internally can achieve different delay times. However, the delay chains 121 to 124 may also be provided with more than one unit delay cell UD1 having the same size and the same delay time, thereby reducing the design complexity of the delay circuit 12b.
[0039] In Figure 3C , the unit delay cell UD3 may be a D flip-flop (DFF). The unit delay cell UD3 is configured to provide the input data received from the input terminal to the output terminal when triggered by a clock signal. Therefore, since the delay time generated by each unit delay cell UD3 is equal, when the unit delay cell UD3 is applied to the delay chains 121 to 124, different numbers of unit delay cells UD3 connected in series can achieve different delay times.
[0040] Figure 4Illustrate the current curves L41 and L42 of the power supply circuits 131 to 133 drawn from the node supplying the power supply voltage VDD according to some embodiments of the present disclosure. Specifically, the curve L41 corresponds to the current of the power supply circuits 131 to 133 that are simultaneously enabled, and the curve L42 corresponds to the current spikes of the power supply circuits 131 to 133 that are individually enabled. As can be seen from Figure 4 it, as the power supply voltage rises and reaches a predetermined voltage level (e.g., 0.55V), the power-on circuit 11 switches the power-on signal VP to the enable voltage level. In an exemplary embodiment where the power-on signal VP is directly provided to the power supply circuits 131 to 133 without the delay circuit 12, all the power supply circuits 131 to 133 are simultaneously enabled, resulting in a large current appearing on the curve L41. In contrast, when a delay circuit 12 is provided between the power-on circuit 11 and the power supply circuits 131 to 133 to delay the power-on signal VP by different delay times, the startup of the power supply circuits 131 to 133 can be effectively separated to avoid drawing a large current from the node supplying the power supply voltage VP, thereby generating a lower current spike on the curve L42. Therefore, the electronic device 1 can effectively maintain the stability of the power supply voltage VP by using the delay circuit 12 to delay the power-on signal VP by different delay times.
[0041] Figure 5 Illustrate a flowchart of an operating method according to some embodiments of the present disclosure. Figure 5 The operating method in can be used to operate Figure 1 the electronic device 1 in. Specifically, the operating method includes steps S51 to S53.
[0042] In step S51, the power-on circuit 11 controls the power-on signal VP according to the power supply voltage VDD. Specifically, the power-on circuit 11 is configured to implement a power-on sequence and compare the power supply voltage VDD with a predetermined voltage level. In some embodiments, the predetermined voltage level can be a voltage level selected from the range between 0.5V and 0.9V. When the power-on circuit 11 senses that the power supply voltage VDD rises to be greater than the predetermined voltage, which means that the power supply voltage VDD can be supplied to certain specific circuits in the electronic device 1 to implement the power-on sequence, the power-on circuit 11 can accordingly pull up the power-on signal VP to the enable voltage level to notify these circuits to start their startup.
[0043] In step S52, multiple enable signals are generated by delaying a power-on signal by different delay times. Specifically, a delay circuit 12 is coupled to a power-on circuit 11 and configured to generate enable signals VEn1 to VEn3 by delaying the power-on signal VP by different delay times. By applying different delay times to the power-on signal VP, the rising edges of the enable signals VEn1 to VEn3 can be properly separated. In some embodiments, the delay times inserted by the delay circuit 12 may be on the order of nanoseconds (e.g., 20 ns, 50 ns, 100 ns), or on the order of microseconds (e.g., 15 μs, 20 μs), or other suitable time lengths, depending on the system requirements and design concept of the electronic device 1.
[0044] In step S53, multiple power supply circuits 131 to 133 are enabled by the multiple enable signals VEn1 to VEn3, respectively. Specifically, the power supply circuits 131 to 133 are configured to convert the power supply voltage VDD into power supply voltages VDC1 to VDC3 by the enable signals VEn1 to VEn3, respectively. In some embodiments, the power supply circuits 131 to 133 are coupled to the same node that supplies the power supply voltage VDD and are respectively configured to convert the power supply voltage VDD into power supply voltages at appropriate voltage levels such that the corresponding circuit components inside the electronic device 1 can be supplied by these converted power supply voltages for operation. Specifically, since the enable signals VEn1 to VEn3 are delayed by different delay times, the rising edges of the enable signals VEn1 to VEn3 are separated, and thus the power supply circuits 131 to 133 are enabled at different time points according to the rising edges of the enable signals VEn1 to VEn3. In this way, the power supply voltage VDD can be effectively stabilized by sequentially and individually turning on the power supply circuits 131 to 133 to avoid all the power supply circuits 131 to 133 drawing current from the node that supplies the power supply voltage VDD simultaneously. In some embodiments, each of the power supply circuits 131 to 133 may be a low dropout (LDO) circuit or a DC-DC converter, and the DC-DC converter can be used to convert one voltage level into another voltage level, such as raising or lowering the voltage level to another appropriate voltage level and stabilizing the voltage.
[0045] In summary, the electronic device and the operation method can effectively separate the startup of each power supply circuit by setting a delay circuit to delay the power-on signal by different delay times. In this way, the startup of each power supply circuit can be separated to avoid drawing a large current from the node that supplies the power supply voltage, thereby stabilizing the power supply voltage.
[0046] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In summary, the present disclosure is intended to cover modifications and variations that fall within the scope of the above claims and their equivalents.
Claims
1. An electronic device comprising: a power-on circuit configured to control a power-on signal according to a power supply voltage; a delay circuit configured to provide a plurality of enable signals by delaying the power-on signal by different delay times; as well as A plurality of power supply circuits are configured to be enabled by the plurality of enable signals, respectively. 2 . The electronic device according to claim 1 , wherein the power-on circuit is configured to switch the power-on signal to an enable voltage level when the power-on circuit senses that the power supply voltage increases to be greater than a predetermined voltage level. 3 . The electronic device according to claim 2 , wherein the predetermined voltage level is selected from a range between 0.5V and 0.9V. 4 . The electronic device of claim 1 , wherein each of the plurality of power supply circuits is enabled by a corresponding enable signal of the plurality of enable signals to convert the power supply voltage into a power supply voltage. 5 . The electronic device according to claim 1 , wherein at least one of the plurality of power supply circuits is a low voltage dropout circuit or a DC-DC converter.
6. The electronic device according to claim 1, wherein the delay circuit comprises a plurality of delay chains, and each of the plurality of delay chains comprises at least one unit delay cell coupled in series between the power-up circuit and a corresponding power supply circuit among the plurality of power supply circuits. 7 . The electronic device according to claim 6 , wherein each of the at least one unit delay cell is a resistor-capacitor delay cell, a buffer, an inverter, or a flip-flop. 8 . The electronic device according to claim 7 , wherein each of the at least one unit delay cell is the buffer or the inverter, and sizes of the at least one unit delay cell are different. 9 . The electronic device according to claim 6 , wherein each of the at least one unit delay cell provides a same unit delay time, and the plurality of delay chains include different numbers of the unit delay cells.
10. The electronic device according to claim 1, wherein the delay circuit comprises a delay chain coupled to the power-on circuit, the delay chain comprises a plurality of unit delay cells coupled in series, and the plurality of enable signals are output by the plurality of unit delay cells at different stages in the delay chain.
11. An operating method of an electronic device, the electronic device comprising a power-on circuit, a delay circuit and a plurality of power supply circuits, the operating method comprising: The power-on circuit controls the power-on signal according to the power supply voltage; The delay circuit provides a plurality of enable signals by delaying the power-on signal by different delay times; as well as The plurality of power supply circuits are enabled respectively by the plurality of enable signals.
12. The operating method of claim 11, comprising switching, by the power-up circuit, the power-up signal to an enable voltage level when the power-up circuit senses that the power supply voltage rises above a predetermined voltage level.
13. The operating method according to claim 12, wherein the predetermined voltage level is selected from a voltage level between 0.5V and 0.9V. 14 . The operating method of claim 11 , comprising enabling each of the plurality of power supply circuits to convert the power supply voltage into a power supply voltage by a corresponding enable signal of the plurality of enable signals.