Parameter optimization method based on PCB processing abnormity identification

Abstract

The invention discloses a parameter optimization method based on PCB processing abnormity identification, and relates to the technical field of circuit boards, and the method comprises the steps: obtaining the etching parameters of a PCB; determining the line width of the PCB; forming a copper residue short circuit discrimination mechanism; constructing an optimization model of the etching parameters; judging whether the etching of the PCB is abnormal or not; when parameters are optimized, positions where etching is abnormal are divided into a first abnormal position and a second abnormal position; and forming a first parameter optimization scheme at the first abnormal position, and forming a second parameter optimization scheme at the second abnormal position. By determining the line width of the PCB, forming a short-circuit discrimination mechanism of copper residues, constructing an optimization model of etching parameters, forming a first parameter optimization scheme and a second parameter optimization scheme, etching abnormalities at different positions in the circuit board are identified, and the etching duration of the positions with abnormalities is adjusted.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit boards, and more particularly to a parameter optimization method for identifying processing anomalies in PCB circuit boards. Background Art

[0002] The processing of PCB circuit boards involves multiple processes, and etching is one of the more important processes. Etching is the chemical removal of copper from unprotected non-conductive parts to form specific circuit patterns. Its core purpose is to precisely produce circuit patterns according to design requirements. Etching is affected by concentration, temperature, and etching time. When the concentration and temperature are fixed, if the etching time is too long, the circuit will be over-etched, affecting conductivity; if the etching time is insufficient, there will be residual copper. The circuits on PCB circuit boards are very dense, and residual copper may cause short circuits. Summary of the Invention

[0003] To solve the above technical problems, a parameter optimization method for identifying processing anomalies in PCB circuit boards is provided, and this technical solution solves the problems raised in the above background art.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0005] A parameter optimization method for identifying processing anomalies in PCB circuit boards, comprising:

[0006] Obtain the etching parameters of the PCB circuit board, which are composed of the concentration of the etching solution, temperature, and etching time;

[0007] Based on the circuit layout of the PCB circuit board, determine the circuit width of the PCB circuit board;

[0008] Form a short-circuit discrimination mechanism for copper residue;

[0009] Based on historical data, construct an optimization model for etching parameters;

[0010] Monitor the etching process of the PCB circuit board to determine whether there are any anomalies in the etching of the PCB circuit board. If not, no treatment is required; if so, parameter optimization is performed;

[0011] During parameter optimization, obtain the real-time concentration, real-time temperature, and actual etching time of the etching solution, obtain the positions where etching anomalies exist in the PCB circuit board, and based on the types of anomalies, divide the positions where etching anomalies exist into a first abnormal position and a second abnormal position;

[0012] Based on the optimization model of etching parameters, form a first parameter optimization plan for the first abnormal position and a second parameter optimization plan for the second abnormal position;

[0013] Adjust according to the parameters in the first parameter optimization plan and the second parameter optimization plan.

[0014] Preferably, for the circuit layout based on the PCB circuit board, determining the circuit width of the PCB circuit board includes the following steps:

[0015] Obtain the circuit layout of the circuits in the PCB circuit board, obtain the current input terminal and the current output terminal in the circuit layout, and obtain all branches in the circuit layout, where the branch is the circuit connecting the current input terminal and the current output terminal in the circuit layout;

[0016] Obtain the longest branch in the circuit layout as the characteristic branch, and obtain the shortest branch in the circuit layout as the non-characteristic branch;

[0017] Use the length of the characteristic branch and the length of the non-characteristic branch as endpoints to form a characteristic interval;

[0018] Evenly divide the characteristic interval into at least one local interval, and obtain the proportion of the branches whose lengths belong to the local interval as the characteristic proportion;

[0019] Based on historical data, obtain the lower limit value of the conductivity of the PCB circuit board;

[0020] Establish a conductivity identification function;

[0021] Input the lower limit value of conductivity and the midpoint of the local interval into the conductivity identification function to obtain a characteristic value;

[0022] Multiply the characteristic value by the corresponding characteristic proportion and then accumulate to obtain the circuit width of the PCB circuit board.

[0023] Preferably, establishing the conductivity identification function includes the following steps:

[0024] Based on historical data, obtain the conductivity value range of the PCB circuit board, and evenly divide the conductivity value range to obtain at least one conductivity point;

[0025] Obtain the value range of the branch, and evenly divide the value range of the branch to obtain at least one length point;

[0026] Randomly combine at least one conductivity point and at least one length point to obtain at least one test group;

[0027] Obtain the circuit whose conductivity and length are respectively equal to the conductivity point and the length point values in the test group as the target circuit, where the target circuit is a line segment;

[0028] Measure the width of the target line, pair and fit the test group with the width of the target line to obtain a conductive performance identification function, where the values of the conductive points and length points in the test group are independent variables and the width of the target line is the dependent variable.

[0029] Preferably, the short - circuit discrimination mechanism for forming copper residues includes the following steps:

[0030] Obtain at least one abnormal circuit board with a short - circuit, where the cause of the short - circuit of the abnormal circuit board is caused by excessive copper residues;

[0031] Perform image recognition on the abnormal circuit board to obtain at least one feature region, where the feature region is an area covered with copper and has no intersection with the circuits in the abnormal circuit board;

[0032] Obtain the smallest loop in the abnormal circuit board where the circuit contains the feature region as the feature loop;

[0033] Obtain the minimum value of the distance from the feature loop to the feature region it contains as the feature distance;

[0034] Take the minimum value of at least one feature distance in a single abnormal circuit board as the target distance;

[0035] Take the interval formed by the maximum and minimum values of at least one target distance as endpoints as the short - circuit identification interval;

[0036] When the minimum distance from the remaining copper to the circuits in the PCB circuit board belongs to the short - circuit identification interval, the remaining copper will cause a short - circuit, otherwise, it will not cause a short - circuit.

[0037] Preferably, the construction of the optimization model for etching parameters based on historical data includes the following steps:

[0038] Obtain the concentration value range of the etching solution, equally divide the concentration value range to obtain at least one concentration point;

[0039] Obtain the temperature value range of the etching solution, equally divide the temperature value range to obtain at least one temperature point;

[0040] Randomly combine at least one concentration point and at least one temperature point to obtain at least one verification group;

[0041] Obtain the time consumed for the etching to reach the line width of the PCB circuit board under the conditions of the verification group as the target time;

[0042] Pair and fit the verification group with the target time to obtain an etching fitting function, where the values of the concentration point and temperature point in the verification group are independent variables and the target time is the dependent variable.

[0043] Preferably, the determination of whether there is an abnormality in the etching of the PCB circuit board includes the following steps:

[0044] Identify the copper residue positions in the PCB circuit board to obtain at least one actual residue area, where the actual residue area is the area covered by copper that has no intersection with the circuits in the PCB circuit board;

[0045] Obtain the minimum value from the actual residue area to the circuits in the PCB circuit board as the distance to be identified;

[0046] Use the short - circuit discrimination mechanism of copper residue to identify the distance to be identified, and obtain the actual residue areas with abnormalities;

[0047] Evenly divide the circuits in the PCB circuit board into at least one sampling block, identify the width at the mid - point of the sampling block, and obtain the sampling width;

[0048] When the difference between the sampling width and the circuit width of the PCB circuit board exceeds a preset value, the sampling block corresponding to the sampling width has an abnormality.

[0049] Preferably, the classification of the positions with etching abnormalities into the first abnormal positions and the second abnormal positions based on the types of abnormalities includes the following steps:

[0050] Take the actual residue areas with abnormalities as the first abnormal positions, and take the sampling blocks with abnormalities as the second abnormal positions.

[0051] Preferably, the formation of the first parameter optimization scheme at the first abnormal positions includes the following steps:

[0052] Take at least one identification point on the contour of the first abnormal position, fit the coordinates of at least one identification point to obtain the contour curve function;

[0053] Use a horizontal line to divide the contour of the first abnormal position. The contour curve function above the horizontal line is the upper contour curve function, and the contour curve function below the horizontal line is the lower contour curve function;

[0054] Use the length formula to calculate the length of the contour of the first abnormal position as the characteristic length;

[0055] Evenly take at least one scaling point in the interval (0, 1), and shrink the first abnormal position according to the value of the scaling point to obtain a reduced area, where the scaling point is the center of the first abnormal position;

[0056] Obtain the minimum distance from the reduced area to the circuits of the PCB circuit board as the distance to be monitored;

[0057] Use the short - circuit discrimination mechanism of copper residue to identify the distance to be monitored, and take the distance to be monitored that will not cause a short - circuit as the calibration distance;

[0058] Use the value of the scaling point adopted for the minimum calibration distance as the characteristic ratio;

[0059] Integrate the area enclosed by the contour curve function to obtain the characteristic area;

[0060] Use the width formula to calculate the etching compensation width at the first abnormal position;

[0061] Input the real-time concentration and real-time temperature into the etching fitting function to obtain the second etching time;

[0062] Multiply the etching compensation width divided by the line width of the PCB by the second etching time to obtain the etching time compensation value;

[0063] Overlay the actual etching time with the etching time compensation value to obtain the first etching time. Use the real-time concentration, real-time temperature, and the first etching time as the first parameter optimization scheme;

[0064] The length formula is as follows:

[0065]

[0066] Wherein, L is the characteristic length, a and b are respectively the abscissas of the intersection points of the horizontal line and the contour of the first abnormal position, g(x) is the derivative of the upper contour curve function, f(x) is the derivative of the lower contour curve function, and x is the abscissa of the point on the contour of the first abnormal position;

[0067] The width formula is as follows:

[0068]

[0069] Wherein, B is the etching compensation width, k is the characteristic ratio, and S is the characteristic area.

[0070] Preferably, the formation of the second parameter optimization scheme at the second abnormal position includes the following steps:

[0071] Use the real-time concentration, real-time temperature, and the second etching time as the second parameter optimization scheme.

[0072] Preferably, the regulation according to the parameters in the first parameter optimization scheme and the second parameter optimization scheme includes the following steps:

[0073] Etch the part of the PCB other than the first abnormal position and the second abnormal position according to the real-time concentration and real-time temperature, and the etching time is the actual etching time;

[0074] Etch the first abnormal position according to the real-time concentration and real-time temperature, and the etching time is the first etching time;

[0075] Etch the second abnormal position according to the real-time concentration and real-time temperature, and the etching time is the second etching time.

[0076] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0077] By determining the line width of the PCB circuit board, forming a short-circuit discrimination mechanism for copper residue, constructing an optimization model for etching parameters, forming a first parameter optimization scheme and a second parameter optimization scheme, it is possible to identify etching abnormalities at different positions on the circuit board and adjust the etching duration of the positions with abnormalities, so as to ensure that the etching duration exactly meets the requirements, avoiding both excessive etching that affects conductivity and insufficient etching time that leads to circuit short-circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] Figure 1 is a schematic flowchart of the parameter optimization method for identifying processing abnormalities of a PCB circuit board according to the present invention;

[0079] Figure 2 is a schematic flowchart of determining the line width of a PCB circuit board based on the circuit layout of the PCB circuit board according to the present invention;

[0080] Figure 3 is a schematic flowchart of establishing a conductivity identification function according to the present invention;

[0081] Figure 4 is a schematic flowchart of forming a short-circuit discrimination mechanism for copper residue according to the present invention;

[0082] Figure 5 is a schematic flowchart of constructing an optimization model for etching parameters based on historical data according to the present invention;

[0083] Figure 6 is a schematic flowchart of determining whether there is an abnormality in the etching of a PCB circuit board according to the present invention;

[0084] Figure 7 is a schematic flowchart of forming a first parameter optimization scheme at the first abnormal position according to the present invention;

[0085] Figure 8 is a schematic flowchart of adjusting according to the parameters in the first parameter optimization scheme and the second parameter optimization scheme according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0086] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations.

[0087] Refer to Figure 1As shown in the figure, a parameter optimization method based on the recognition of abnormal PCB circuit board processing includes:

[0088] Obtain the etching parameters of the PCB circuit board, where the etching parameters consist of the concentration, temperature, and etching time of the etching solution;

[0089] Based on the circuit layout of the PCB circuit board, determine the circuit width of the PCB circuit board;

[0090] Form a short - circuit discrimination mechanism for copper residue;

[0091] Based on historical data, construct an optimization model for etching parameters;

[0092] Monitor the etching process of the PCB circuit board to determine whether there is an abnormality in the etching of the PCB circuit board. If not, do nothing. If so, perform parameter optimization;

[0093] During parameter optimization, obtain the real - time concentration, real - time temperature, and actual etching time of the etching solution, obtain the positions where etching abnormalities occur in the PCB circuit board, and based on the types of abnormalities, divide the positions where etching abnormalities occur into the first abnormal position and the second abnormal position;

[0094] Based on the optimization model of etching parameters, form a first parameter optimization plan for the first abnormal position and a second parameter optimization plan for the second abnormal position;

[0095] Regulate according to the parameters in the first parameter optimization plan and the second parameter optimization plan.

[0096] In this solution, the etching conditions at different positions on the PCB circuit board may vary. Therefore, it is necessary to unify the etching to ensure that the width of its circuit is the required width, so that its overall conductivity meets the requirements. In addition, due to the dense circuit of the circuit board, the remaining copper may conduct with the circuit, thereby causing a short - circuit, and the conduction is caused by the too - small distance between the remaining copper and the circuit of the circuit board. Therefore, it is necessary to ensure that the distance between the copper in the non - circuit and the circuit of the circuit board is increased. Therefore, further etching is required here. For the processing efficiency, it is necessary to determine the shortest time to be extended. Therefore, a corresponding algorithm is formed for the first parameter optimization plan.

[0097] Refer to Figure 2 As shown in the figure, determining the circuit width of the PCB circuit board based on the circuit layout of the PCB circuit board includes the following steps:

[0098] Obtain the circuit layout of the circuits in the PCB circuit board, obtain the current input terminal and current output terminal in the circuit layout, and obtain all branches in the circuit layout, where the branch is the circuit connecting the current input terminal and the current output terminal in the circuit layout;

[0099] Obtain the longest branch in the circuit layout as the characteristic branch, and obtain the shortest branch in the circuit layout as the non-characteristic branch;

[0100] Use the length of the characteristic branch and the length of the non-characteristic branch as endpoints to form a characteristic interval;

[0101] Evenly divide the characteristic interval into at least one local interval, and obtain the proportion of the branches whose lengths belong to the local interval as the characteristic proportion;

[0102] Based on historical data, obtain the lower limit value of the conductivity of the PCB circuit board;

[0103] Establish a conductivity identification function;

[0104] Input the lower limit value of conductivity and the midpoint of the local interval into the conductivity identification function to obtain a characteristic value;

[0105] Multiply the characteristic value by the corresponding characteristic proportion and then accumulate to obtain the line width of the PCB circuit board.

[0106] When the circuit layout of the PCB circuit board is determined, its overall length and orientation are determined. The conductivity of the PCB circuit board can be represented by the reciprocal of its resistance, and the resistance is determined by the width of the circuit of the PCB circuit board. The larger the width, the smaller the resistance. Therefore, by combining the lower limit value of the conductivity of the PCB circuit board with the conditions of different branches in the PCB circuit board, the line width of the PCB circuit board is comprehensively obtained. For convenience in calculation, the branches with approximately the same length are processed in the same way.

[0107] Refer to Figure 3 As shown, establishing the conductivity identification function includes the following steps:

[0108] Based on historical data, obtain the conductivity value range of the PCB circuit board, and evenly divide the conductivity value range to obtain at least one conductivity point;

[0109] Obtain the value range of the branch, and evenly divide the value range of the branch to obtain at least one length point;

[0110] Randomly combine at least one conductivity point and at least one length point to obtain at least one test group;

[0111] Obtain the circuit whose conductivity and length are respectively equal to the conductivity point and length point values in the test group as the target circuit, where the target circuit is a line segment;

[0112] Measure and obtain the width of the target circuit, pair and fit the test group with the width of the target circuit to obtain the conductivity identification function, where the conductivity point and length point values in the test group are independent variables and the width of the target circuit is the dependent variable.

[0113] When the length and width of the branch change, its conductivity also changes. Therefore, it is necessary to establish a corresponding model to predict the relationship between them. Thus, the width of the branch can be determined according to the conductivity requirement and the length of the branch, and then the width of the overall circuit can be calculated based on this.

[0114] Refer to Figure 4 As shown, the short - circuit discrimination mechanism for copper residue formation includes the following steps:

[0115] Obtain at least one abnormal circuit board with a short - circuit, where the cause of the short - circuit of the abnormal circuit board is caused by excessive copper residue;

[0116] Perform image recognition on the abnormal circuit board to obtain at least one characteristic region, where the characteristic region is a region covered by copper and has no intersection with the circuits in the abnormal circuit board;

[0117] Obtain the smallest loop in the circuit of the abnormal circuit board that contains the characteristic region as the characteristic loop;

[0118] Obtain the minimum value of the distance from the characteristic loop to the characteristic region it contains as the characteristic distance;

[0119] Take the minimum value of at least one characteristic distance in a single abnormal circuit board as the target distance;

[0120] Take the interval formed by the maximum and minimum values of at least one target distance as endpoints as the short - circuit identification interval;

[0121] When the minimum distance from the residual copper to the circuits in the PCB circuit board belongs to the short - circuit identification interval, the residual copper will cause a short - circuit; otherwise, it will not cause a short - circuit.

[0122] The reason for the short - circuit is that the distance from the residual copper to the circuits in the PCB circuit board is too small, so the two are conducted. Thus, changing the circuit layout may lead to a short - circuit situation. Therefore, it is necessary to determine the possible distance interval and then identify the short - circuit according to this interval.

[0123] Refer to Figure 5 As shown, based on historical data, the steps for constructing an optimized model of etching parameters include the following:

[0124] Obtain the concentration value range of the etching solution, and equally - spaced divide the concentration value range to obtain at least one concentration point;

[0125] Obtain the temperature value range of the etching solution, and equally - spaced divide the temperature value range to obtain at least one temperature point;

[0126] Randomly combine at least one concentration point and at least one temperature point to obtain at least one verification group;

[0127] Obtain the time consumed for etching to reach the line width of the PCB circuit board under the conditions of the verification group as the target time;

[0128] Pair and fit the verification group with the target time to obtain an etching fitting function, where the values of the concentration point and temperature point in the verification group are independent variables and the target time is the dependent variable.

[0129] The purpose of the optimization model of the etching parameters is to predict the etching duration. When the concentration and temperature of the etching solution are determined, the etching duration determines the etching effect. In this solution, it is the most convenient to adjust the etching duration because the adjustment of temperature and concentration requires re - setting, which is more troublesome, while the measurement of time is relatively easy. Therefore, the required etching time is predicted through the optimization model of the etching parameters, the real - time concentration and real - time temperature of the etching solution, and based on this, abnormal regulation is carried out.

[0130] Refer to Figure 6 As shown, determining whether there is an abnormality in the etching of the PCB circuit board includes the following steps:

[0131] Identify the copper residue positions in the PCB circuit board to obtain at least one actual residue area, and the actual residue area is the area covered by copper that has no intersection with the lines in the PCB circuit board;

[0132] Obtain the minimum value from the actual residue area to the lines in the PCB circuit board as the distance to be identified;

[0133] Use the short - circuit discrimination mechanism of copper residue to identify the distance to be identified and obtain the actual residue areas with abnormalities;

[0134] Evenly divide the lines in the PCB circuit board into at least one sampling block, identify the width at the mid - point of the sampling block to obtain the sampling width;

[0135] When the difference between the sampling width and the line width of the PCB circuit board exceeds the preset value, the sampling block corresponding to the sampling width is abnormal.

[0136] Based on the types of abnormalities, classifying the positions with etching abnormalities into the first abnormal position and the second abnormal position includes the following steps:

[0137] Take the actual residue areas with abnormalities as the first abnormal position and the sampling blocks with abnormalities as the second abnormal position.

[0138] Refer to Figure 7 As shown, forming the first parameter optimization plan for the first abnormal position includes the following steps:

[0139] Take at least one recognition point on the contour of the first abnormal position, fit the coordinates of at least one recognition point, and obtain the contour curve function;

[0140] Use a horizontal line to divide the contour of the first abnormal position. The contour curve function above the horizontal line is the upper contour curve function, and the contour curve function below the horizontal line is the lower contour curve function;

[0141] Use the length formula to calculate the length of the contour of the first abnormal position as the characteristic length;

[0142] Uniformly take at least one scaling point in the interval (0, 1), and shrink the first abnormal position according to the value of the scaling point to obtain a reduced area, and the scaling point is the center of the first abnormal position;

[0143] Obtain the minimum distance from the reduced area to the circuit of the PCB as the distance to be monitored;

[0144] Use the short-circuit discrimination mechanism of copper residue to identify the distance to be monitored, and take the distance to be monitored that will not cause a short circuit as the calibrated distance;

[0145] Take the value of the scaling point adopted by the minimum calibrated distance as the characteristic ratio;

[0146] Integrate the area enclosed by the contour curve function to obtain the characteristic area;

[0147] Use the width formula to calculate the etching compensation width of the first abnormal position;

[0148] Input the real-time concentration and real-time temperature into the etching fitting function to obtain the second etching time;

[0149] Multiply the etching compensation width divided by the circuit width of the PCB by the second etching time to obtain the etching time compensation value;

[0150] Overlay the actual etching time consumption and the etching time compensation value to obtain the first etching time, and take the real-time concentration, real-time temperature and the first etching time as the first parameter optimization scheme;

[0151] The length formula is as follows:

[0152]

[0153] Wherein, L is the characteristic length, a and b are respectively the abscissas of the intersection points of the horizontal line and the contour of the first abnormal position, g(x) is the derivative of the upper contour curve function, f(x) is the derivative of the lower contour curve function, and x is the abscissa of the point on the contour of the first abnormal position;

[0154] The width formula is as follows:

[0155]

[0156] Wherein, B is the etching compensation width, k is the feature ratio, and S is the feature area.

[0157] The elimination of the residual copper is different from the etching of the circuit on the PCB board. Its main purpose is to etch the residual copper until no short circuit occurs. This can be judged by the short circuit discrimination mechanism of the copper residue. Thus, the feature ratio is obtained. The feature ratio is the ratio that requires the least etching time for optimization. The feature ratio is the ratio of the copper after etching to the copper before etching. The difference between the area of the copper after etching and the area of the copper before etching is the feature area. This is an annular band-shaped area. Then, the width of the band-shaped area can be approximately regarded as the etching compensation width. Since etching the line width of the PCB board requires a second etching time, therefore, proportionally, the etching time compensation value corresponding to the etching compensation width is obtained. Since the etching itself takes the actual etching time, therefore, the actual etching time is superimposed with the etching time compensation value to obtain the first etching time.

[0158] Forming the second parameter optimization plan at the second abnormal position includes the following steps:

[0159] Taking the real-time concentration, real-time temperature, and the second etching time as the second parameter optimization plan.

[0160] Since the optimization model of the etching parameters is specifically set for the second abnormal position, therefore, directly inputting the real-time concentration and real-time temperature into the etching fitting function can obtain the required etching duration.

[0161] Refer to Figure 8 As shown, the regulation according to the parameters in the first parameter optimization plan and the second parameter optimization plan includes the following steps:

[0162] Etch the part of the PCB board except the first abnormal position and the second abnormal position according to the real-time concentration and real-time temperature, and the etching time is the actual etching time;

[0163] Etch the first abnormal position according to the real-time concentration and real-time temperature, and the etching time is the first etching time;

[0164] Etch the second abnormal position according to the real-time concentration and real-time temperature, and the etching time is the second etching time.

[0165] Assume that they are arranged in size as: the actual etching time, the first etching time, and the second etching time. Among them, the second etching time is the largest;

[0166] When the etching duration reaches the actual etching time, only keep the etching solution on the surfaces of the first abnormal position and the second abnormal position;

[0167] When the etching duration reaches the first etching time, the etching solution is only retained on the surface of the second abnormal position;

[0168] When the etching duration reaches the second etching time, all the etching solution is removed;

[0169] For any size order of the actual etching time, the first etching time, and the second etching time, the above method is adopted for processing.

[0170] Furthermore, this solution also proposes a storage medium, on which a computer-readable program is stored. When the computer-readable program is called, it executes the above-mentioned parameter optimization method for identifying processing anomalies of a PCB circuit board.

[0171] It can be understood that the storage medium can be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; an optical medium, such as a DVD; or a semiconductor medium, such as a solid-state disk (SSD).

[0172] In summary, the advantages of the present invention are as follows: By determining the line width of the PCB circuit board, forming a short-circuit discrimination mechanism for copper residue, constructing an optimization model for etching parameters, and forming a first parameter optimization scheme and a second parameter optimization scheme, it is possible to identify etching anomalies at different positions on the circuit board and adjust the etching duration of the positions with anomalies, so as to ensure that the etching duration exactly meets the requirements, avoiding excessive etching that affects conductivity and insufficient etching time that causes circuit short circuits.

[0173] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. What is described in the above embodiments and the specification is only the principle of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of protection claimed by the present invention is defined by the appended claims and their equivalents.

Claims

1. A parameter optimization method based on PCB circuit board processing abnormality identification, characterized in that: include: Obtain the etching parameters of the PCB circuit board, which are composed of the concentration, temperature and etching time of the etching solution; Based on the circuit layout of the PCB circuit board, determine the circuit width of the PCB circuit board; Forming a short-circuit discrimination mechanism for copper residue; Based on historical data, an optimization model for etching parameters is constructed; Monitor the etching process of the PCB circuit board to determine whether there is any abnormality in the etching of the PCB circuit board. If not, no treatment will be performed. If yes, parameter optimization will be performed. When optimizing parameters, the real-time concentration, real-time temperature and actual etching time of the etching solution are obtained, the position where the etching is abnormal in the PCB circuit board is obtained, and based on the type of abnormality, the position where the etching is abnormal is divided into a first abnormal position and a second abnormal position; Based on the optimization model of etching parameters, a first parameter optimization scheme is formed at a first abnormal position, and a second parameter optimization scheme is formed at a second abnormal position; The parameters in the first parameter optimization scheme and the second parameter optimization scheme are adjusted.

2. A parameter optimization method based on PCB circuit board processing abnormality identification according to claim 1, characterized in that: Determining the line width of the PCB circuit board based on the line layout of the PCB circuit board includes the following steps: Obtaining a circuit layout of a circuit in a PCB circuit board, obtaining a current input terminal and a current output terminal in the circuit layout, and obtaining all branches in the circuit layout, wherein the branch is a circuit in the circuit layout connecting the current input terminal and the current output terminal; The longest branch in the line layout is obtained as a characteristic branch, and the shortest branch in the line layout is obtained as a non-characteristic branch; Use the length of the characteristic branch and the length of the non-characteristic branch as endpoints to form a characteristic interval; Evenly divide the feature interval into at least one local interval, and obtain the proportion of branches whose lengths belong to the local interval as the feature proportion; Based on historical data, obtain the lower limit value of the conductivity of the PCB circuit board; Establishing the electrical conductivity identification function; Input the conductivity lower limit value and the midpoint of the local interval into the conductivity identification function to obtain the characteristic value; The characteristic value is multiplied by the corresponding characteristic proportion and then added up to obtain the line width of the PCB circuit board.

3. A parameter optimization method based on PCB circuit board processing abnormality identification according to claim 2, characterized in that: The establishment of the conductivity identification function comprises the following steps: Based on historical data, a conductivity value range of the PCB circuit board is obtained, and the conductivity value range is divided into equal intervals to obtain at least one conductive point; Obtain a value range of the branch, divide the value range of the branch into equal intervals, and obtain at least one length point; Randomly combining at least one conductive point and at least one length point to obtain at least one test group; Acquire a line whose conductivity and length are respectively equal to the values ​​of the conductivity point and the length point in the test group as a target line, wherein the target line is a line segment; The width of the target line is measured and obtained, and the test group is paired with the width of the target line and fitted to obtain a conductive performance identification function, wherein the values ​​of the conductive points and length points in the test group are independent variables, and the width of the target line is a dependent variable.

4. A parameter optimization method based on PCB circuit board processing abnormality identification according to claim 3, characterized in that: The short circuit discrimination mechanism for forming copper residues comprises the following steps: Obtain at least one abnormal circuit board with a short circuit, where the short circuit of the abnormal circuit board is caused by excessive copper residue; Perform image recognition on the abnormal circuit board to obtain at least one characteristic region, where the characteristic region is a region covered by copper and has no intersection with the circuits in the abnormal circuit board; Obtain the minimum loop of the circuit in the abnormal circuit board that contains the characteristic area as the characteristic loop; Obtain the minimum value of the distance from the characteristic loop to the characteristic region it contains as the characteristic distance; The minimum value of at least one characteristic distance in a single abnormal circuit board is used as the target distance; An interval formed by taking the maximum value and the minimum value of at least one target distance as endpoints is used as a short circuit identification interval; When the minimum distance from the residual copper to the circuit in the PCB circuit board belongs to the short circuit identification interval, the residual copper will cause a short circuit, otherwise, it will not cause a short circuit.

5. A parameter optimization method based on PCB circuit board processing abnormality identification according to claim 4, characterized in that: The method of constructing an optimization model for etching parameters based on historical data comprises the following steps: Obtaining a concentration value range of the etching solution, dividing the concentration value range at equal intervals, and obtaining at least one concentration point; Obtaining a temperature value range of the etching solution, dividing the temperature value range at equal intervals, and obtaining at least one temperature point; Randomly combining at least one concentration point and at least one temperature point to obtain at least one validation group; Obtain the time taken to etch the line width of the PCB circuit board under the conditions of the verification group as the target time; The validation group is paired with the target time and fitted to obtain an etching fitting function, wherein the values ​​of the concentration points and temperature points in the validation group are independent variables and the target time is the dependent variable.

6. A parameter optimization method based on PCB circuit board processing abnormality identification according to claim 5, characterized in that: The method of judging whether there is an abnormality in the etching of the PCB circuit board comprises the following steps: Identify the copper residue position in the PCB circuit board to obtain at least one actual residue area, where the actual residue area is an area covered by copper that has no intersection with the circuits in the PCB circuit board; Obtain the minimum value from the actual residual area to the circuit in the PCB circuit board as the distance to be identified; Use the short-circuit discrimination mechanism of copper residue to identify the distance to be identified and obtain the actual residue area with abnormality; Evenly divide the circuits in the PCB circuit board into at least one sampling block, identify the width at the midpoint of the sampling block, and obtain the sampling width; When the difference between the sampling width and the line width of the PCB circuit board exceeds a preset value, the sampling block corresponding to the sampling width is abnormal.

7. A parameter optimization method based on PCB circuit board processing abnormality identification according to claim 6, characterized in that: The step of dividing the etching abnormality location into the first abnormal location and the second abnormal location based on the abnormality type comprises the following steps: The actual residual area where the abnormality exists is taken as the first abnormal position, and the sampling block where the abnormality exists is taken as the second abnormal position.

8. A parameter optimization method based on PCB circuit board processing abnormality identification according to claim 7, characterized in that: The first parameter optimization scheme for forming the first abnormal position comprises the following steps: Taking at least one identification point on the contour of the first abnormal position, fitting the coordinates of the at least one identification point to obtain a contour curve function; The contour of the first abnormal position is segmented using a horizontal line, the contour curve function above the horizontal line is an upper contour curve function, and the contour curve function below the horizontal line is a lower contour curve function; Using the length formula, the length of the contour of the first abnormal position is calculated as the characteristic length; Uniformly select at least one scaling point in the interval (0, 1), and reduce the first abnormal position according to the value of the scaling point to obtain a reduced area, where the scaling point is the center of the first abnormal position; Obtain the minimum distance from the reduced area to the circuit of the PCB circuit board as the distance to be monitored; Use the copper residual short circuit discrimination mechanism to identify the monitoring distance, and use the monitoring distance that will not cause short circuit as the calibration distance; The value of the scaling point used for the minimum calibration distance is used as the feature scale; Integrate the area enclosed by the contour curve function to obtain the characteristic area; Using the width formula, the etching compensation width of the first abnormal position is calculated; Inputting the real-time concentration and the real-time temperature into the etching fitting function to obtain a second etching time; The etching compensation width is divided by the line width of the PCB circuit board and then multiplied by the second etching time to obtain an etching time compensation value; The actual etching time is superimposed with the etching time compensation value to obtain a first etching time, and the real-time concentration, the real-time temperature and the first etching time are used as a first parameter optimization scheme; The length formula is as follows: Wherein, L is the characteristic length, a and b are the horizontal coordinates of the intersection of the horizontal line and the contour of the first abnormal position, g(x) is the derivative of the upper contour curve function, f(x) is the derivative of the lower contour curve function, and x is the horizontal coordinate of the point on the contour of the first abnormal position; The width formula is as follows: Wherein, B is the etching compensation width, k is the feature ratio, and S is the feature area.

9. A parameter optimization method based on PCB circuit board processing abnormality identification according to claim 8, characterized in that: The second parameter optimization scheme for forming the second abnormal position comprises the following steps: The real-time concentration, real-time temperature and the second etching time are used as the second parameter optimization scheme.

10. A parameter optimization method based on PCB circuit board processing abnormality identification according to claim 9, characterized in that: The control according to the parameters in the first parameter optimization scheme and the second parameter optimization scheme comprises the following steps: Etching the portion of the PCB circuit board other than the first abnormal position and the second abnormal position according to the real-time concentration and the real-time temperature, wherein the etching time is the actual etching time; Etching the first abnormal position according to the real-time concentration and the real-time temperature, and the etching time is the first etching time; The second abnormal position is etched according to the real-time concentration and the real-time temperature, and the etching time is the second etching time.

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