Gaas-based enhancement / depletion pheMT structure, epitaxial structure and method of manufacturing the same

Abstract

The application provides a GaAs-based enhancement / depletion type PHEMT structure, an epitaxial structure and a preparation method thereof. By arranging an epitaxial insertion layer composed of a GaAs insertion layer and a GaP insertion layer between a second AlGaAs barrier layer (an enhancement type barrier layer) and an InGaP barrier layer (a depletion type barrier layer), growing the GaAs insertion layer and the GaP insertion layer in sequence after the growth of the second AlGaAs barrier layer, and then growing the InGaP barrier layer, low-bandgap InGaAs or InGaAsP intermediate layers generated by the influence of As and P exchange processes can be effectively avoided, meanwhile, the epitaxial insertion layer can also reduce or even avoid the risk of diffusion of As atoms in the second AlGaAs barrier layer to the InGaP barrier layer to generate an InGaAsP low-bandgap interface layer, so that the growth interface of the second AlGaAs barrier layer and the InGaP barrier layer and the growth quality of the barrier layer are optimized.

Description

Technical Field

[0001] This invention relates to the field of HEMT semiconductor technology, and in particular to a GaAs-based enhanced / depletion-type PHEMT structure, epitaxial structure, and preparation method thereof. Background Technology

[0002] Gallium arsenide (GaAs), as a mature compound semiconductor material, possesses high breakdown voltage and is widely used in ultra-high-speed and ultra-high-frequency devices. GaAs-based pseudomolecular high electron mobility transistors (GaAs-based PHEMTs) feature high frequency, high power gain, and low noise, making them widely used in communication fields such as fiber optic communication, microwave communication, and satellite communication, as well as in integrated circuits. In GaAs-based PHEMTs, due to approximately 1% lattice mismatch between InGaAs (channel layer) and GaAs, the InGaAs channel layer is typically grown very thin, causing lattice distortion to absorb stress; this structure is commonly referred to as a pseudomolecular structure.

[0003] With the development of GaAs-based PHEMT structures, four basic logic circuit forms for GaAs ICs have been proposed: BFL (Buffered FET Logic); SDFL (Schottky Diode FET Logic); SCFL (Source Coupled FET Logic); and DCFL (Direct Coupled FET Logic). The first three are based on depletion-mode FETs, while DCFL is based on enhancement / depletion-mode FETs. BFL, SCFL, and SDFL require dual or negative power supplies and suffer from level drift, resulting in complex GaAs IC logic circuit structures and high power consumption, making them unsuitable for large-scale integrated circuit design. In contrast, DCFL logic circuits offer advantages such as low power consumption, high speed, very simple circuit structure (e.g., no level drift), and a single power supply, making it considered one of the best logic technologies for large-scale integrated circuits.

[0004] The quality of GaAs-based enhanced / depletion-mode PHEMT epitaxial structures plays a decisive role in the performance of the final product. In existing GaAs-based enhanced / depletion-mode PHEMT epitaxial structures, AlGaAs is used as the enhancement barrier layer and InGaP is grown on it as the depletion barrier layer. The barrier layer is an important device layer that restricts the movement of the two-dimensional electron gas (2-DEG) and forms a quantum well. Therefore, the high-quality material growth of the AlGaAs enhancement barrier layer and the InGaP depletion barrier layer is the foundation for realizing the structural performance of GaAs-based enhanced / depletion-mode PHEMT devices. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a GaAs-based reinforced / depleted PHEMT structure, epitaxial structure and preparation method thereof, to solve the problem of low material growth quality of AlGaAs reinforced barrier layer and InGaP depleted barrier layer in GaAs-based reinforced / depleted PHEMT epitaxial structure in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a GaAs-based enhanced / depletion-type PHEMT epitaxial structure, the epitaxial structure comprising:

[0007] Substrate; and

[0008] The following layers are arranged sequentially from bottom to top on one side of the substrate: a buffer layer, a first AlGaAs barrier layer, a first AlGaAs isolation layer, an InGaAs channel layer, a second AlGaAs isolation layer, a second AlGaAs barrier layer, an epitaxial insertion layer, an InGaP barrier layer, and a GaAs cap layer.

[0009] The epitaxial insertion layer includes, from bottom to top, a GaAs insertion layer and a GaP insertion layer;

[0010] The buffer layer, from bottom to top, includes a GaAs buffer layer and a superlattice buffer layer composed of AlGaAs layers / GaAs layers.

[0011] Optionally, the thickness of the GaAs insertion layer is 0.25 nm to 0.35 nm, and the thickness of the GaP insertion layer is 0.3 nm to 0.6 nm.

[0012] Optionally, the upper surface of the first AlGaAs barrier layer is doped with a first silicon δ doping, and the upper surface of the second AlGaAs isolation layer is doped with a second silicon δ doping, wherein the doping concentration of the second silicon δ doping is 2.9 to 3.1 times that of the first silicon δ doping; the upper and lower surfaces of the InGaAs channel layer are pre-set to a GaAs growth transition layer with a predetermined thickness, and the composition of the remaining thickness of the InGaAs channel layer is denoted as In. x Ga 1-x In the As layer, the value of the In component x is 0.25 < x < 0.3, and the In... x Ga 1-x The As layer underwent silicon doping with gradually increasing doping concentration from bottom to top.

[0013] Furthermore, the InGaAs channel layer contains In x Ga 1-xThe thickness of the As layer is 8 nm to 10 nm, and the thickness of the GaAs growth transition layer is 0.9 nm to 1.1 nm; the In... x Ga 1-x The silicon doping concentration in the As layer is 2E17cm⁻¹ -3 Gradient to 4E17cm -3 .

[0014] Furthermore, the doping concentration of the first silicon δ-doped silicon is 1.4E12cm⁻¹. -2 ~1.6E12cm -2 The doping concentration of the second silicon δ-doped silicon is 4.2E12cm⁻¹. -2 ~4.8E12cm -2 .

[0015] Optionally, the GaAs cap layer is a silicon-doped GaAs cap layer, and the silicon doping concentration is 0.5E19cm⁻¹. -3 ~1.0E19cm -3 .

[0016] Further, the thickness of the GaAs buffer layer is 100nm to 200nm; the single-layer thickness of the AlGaAs layer in the superlattice buffer layer is 9nm to 11nm, and the single-layer thickness of the GaAs layer is 1.3nm to 1.7nm; the thickness of the first AlGaAs barrier layer is 30nm to 40nm; the thickness of the first AlGaAs isolation layer is 5nm to 10nm; the thickness of the second AlGaAs isolation layer is 5nm to 10nm; the thickness of the second AlGaAs barrier layer is 6nm to 10nm; the thickness of the InGaP barrier layer is 30nm to 35nm; and the thickness of the GaAs cap layer is 48nm to 52nm.

[0017] This invention also provides a method for preparing a GaAs-based enhanced / depletion-type PHEMT epitaxial structure, the method comprising the following steps:

[0018] S1: Provides a substrate;

[0019] S2: A GaAs buffer layer and a superlattice buffer layer composed of AlGaAs layer / GaAs layer are grown sequentially on one side of the substrate at a growth temperature of 580℃~600℃.

[0020] S3: Grow a first AlGaAs barrier layer on the superlattice buffer layer;

[0021] S4: Grow a first AlGaAs isolation layer on the first AlGaAs barrier layer;

[0022] S5: An InGaAs channel layer is grown on the first AlGaAs isolation layer at a growth temperature of 480℃~500℃;

[0023] S6: Heat to 580℃~600℃ to grow a second AlGaAs isolation layer on the InGaAs channel layer;

[0024] S7: A second AlGaAs barrier layer and a GaAs insertion layer are sequentially grown on the second AlGaAs isolation layer;

[0025] S8: Reduce the temperature to 500℃~520℃, and sequentially grow a GaP insertion layer and an InGaP barrier layer on the GaAs insertion layer.

[0026] S9: Grow a GaAs cap layer on the InGaP barrier layer.

[0027] Optionally, in step S4, the upper surface of the first AlGaAs barrier layer is first subjected to silicon δ-doping before the first AlGaAs isolation layer is grown; in step S5, the upper and lower surfaces of the InGaAs channel layer are pre-set to have a GaAs growth transition layer thickness, and the composition of the InGaAs channel layer with the remaining thickness is denoted as In x Ga 1-x In the As layer, the value of the In component x is 0.25 < x < 0.3, and the In... x Ga 1-x The As layer undergoes silicon doping with gradually increasing doping concentration from bottom to top; after the second AlGaAs isolation layer is formed in step S6, its upper surface is subjected to second silicon δ doping.

[0028] The present invention also provides a GaAs-based enhanced / depletion-type PHEMT structure, wherein the PHEMT structure is prepared based on the GaAs-based enhanced / depletion-type PHEMT epitaxial structure described in any of the above claims.

[0029] As described above, the GaAs-based enhanced / depletion-type PHEMT structure, epitaxial structure, and preparation method of the present invention, by setting an epitaxial insertion layer composed of GaAs and GaP insertion layers between the second AlGaAs barrier layer (enhanced barrier layer) and the InGaP barrier layer (depletion-type barrier layer), and performing the second AlGaAs barrier layer growth, first growing the GaAs and GaP insertion layers sequentially, and then growing the InGaP barrier layer, can effectively avoid the low bandgap InGaAs or InGaAsP intermediate layers caused by the As and P exchange process. At the same time, the epitaxial insertion layer can also reduce or even avoid the risk of As atoms in the second AlGaAs barrier layer diffusing into the InGaP barrier layer, generating a low bandgap InGaAsP interface layer, thus achieving the effect of optimizing the growth interface and barrier layer growth quality of the second AlGaAs barrier layer and the InGaP barrier layer. Attached Figure Description

[0030] Figure 1 The diagram shown is a cross-sectional schematic of a GaAs-based enhanced / depleted PHEMT epitaxial structure according to an embodiment of the present invention.

[0031] Figure 2 The diagram shown is a cross-sectional view of the InGaAs channel layer in this embodiment.

[0032] Figure 3 The diagram shown is a cross-sectional structural schematic of the epitaxial insertion layer in this embodiment.

[0033] Figure 4 This diagram illustrates the shutter sequence during the growth of the enhancement barrier layer to the GaAs cap layer in a GaAs-based enhanced / depleted PHEMT epitaxial structure fabrication method according to an embodiment of the present invention.

[0034] Figure 5 The diagram shows a flow chart of a method for preparing a GaAs-based enhanced / depleted PHEMT epitaxial structure according to an embodiment of the present invention.

[0035] Component designation explanation

[0036] 10 Substrates

[0037] 11 Buffer Layer

[0038] 110 GaAs buffer layer

[0039] 111 Superlattice Buffer Layer

[0040] 12 First AlGaAs Barrier Layer

[0041] 120 First silicon δ-doped

[0042] 13 First AlGaAs isolation layer

[0043] 14 InGaAs channel layer

[0044] 140 GaAs Growth Transition Layer

[0045] 141 In x Ga 1-x As layer

[0046] 15 Second AlGaAs isolation layer

[0047] 150 Second silicon δ-doped

[0048] 16 Second AlGaAs barrier layer

[0049] 17 Epitaxial Insertion Layer

[0050] 170 GaAs Insertion Layer

[0051] 171 GaP Insertion Layer

[0052] 18 InGaP barrier layer

[0053] 19 GaAs cap layer Detailed Implementation

[0054] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0056] It should be understood that the use of terms such as "first," "second," and "third" to define the components is merely for the purpose of distinguishing the aforementioned components. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this invention.

[0057] Please see Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0058] like Figure 1 and Figure 3 As shown, this embodiment provides a GaAs-based enhanced / depletion-type PHEMT epitaxial structure, the epitaxial structure comprising:

[0059] Substrate 10; and

[0060] The buffer layer 11, the first AlGaAs barrier layer 12, the first AlGaAs isolation layer 13, the InGaAs channel layer 14, the second AlGaAs isolation layer 15, the second AlGaAs barrier layer 16, the epitaxial insertion layer 17, the InGaP barrier layer 18 and the GaAs cap layer 19 are arranged sequentially from bottom to top on one side of the substrate 10.

[0061] The epitaxial insertion layer 17 includes, from bottom to top, a GaAs insertion layer 170 and a GaP insertion layer 171;

[0062] The buffer layer 11 includes, from bottom to top, a GaAs buffer layer 110 and a superlattice buffer layer 111 composed of AlGaAs layers / GaAs layers.

[0063] In GaAs-based enhancement / depletion type PHEMT epitaxial structures, when an AlGaAs barrier layer (enhancement barrier layer) and an InGaP barrier layer (depletion barrier layer) are formed in direct contact, a low-bandgap InGaAs or InGaAsP intermediate layer is formed at the interface due to the As-to-As exchange process. Furthermore, As atoms readily diffuse from a surface layer deeper into the bulk InGaP; prolonged irradiation of As allows As to diffuse into the InGaP material, forming the InGaAsP interface layer. Since InGaAs or InGaAsP have lower bandgap than InGaP or AlGaAs, the position of the interface PL peak is not entirely determined by the band shift between InGaP and AlGaAs, thus affecting the band shift between the AlGaAs and InGaP barrier layers and consequently reducing the performance of GaAs-based enhancement / depletion type PHEMT devices. In this embodiment, an epitaxial insertion layer 17, consisting of a GaAs insertion layer 170 and a GaP insertion layer 171, is provided between the second AlGaAs barrier layer 16 (enhancement barrier layer) and the InGaP barrier layer 18 (depletion barrier layer). After the second AlGaAs barrier layer 16 is grown, the GaAs insertion layer 170 and the GaP insertion layer 171 are grown sequentially, and then the InGaP barrier layer 18 is grown. This effectively avoids the low bandgap InGaAs or InGaAsP intermediate layers caused by the As and P exchange process. At the same time, the epitaxial insertion layer 17 can also reduce or even avoid the risk of As atoms in the second AlGaAs barrier layer 16 diffusing into the InGaP barrier layer 18 and generating a low bandgap InGaAsP interface layer, thereby optimizing the growth interface and barrier layer growth quality of the second AlGaAs barrier layer 16 and the InGaP barrier layer 18.

[0064] As a preferred example, the thickness of the GaAs insertion layer 170 is 0.25 nm to 0.35 nm, and the thickness of the GaP insertion layer 171 is 0.3 nm to 0.6 nm. More preferably, the thickness of the GaAs insertion layer 170 is approximately 0.3 nm, and the thickness of the GaP insertion layer 171 can be selected within the range of 0.3 nm to 0.6 nm.

[0065] As another better example, such as Figure 1 and Figure 2As shown, the upper surface of the first AlGaAs barrier layer 12 is doped with a first silicon δ-doped layer 120, and the upper surface of the second AlGaAs isolation layer 15 is doped with a second silicon δ-doped layer 150. The doping concentration of the second silicon δ-doped layer 150 is 2.9 to 3.1 times that of the first silicon δ-doped layer 120, more preferably 3 times. The upper and lower surfaces of the InGaAs channel layer 14 are pre-set to a GaAs growth transition layer 140 in thickness, and the remaining thickness of the InGaAs channel layer is denoted as In. x Ga 1-x As layer 141, wherein the In component x takes the value of 0.25 < x < 0.3, and the In x Ga 1-x As layer 141 undergoes silicon doping with gradually increasing doping concentration from bottom to top (i.e., along the growth direction). While considering the impact of In / As content in the channel layer on lattice mismatch, moderately increasing the In / As content in the channel layer (x is 0.25 < x < 0.3) effectively improves the electron transport velocity in the channel. Furthermore, adding graded silicon doping to the channel layer and synergistically changing the silicon δ-doping ratio on both sides of the channel layer (2.9 to 3.1 times) effectively improves the efficiency of electron transfer from the silicon δ-doped layer to the channel layer in the epitaxial layer, increases the 2DEG density in the channel, and improves the 2DEG distribution, making the electron distribution in the channel approach a square well. This results in a more uniform electron distribution in the channel, thereby improving the linearity of the PHEMT device, making it more suitable for high-linearity applications in microwave power devices. It also improves the Ids performance and noise performance of the PHEMT device.

[0066] Furthermore, such as Figure 2 As shown, the InGaAs channel layer 14 contains In x Ga 1-x The thickness of the As layer 141 is 8 nm to 10 nm; the thickness of the GaAs growth transition layer 140 is 0.9 nm to 1.1 nm, for example, it can be 0.9 nm, 1.0 nm, or 1.1 nm; the In... x Ga 1-x The silicon doping concentration in As layer 141 is 2E17cm⁻¹ -3 Gradient to 4E17cm -3 Even better, such as Figure 1 As shown, the doping concentration of the first silicon δ-doped 120 is 1.4E12cm. -2 ~1.6E12cm -2 The doping concentration of the second silicon δ-doped 150 is 4.2E12cm. -2 ~4.8E12cm -2Ideally, the doping concentration of the first silicon δ-doped 120 is 1.5E12cm⁻¹. -2 The doping concentration of the second silicon δ-doped 150 is 4.5E12cm. -2 .

[0067] As an example, the GaAs cap layer 19 is a silicon-doped GaAs cap layer, and the silicon doping concentration is 0.5E19cm. -3 ~1.0E19cm -3 .

[0068] As a specific example, the thickness of each layer in the GaAs-based enhanced / depletion-type PHEMT epitaxial structure is as follows: the thickness of the GaAs buffer layer 110 is 100nm to 200nm; the single-layer thickness of the AlGaAs layer in the superlattice buffer layer 111 is 9nm to 11nm (preferably 10nm), the single-layer thickness of the GaAs layer is 1.3nm to 1.7nm (preferably 1.5nm), and the cycle count is 18 to 22 (preferably 20); the thickness of the first AlGaAs barrier layer 12 is 30nm to 40nm; the thickness of the first AlGaAs isolation layer 13 is 5nm to 10nm; and the InGaAs channel layer 14 contains In... x Ga 1-x The thickness of the As layer 141 is 8 nm to 10 nm, the thickness of the GaAs growth transition layer 140 is 0.9 nm to 1.1 nm (preferably 1 nm), the thickness of the second AlGaAs isolation layer 15 is 5 nm to 10 nm, the thickness of the second AlGaAs barrier layer 16 is 6 nm to 10 nm, the thickness of the GaAs insertion layer 170 is 0.25 nm to 0.35 nm (preferably 0.3 nm), the thickness of the GaP insertion layer 171 is 0.3 nm to 0.6 nm, the thickness of the InGaP barrier layer 18 is 30 nm to 35 nm, and the thickness of the GaAs cap layer 19 is 48 nm to 52 nm (preferably 50 nm).

[0069] As a specific example, when the GaAs-based reinforced / depletion-type PHEMT epitaxial structure involves AlGaAs material, its composition is denoted as Al. x Ga 1-x As, where the Al component x takes values ​​of 0.2 < x < 0.3; when dealing with InGaP materials, its component is denoted as In. y Ga 1-y P, where the component y of In takes the value 0.49 < x < 0.51.

[0070] This embodiment also provides a method for preparing a GaAs-based enhanced / depletion-type PHEMT epitaxial structure, used to prepare the aforementioned GaAs-based enhanced / depletion-type PHEMT epitaxial structure. Figure 5 This is a schematic diagram of the process for fabricating the GaAs-based enhanced / depleted PHEMT epitaxial structure in this embodiment. Figure 1 To obtain the GaAs-based enhanced / depleted PHEMT epitaxial structure using this preparation method, the preparation method includes the following steps:

[0071] S1: Provides a substrate;

[0072] S2: A GaAs buffer layer and a superlattice buffer layer composed of AlGaAs layer / GaAs layer are grown sequentially on one side of the substrate at a growth temperature of 580℃~600℃.

[0073] S3: Grow a first AlGaAs barrier layer on the superlattice buffer layer;

[0074] S4: Grow a first AlGaAs isolation layer on the first AlGaAs barrier layer;

[0075] S5: An InGaAs channel layer is grown on the first AlGaAs isolation layer at a growth temperature of 480℃~500℃;

[0076] S6: Heat to 580℃~600℃ to grow a second AlGaAs isolation layer on the InGaAs channel layer;

[0077] S7: A second AlGaAs barrier layer and a GaAs insertion layer are sequentially grown on the second AlGaAs isolation layer;

[0078] S8: Reduce the temperature to 500℃~520℃, and sequentially grow a GaP insertion layer and an InGaP barrier layer on the GaAs insertion layer.

[0079] S9: Grow a GaAs cap layer on the InGaP barrier layer.

[0080] As an example, the GaAs-based enhanced / depleted PHEMT epitaxial structure in this embodiment is prepared using molecular beam epitaxy (MBE). Furthermore, a "growth interruption method" is employed during the MBE process to improve the crystallinity of the epitaxial film, control interface properties, or achieve specific material structures.

[0081] Specifically, such as Figure 1As shown, in step S1, a substrate 10 is provided. The substrate 10 includes, but is not limited to, gallium arsenide substrates of 2 inches, 4 inches, 6 inches, and 8 inches, as well as composite substrates composed of silicon-based gallium arsenide. In this embodiment, a semi-insulating GaAs substrate is used as the substrate 10 for the epitaxial structure growth.

[0082] As an example, in step S2, the GaAs buffer layer 110 grown on the substrate 10 typically has a thickness of 100nm to 200nm, which can make the surface of the substrate 10 smooth after high-temperature deoxidation. The superlattice buffer layer 111 grown on the GaAs buffer layer 110 can effectively prevent defects in the substrate 10 from extending into the channel within a short growth time, thereby ensuring the quality of the channel layer adjacent to the buffer layer. The single-layer thickness of the AlGaAs layer in the superlattice buffer layer 111 is 9nm to 11nm (preferably 10nm), the single-layer thickness of the GaAs layer is 1.3nm to 1.7nm (preferably 1.5nm), and the cycle count is 18 to 22 (preferably 20). In step S3, the thickness of the first AlGaAs barrier layer 12 grown is 30nm to 40nm. In step S4, the thickness of the first AlGaAs isolation layer 13 grown is 5nm to 10nm. In step S5, the InGaAs channel layer 14 grown contains In x Ga 1-x The thickness of the As layer 141 is 8 nm to 10 nm, and the thickness of the GaAs growth transition layer 140 is 0.9 nm to 1.1 nm (preferably 1 nm). In step S6, the thickness of the grown second AlGaAs isolation layer 15 is 5 nm to 10 nm. In step S7, the thickness of the grown second AlGaAs barrier layer 16 is 6 nm to 10 nm, and the thickness of the GaAs insertion layer 170 is 0.25 nm to 0.35 nm (preferably 0.3 nm). In step S8, the thickness of the grown GaP insertion layer 171 is 0.3 nm to 0.6 nm, and the thickness of the InGaP barrier layer 18 is 30 nm to 35 nm. In step S9, the thickness of the grown GaAs cap layer 19 is 48 nm to 52 nm (preferably 50 nm).

[0083] In the method for preparing GaAs-based reinforced / depleted PHEMT epitaxial structures in this embodiment, the same growth temperature is used when growing AlGaAs and GaAs materials, for example, the growth temperature of 580℃~600℃ in step S1.

[0084] like Figure 4The diagram shown illustrates the shutter sequence during the growth of the enhancement barrier layer (i.e., the second AlGaAs barrier layer 16) to the GaAs cap layer 19 in the GaAs-based enhanced / depleted PHEMT epitaxial structure fabrication method of this embodiment. (Combined with...) Figure 1 and Figure 4 The time period is as follows: a) is the growth time of the second AlGaAs barrier layer 16, and the specific growth time is determined according to the thickness and growth rate; b) is the growth time of the GaAs insertion layer 170, which is used to protect the second AlGaAs barrier layer 16 from the influence of the MBE cavity environment during the growth temperature change waiting process, and also to protect the material composition from the influence of P element during the As / P switching process; c) is the temperature change time between the growth temperature of the second AlGaAs barrier layer 16 and the InGaP barrier layer 18. During this process, the As source is continuously introduced to protect the growth surface. There is a large temperature difference between the growth temperatures of AlGaAs and InGaP materials. As mentioned above, the growth temperature of the second AlGaAs barrier layer 16 is 580℃~600℃, and the growth temperature of the InGaP barrier layer 18 is 500℃~520℃; d) is the growth time of the second AlGaAs barrier layer 16. The time of the As / P exchange process in the structure of As barrier layer 16 and InGaP barrier layer 18; the e time period is the stabilization time of the P atmosphere after the As / P exchange; the f time period is the growth time of the GaP insertion layer 171, which is used to protect the InGaP barrier layer 18 (depletion-type barrier layer), serving as an interface between arsenide and phosphide materials, protecting the energy level of the depletion-type barrier layer, and improving the growth quality of the barrier layer; the g time period is the growth time of the InGaP barrier layer 18, the specific growth time being determined according to the thickness and growth rate; the h time period is the temperature change time between the InGaP barrier layer 18 and the GaAs cap layer 19, during which the P source is continuously introduced to protect the growth surface; the i time period is the As / P exchange process time, preventing the diffusion effect of As atoms; the j time period is the growth time of the GaAs cap layer 19; and the k time period is the cooling time after the growth is completed.

[0085] like Figure 1 As shown, as a preferred example, in step S4, the first AlGaAs barrier layer 12 is first subjected to silicon δ-doping 120 on its upper surface before the first AlGaAs isolation layer 13 is grown; Figure 2 As shown, the upper and lower surfaces of the InGaAs channel layer 14 formed in step S5 have a preset thickness of GaAs growth transition layer 140, and the remaining thickness of the InGaAs channel layer 14 is denoted as In x Ga 1-x As layer 141, wherein the In component x takes the value of 0.25 < x < 0.3, and the In x Ga1-x As layer 141 is doped with silicon with gradually increasing doping concentration from bottom to top; after the second AlGaAs isolation layer 15 is formed in step S6, its upper surface is doped with second silicon δ doping 150.

[0086] This embodiment also provides a GaAs-based enhanced / depletion-type PHEMT structure, which is prepared based on the GaAs-based enhanced / depletion-type PHEMT epitaxial structure described in this embodiment.

[0087] In summary, this invention provides a GaAs-based enhanced / depletion-type PHEMT structure, epitaxial structure, and its fabrication method. By placing an epitaxial insertion layer composed of GaAs and GaP insertion layers between the second AlGaAs barrier layer (enhanced barrier layer) and the InGaP barrier layer (depletion-type barrier layer), and performing growth of the second AlGaAs barrier layer followed by sequential growth of the GaAs and GaP insertion layers, and then growing the InGaP barrier layer, the low-bandgap InGaAs or InGaAsP intermediate layers caused by the As-P exchange process can be effectively avoided. Simultaneously, the epitaxial insertion layer can reduce or even prevent the diffusion of As atoms from the second AlGaAs barrier layer into the InGaP barrier layer, thus reducing the risk of forming a low-bandgap InGaAsP interface layer. This achieves the effect of optimizing the growth interface and barrier layer growth quality of the second AlGaAs and InGaP barrier layers. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0088] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A GaAs-based enhanced / depletion-type PHEMT epitaxial structure, characterized in that, The epitaxial structure includes: Substrate; and The substrate contains, in order from bottom to top, a buffer layer, a first AlGaAs barrier layer, a first AlGaAs isolation layer, an InGaAs channel layer, a second AlGaAs isolation layer, a second AlGaAs barrier layer, an epitaxial insertion layer, an InGaP barrier layer, and a GaAs cap layer. The epitaxial insertion layer includes, from bottom to top, a GaAs insertion layer and a GaP insertion layer; The buffer layer, from bottom to top, includes a GaAs buffer layer and a superlattice buffer layer composed of AlGaAs layers / GaAs layers.

2. The GaAs-based enhanced / depletion-type PHEMT epitaxial structure according to claim 1, characterized in that: The thickness of the GaAs insertion layer is 0.25 nm to 0.35 nm, and the thickness of the GaP insertion layer is 0.3 nm to 0.6 nm.

3. The GaAs-based enhanced / depletion-type PHEMT epitaxial structure according to claim 1, characterized in that: The upper surface of the first AlGaAs barrier layer is doped with silicon δ, and the upper surface of the second AlGaAs isolation layer is doped with silicon δ, wherein the doping concentration of the second silicon δ doping is 2.9 to 3.1 times that of the first silicon δ doping. The upper and lower surfaces of the InGaAs channel layer are pre-set to a GaAs growth transition layer thickness, and the composition of the remaining thickness of the InGaAs channel layer is denoted as In. x Ga 1-x In the As layer, the value of the In component x is 0.25 < x < 0.3, and the In... x Ga 1- x The As layer underwent silicon doping with gradually increasing doping concentration from bottom to top.

4. The GaAs-based enhanced / depletion-type PHEMT epitaxial structure according to claim 3, characterized in that: The InGaAs channel layer in the InGaAs x Ga 1-x The thickness of the As layer is 8 nm to 10 nm, and the thickness of the GaAs growth transition layer is 0.9 nm to 1.1 nm; the In... x Ga 1-x The silicon doping concentration in the As layer is 2E17cm⁻¹ -3 Gradient to 4E17cm -3 .

5. The GaAs-based enhanced / depletion-type PHEMT epitaxial structure according to claim 4, characterized in that: The doping concentration of the first silicon δ-doped silicon is 1.4E12cm. -2 ~1.6E12cm -2 The doping concentration of the second silicon δ-doped silicon is 4.2E12cm⁻¹. -2 ~4.8E12cm -2 .

6. The GaAs-based enhanced / depletion-type PHEMT epitaxial structure according to claim 1, characterized in that: The GaAs cap layer is a silicon-doped GaAs cap layer, and the silicon doping concentration is 0.5E19cm⁻¹. -3 ~1.0E19cm -3 .

7. The GaAs-based enhanced / depletion-type PHEMT epitaxial structure according to any one of claims 1 to 6, characterized in that: The thickness of the GaAs buffer layer is 100nm~200nm; the single-layer thickness of the AlGaAs layer in the superlattice buffer layer is 9nm~11nm, and the single-layer thickness of the GaAs layer is 1.3nm~1.7nm; the thickness of the first AlGaAs barrier layer is 30nm~40nm; the thickness of the first AlGaAs isolation layer is 5nm~10nm; the thickness of the second AlGaAs isolation layer is 5nm~10nm; the thickness of the second AlGaAs barrier layer is 6nm~10nm; the thickness of the InGaP barrier layer is 30nm~35nm; and the thickness of the GaAs cap layer is 48nm~52nm.

8. A method for preparing a GaAs-based reinforced / depletion-type PHEMT epitaxial structure, characterized in that, The preparation method includes the following steps: S1: Provides a substrate; S2: A GaAs buffer layer and a superlattice buffer layer composed of AlGaAs layer / GaAs layer are sequentially grown on the substrate at a growth temperature of 580℃~600℃. S3: Grow a first AlGaAs barrier layer on the superlattice buffer layer; S4: Grow a first AlGaAs isolation layer on the first AlGaAs barrier layer; S5: An InGaAs channel layer is grown on the first AlGaAs isolation layer at a growth temperature of 480℃~500℃; S6: Heat to 580℃~600℃ to grow a second AlGaAs isolation layer on the InGaAs channel layer; S7: A second AlGaAs barrier layer and a GaAs insertion layer are sequentially grown on the second AlGaAs isolation layer; S8: Reduce the temperature to 500℃~520℃, and sequentially grow a GaP insertion layer and an InGaP barrier layer on the GaAs insertion layer. S9: Grow a GaAs cap layer on the InGaP barrier layer.

9. The method for preparing the GaAs-based enhanced / depletion-type PHEMT epitaxial structure according to claim 8, characterized in that: In step S4, the upper surface of the first AlGaAs barrier layer is first subjected to silicon δ-doping before the first AlGaAs isolation layer is grown; in step S5, the upper and lower surfaces of the InGaAs channel layer formed are pre-defined as GaAs growth transition layers, and the composition of the InGaAs channel layer with the remaining thickness is denoted as In. x Ga 1-x In the As layer, the value of the In component x is 0.25 < x < 0.3, and the In... x Ga 1-x The As layer undergoes silicon doping with gradually increasing doping concentration from bottom to top; after the second AlGaAs isolation layer is formed in step S6, its upper surface is subjected to second silicon δ doping.

10. A GaAs-based enhanced / depletion-type PHEMT structure, characterized in that: The PHEMT structure is prepared based on the GaAs-based enhanced / depleted PHEMT epitaxial structure described in any one of claims 1 to 7.

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