A field effect transistor and a method of manufacturing the same

Abstract

The application provides a field effect transistor and a manufacturing method thereof, and comprises the following steps: forming a bottom dielectric isolation layer of the field effect transistor by bonding a first bonding layer and a second bonding layer; arranging a top source, a top drain, a top channel structure, a bottom source, a bottom drain and a bottom channel structure on one side of the bottom dielectric isolation layer, wherein the top channel structure and the bottom channel structure are connected by an intermediate dielectric layer, the top channel structure and the bottom channel structure comprise a plurality of nanosheet stacks, and a gate is arranged around the nanosheet. The insulating dielectric layer at the bottom of the channel structure is formed by bonding the first bonding layer and the second bonding layer, and the intermediate dielectric layer is used as the insulating dielectric layer between the top channel structure and the bottom channel structure, so that the problem of the substrate parasitic leakage of the field effect transistor under the short channel is avoided, and the performance of the field effect transistor is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a complementary field-effect transistor and a method for manufacturing the same. Background Technology

[0002] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink. Traditional triple-gate or double-gate Fin Field-Effect Transistors (FinFETs) are limited below the 3-nanometer (nm) node. Nanosheet-Gate all-round Fin Field-Effect Transistors (Nanosheet-GAAFETs) have been developed to alleviate the 3nm node limitation. Furthermore, Complementary Field-Effect Transistors (CFETs) have received widespread attention and research due to their breakthrough of the 1nm node limitation.

[0003] Current field-effect transistors suffer from parasitic leakage current in the bottom substrate under short-channel conditions. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a field-effect transistor and a method for manufacturing the same, which can avoid the parasitic leakage problem of field-effect transistors in short-channel conditions and improve the performance of complementary field-effect transistors.

[0005] This application provides a field-effect transistor, the field-effect transistor comprising:

[0006] A bottom dielectric isolation layer, the bottom dielectric isolation layer comprising a first bonding layer and a second bonding layer;

[0007] A top source, a top drain, a top channel structure, a bottom source, a bottom drain, and a bottom channel structure are disposed on the bottom dielectric isolation layer. In a direction perpendicular to the plane of the bottom dielectric isolation layer, the top channel structure and the bottom channel structure overlap and are isolated from each other by an intermediate dielectric layer. The top channel structure is located between the top source and the top drain, and the bottom channel structure is located between the bottom source and the bottom drain. The top channel structure and the bottom channel structure comprise a stack of multiple nanosheets.

[0008] A gate, which surrounds the nanosheet.

[0009] The thickness of the first bonding layer is greater than the thickness of the second bonding layer, and the thickness of the first bonding layer is greater than the thickness of the intermediate dielectric layer.

[0010] Optionally, the thickness of the first bonding layer and the second bonding layer ranges from 1 to 1000 nm.

[0011] Optionally, the first substrate is a silicon substrate, a germanium substrate, or a germanium-silicon substrate, and the semiconductor-on-insulator substrate is a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a germanium-silicon-on-insulator substrate.

[0012] Optionally, the material of the first bonding layer or the second bonding layer is SiO2 or SiN. x One or more of SiNO, SiCO, SiCNO and SiCN.

[0013] Optionally, the thickness of the intermediate dielectric layer ranges from 1 to 100 nm.

[0014] Optionally, the top channel structure and the bottom channel structure are N-type and P-type, respectively; or P-type and N-type.

[0015] Optionally, the intermediate dielectric layer includes a first portion located at the center and a second portion located on both sides of the first portion, wherein the second portion extends along both sides of the surface of the first portion in a direction perpendicular to the surface of the bottom dielectric isolation layer, and the thickness of the second portion is greater than the thickness of the first portion.

[0016] Optionally, a contact interface is included between the first part and the second part.

[0017] This application provides a method for manufacturing a field-effect transistor, the method comprising:

[0018] A first substrate is provided, and a first bonding layer is formed on the first substrate;

[0019] A semiconductor-on-insulator substrate is provided, the semiconductor-on-insulator substrate comprising a bottom semiconductor substrate, a buried oxide layer and a top semiconductor substrate stacked thereon, a first stacked structure and a second bonding layer formed on the semiconductor-on-insulator substrate; the first stacked structure is obtained by alternately stacking a plurality of first semiconductor layers and a plurality of second semiconductor layers;

[0020] The first substrate and the semiconductor-on-insulator substrate are bonded together with the second bonding layer in a direction toward the first bonding layer;

[0021] A second stacked structure is formed on the underlying semiconductor substrate, the second stacked structure being obtained by alternating layers of a plurality of first semiconductor layers and a plurality of second semiconductor layers;

[0022] The first stacked structure and the second stacked structure are processed to form a field-effect transistor.

[0023] The process of forming a field-effect transistor by processing the first stacked structure and the second stacked structure includes:

[0024] The first stacked structure and the second stacked structure are processed to form a nanowire stacked structure, the nanowire stacked structure including a bottom structure located below the buried oxide layer and a top structure located above the buried oxide layer;

[0025] A bottom source and a bottom drain are formed on both sides of the bottom structure; a top source and a top drain are formed on both sides of the top structure.

[0026] The second semiconductor layer is removed to form a plurality of gaps to be filled, and a gate is filled in the plurality of gaps to be filled. The plurality of first semiconductor layers surrounding the gate form a channel structure, the channel structure including a top channel structure and a bottom channel structure, the top channel structure and the bottom channel structure being separated by the buried oxide layer.

[0027] Optionally, before forming the bottom source and bottom drain on both sides of the bottom structure, the method further includes:

[0028] The first semiconductor layer located in the top structure and the bottom structure is selectively etched to form a concave structure;

[0029] An inner wall is formed in the concave structure.

[0030] Optionally, forming an inner wall in the concave structure includes:

[0031] Inner sidewalls are formed on both sides of the surface of the buried oxygen layer in a direction perpendicular to the surface of the bottom medium isolation layer, and the inner sidewalls and the buried oxygen layer constitute an intermediate medium layer.

[0032] Optionally, after forming the bottom source and bottom drain on both sides of the bottom structure and before forming the top source and top drain on both sides of the top structure, the method further includes:

[0033] A first dielectric layer is formed between the bottom source and bottom drain on both sides of the bottom structure and the top source and top drain on both sides of the top structure.

[0034] Optionally, before filling the gate in the plurality of gaps to be filled, the method further includes:

[0035] A second work function layer is formed in multiple gaps to be filled in the bottom structure;

[0036] The first work function layer is formed in multiple gaps to be filled in the top structure.

[0037] Optionally, before forming the second stacked structure on the underlying semiconductor substrate, the method further includes:

[0038] The underlying semiconductor substrate is thinned to a thickness equal to that of the first semiconductor layer or the second semiconductor layer.

[0039] This application provides a field-effect transistor (FET), comprising: a bottom dielectric isolation layer, which includes a first bonding layer and a second bonding layer. Specifically, the bottom dielectric isolation layer is formed by bonding the first and second bonding layers together, thereby creating an insulating dielectric under the subsequently formed channel structure. This insulating dielectric avoids substrate parasitic leakage problems that exist in short-channel FETs. A top source, a top drain, a top channel structure, a bottom source, a bottom drain, and a bottom channel structure are disposed on one side of the bottom dielectric isolation layer. The top channel structure and the bottom channel structure are isolated by an intermediate dielectric layer and overlap in a direction perpendicular to the plane of the bottom dielectric isolation layer. The top channel structure is located at the top source and the top drain. Between the bottom and bottom channels, the bottom channel structure is located between the bottom source and bottom drain. The top and bottom channels consist of a stack of multiple nanosheets, with the gate surrounding the nanosheets. This allows the use of a buried oxide layer as the insulating medium between the top and bottom channels, greatly reducing the process complexity of forming the insulating layer between them. In other words, the insulating medium at the bottom of the channel structure is formed by bonding the first and second bonding layers, while the insulating medium between the top and bottom channels is formed by using an intermediate dielectric layer. This not only avoids the substrate parasitic leakage problem that exists in short-channel field-effect transistors, but also reduces the process complexity of forming the insulating medium between the top and bottom channels, ultimately improving the performance of the manufactured field-effect transistors. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A three-dimensional structural schematic diagram of a field-effect transistor provided in an embodiment of this application is shown;

[0042] Figure 2 and Figure 3 Provided for the embodiments of this application Figure 1 The diagram shows the cross-sectional structure of the field-effect transistor in the XX and YY directions.

[0043] Figure 4 A schematic flowchart of a method for manufacturing a field-effect transistor according to an embodiment of this application is shown;

[0044] Figure 5-2 Figure 0 shows a schematic diagram of the structure of a field-effect transistor manufactured according to the manufacturing method of the field-effect transistor provided in the embodiments of this application. Detailed Implementation

[0045] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0046] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0047] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0048] Current field-effect transistors (FETs) suffer from substrate parasitic leakage current in short-channel conditions. During the manufacturing process of FETs, heavily doped wells can be formed in the substrate to suppress the parasitic leakage current problem in short-channel conditions. However, even heavily doped wells cannot completely eliminate parasitic leakage current.

[0049] Furthermore, in the manufacturing process of field-effect transistors, an intermediate isolation layer needs to be formed between the top-channel and bottom-channel structures. This intermediate isolation layer acts as an insulating medium to separate the top-channel and bottom-channel structures. The formation process of the intermediate isolation layer involves first forming a stacked structure of silicon-germanium (SiGe) layers with different germanium contents and silicon (Si) layers, alternating between them. The SiGe layer in the middle region of the stacked structure has the highest Ge content. The high-Ge content SiGe layer is selectively removed to form gaps, and then some insulating medium is filled into these gaps to form the intermediate isolation layer. However, this method has extremely high requirements for material selectivity and insulating medium filling, resulting in a high degree of process complexity.

[0050] Therefore, there is a current need to reduce the process complexity of field-effect transistors and improve their performance.

[0051] Based on this, this application provides a field-effect transistor, including: a bottom dielectric isolation layer, which includes a first bonding layer and a second bonding layer. That is, the bottom dielectric isolation layer at the bottom of the field-effect transistor is formed by bonding the first bonding layer and the second bonding layer, thereby enabling the placement of an insulating dielectric under the subsequently formed channel structure. This insulating dielectric can avoid the substrate parasitic leakage problem that exists in short channels of the field-effect transistor; a top source, a top drain, a top channel structure, a bottom source, a bottom drain, and a bottom channel structure disposed on one side of the bottom dielectric isolation layer. The top channel structure and the bottom channel structure are isolated by an intermediate dielectric layer, and the top channel structure and the bottom channel structure overlap in a direction perpendicular to the plane of the bottom dielectric isolation layer; the top channel structure is located between the top source and the top... Between the drain and the bottom channel structure, the bottom channel structure is located between the bottom source and the bottom drain. The top and bottom channel structures consist of a stack of multiple nanosheets, with the gate surrounding the nanosheets. This allows the use of a buried oxide layer as the insulating medium between the top and bottom channel structures, greatly reducing the process complexity of forming the insulating layer between them. In other words, the insulating medium at the bottom of the channel structure is formed by bonding the first and second bonding layers, and the insulating medium between the top and bottom channel structures is formed by using an intermediate dielectric layer. This not only avoids the substrate parasitic leakage problem that exists in short-channel field-effect transistors, but also reduces the process complexity of forming the insulating medium between the top and bottom channel structures, ultimately improving the performance of the manufactured field-effect transistors.

[0052] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0053] See Figure 1 This figure is a three-dimensional structural schematic diagram of a field-effect transistor provided in an embodiment of this application. Figure 2 and Figure 3 They are respectively for Figure 1 The cross-sections are obtained by performing cross-sections in the XX and YY directions. The field-effect transistor provided in this application embodiment includes a bottom dielectric isolation layer (BDI) 200, a top source 133, a top drain 134, a top channel structure, a bottom source 131, a bottom drain 132, a bottom channel structure, and a gate 160.

[0054] In the embodiments of this application, the bottom dielectric isolation layer 200 includes a first bonding layer 210 and a second bonding layer 220. The bottom dielectric isolation layer 200 is formed by bonding the first substrate 110 and the semiconductor-on-insulator substrate 310 with the first bonding layer 210 and the second bonding layer 220.

[0055] Specifically, a first bonding layer 210 is formed on the first substrate 110, and a first stacked structure and a second bonding layer 220 are formed on the semiconductor-on-insulator substrate 310. The first stacked structure is formed by alternately stacking multiple first semiconductor layers 121 and multiple second semiconductor layers 122. The semiconductor-on-insulator substrate 310 includes a bottom semiconductor substrate 311, a buried oxide layer 123, and a top semiconductor substrate 312 stacked together. The first substrate 110 and the semiconductor-on-insulator substrate 310 are bonded with the second bonding layer 220 facing the first bonding layer 210, and the first bonding layer 210 and the second bonding layer 220 are in direct contact to form a bottom dielectric isolation layer 200. After bonding, the bottom dielectric isolation layer 200 is formed as the bottom substrate of the field-effect transistor, overcoming the parasitic leakage problem of the bottom heavily doped well (GP Well) in traditional bulk silicon field-effect transistors.

[0056] As one possible implementation, the thickness of the first bonding layer 210 is greater than the thickness of the second bonding layer 220, that is, the thicker first bonding layer 210 and the thinner second bonding layer 220 are used for bonding to construct the bottom dielectric isolation layer 200.

[0057] As one possible implementation, the thickness of the first bonding layer 210 and the second bonding layer 220 is in the range of 1-1000 nm, that is, the thickness of the bottom dielectric isolation layer 200 is in the range of 1-1000 nm, thereby realizing the control of parasitic leakage current problem by controlling the thickness of the bottom dielectric isolation layer 200.

[0058] As one possible implementation, the first bonding layer 210 or the second bonding layer 220 is made of an insulating material, thereby suppressing parasitic leakage current. The material of the first bonding layer 210 or the second bonding layer 220 is SiO2 or SiN. x One or more of SiNO, SiCO, SiCNO and SiCN.

[0059] In one possible implementation, the first substrate 110 is a silicon substrate, a germanium substrate, or a germanium-silicon substrate, and the semiconductor-on-insulator substrate 310 is a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a germanium-silicon-on-insulator substrate. That is, the bottom semiconductor substrate 311 and the top semiconductor substrate 312 are made of silicon, germanium, or germanium-silicon.

[0060] A top source 133, a top drain 134, a top channel structure, a bottom source 131, a bottom drain 132, and a bottom channel structure are disposed on one side of the bottom dielectric isolation layer 200. The top and bottom channel structures comprise stacks of multiple nanosheets, obtained by removing the second semiconductor layer 122 from a plurality of alternately stacked first semiconductor layers 121 and a plurality of second semiconductor layers 122. The top and bottom channel structures overlap in a direction perpendicular to the plane of the bottom dielectric isolation layer 200.

[0061] In embodiments of this application, the top channel structure and the bottom channel structure may have different conductivity types to form a complementary field-effect transistor, for example, the top channel structure and the bottom channel structure may have N-type and P-type conductivity types, respectively; or P-type and N-type conductivity types.

[0062] Specifically, depending on the device type, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be the same. For example, for P-type semiconductor devices and N-type semiconductor devices, the material of the first semiconductor layer 121 can be silicon-germanium, and the material of the second semiconductor layer 122 can be silicon or germanium. Alternatively, depending on the device type, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be different. For example, for P-type semiconductor devices, the material of the first semiconductor layer 121 can be silicon, and the material of the second semiconductor layer 122 can be silicon-germanium. For N-type semiconductor devices, the material of the first semiconductor layer 121 can be silicon-germanium, and the material of the second semiconductor layer 122 can be silicon.

[0063] As an example, a complementary field-effect transistor includes a top N-type field-effect transistor and a bottom P-type field-effect transistor. The first semiconductor layer 121 of the top N-type field-effect transistor and the bottom P-type field-effect transistor are made of the same material, and the second semiconductor layer 122 is also made of the same material. The first semiconductor layer 121 can be made of silicon-germanium, wherein the proportion of germanium is 30%, and the second semiconductor layer 122 can be made of silicon.

[0064] In the direction parallel to the surface of the bottom dielectric isolation layer 200, the top channel structure is located between the top source 133 and the top drain 134, and the bottom channel structure is located between the bottom source 131 and the bottom drain 132.

[0065] In the direction perpendicular to the plane where the bottom dielectric isolation layer 200 is located, there is an intermediate dielectric layer between the top channel structure and the bottom channel structure. That is, the intermediate dielectric layer isolates the top channel structure and the bottom channel structure, thereby forming a separation between the upper and lower transistors of the field-effect transistor.

[0066] As one possible implementation, the thickness of the first bonding layer 210 is greater than the thickness of the intermediate dielectric layer.

[0067] In embodiments of this application, the intermediate dielectric layer includes a first portion located at the center and second portions located on both sides of the first portion, wherein the second portions extend along both sides of the surface of the first portion in a direction perpendicular to the surface of the bottom dielectric isolation layer 200, and the thickness of the second portion is greater than the thickness of the first portion. That is, the intermediate dielectric layer has an H-shaped structure.

[0068] Specifically, the first part and the second part include a contact interface, meaning that the first part and the second part are not formed simultaneously, and the first part and the second part are in contact using the contact interface. The first part is the buried oxide layer 123, and the second part is the inner wall 206 that is in contact with the buried oxide layer 123.

[0069] Specifically, the embedded oxide layer 123 is made of insulating material, and its thickness ranges from 1 to 100 nm. The material of the embedded oxide layer 123 may be the same as or different from the material of the inner sidewall 206.

[0070] As one possible implementation, in a direction perpendicular to the plane where the bottom dielectric isolation layer 200 is located, the top source 133 and the bottom source 131 overlap, and the top drain 134 and the bottom drain 132 overlap.

[0071] In the embodiments of this application, there is a gap between the multiple nanosheets in the top channel structure and the bottom channel structure, and the gap is filled with a gate 160, that is, the gate 160 surrounds the nanosheets to form a ring gate structure.

[0072] In the embodiments of this application, an inner wall 206 is provided between adjacent nanosheets. The material of the inner wall 206 can be one or more of silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, silicon oxycarbide, boron nitride, and low-k materials.

[0073] An interface layer, a high-k dielectric layer, and a work function layer can also be disposed between the gate 160 and the nanosheet. Specifically, the interface layer surrounds the nanosheet, the high-k dielectric layer surrounds the interface layer, and the work function layer surrounds the high-k dielectric layer. The interface layer can be made of silicon oxide. The high-k dielectric layer can be made of HfO2 or HfSiO2. x , HfON, HfSiON, HfAlOx, HfLaO x Al2O3, ZrO2, ZrSiO x One or a combination of Ta2O5 or La2O3.

[0074] Different types of field-effect transistors (FETs) can be implemented using different types of work function layers. These different types of work function layers include a first type work function layer 710 and a second type work function layer 720. The first type work function layer 710 is one of a P-type work function layer (P-WFL) or an N-type work function layer (N-WFL), and the second type work function layer 720 is the other of a P-type work function layer or an N-type work function layer.

[0075] As an example, the work function layer of the top N-type field-effect transistor is a first type work function layer 710, and the work function layer of the bottom P-type field-effect transistor is a second type work function layer 720. The first type work function layer 710 is an N-type work function layer, and the second type work function layer 720 is a P-type work function layer.

[0076] In embodiments of this application, the bottom dielectric isolation layer 200 includes a back contact 610, which connects to the bottom source 131 or the bottom drain 132, thereby enabling electrical lead-out of the field-effect transistor. The back contact 610 is made of a metallic material. Since the bottom dielectric isolation layer 200 can achieve isolation between adjacent fins, it eliminates the need for shallow trench isolation in the field-effect transistor, thus simplifying the manufacturing process.

[0077] In embodiments of this application, the semiconductor device further includes a second sidewall 205, an isolation layer 207, a top dielectric layer 171, a bottom dielectric layer 172, and a contact electrode 620. The second sidewall 205 is disposed on the side of the top channel structure away from the bottom dielectric isolation layer 200, and a gate 160 is located between the second sidewalls 205. The isolation layer 207 is disposed on the side of the bottom source 131 or bottom drain 132 away from the bottom dielectric isolation layer 200, and the second sidewall 205 and gate 160 are located between the isolation layers 207. The top dielectric layer 171 covers the isolation layer 207, the second sidewall 205, and the gate 160, and a contact electrode 620 is located in the top dielectric layer 171 and the isolation layer 207 for electrically leading out the bottom source 131 or bottom drain 132. The bottom dielectric layer 172 covers the surface of the bottom dielectric isolation layer 200 away from the bottom channel structure, and a back contact 610 is located in the bottom dielectric layer 172.

[0078] Therefore, the field-effect transistor provided in this application includes: a bottom dielectric isolation layer, which is formed by bonding a first substrate and a semiconductor-on-insulator substrate using a first bonding layer and a second bonding layer. In other words, the bottom dielectric isolation layer of the field-effect transistor is formed by bonding the first bonding layer and the second bonding layer, thereby enabling the placement of an insulating dielectric under the subsequently formed channel structure. This insulating dielectric can avoid the parasitic leakage problem that exists in short channels of the field-effect transistor. The semiconductor-on-insulator substrate includes a buried oxide layer, meaning that the buried oxide layer can be used as the top channel structure. The insulating medium between the top and bottom channel structures greatly reduces the process complexity of forming the insulating layer between the top and bottom channel structures. In other words, the insulating medium at the bottom of the channel structure is formed by bonding the first and second bonding layers, and the intermediate dielectric layer between the top and bottom channel structures is formed by including a buried oxide layer in the semiconductor-on-insulator substrate. This not only avoids the substrate parasitic leakage problem that exists in short-channel field-effect transistors, but also reduces the process complexity of forming the insulating medium between the top and bottom channel structures, ultimately improving the performance of the manufactured field-effect transistors.

[0079] Based on the field-effect transistor provided in the above embodiments, this application also provides a method for manufacturing a field-effect transistor, and its working principle will be described in detail below with reference to the accompanying drawings.

[0080] See Figure 4 The figure is a schematic flowchart of a method for manufacturing a field-effect transistor according to an embodiment of this application.

[0081] The method for manufacturing a field-effect transistor provided in this application includes the following steps:

[0082] S101, a first substrate is provided, and a first bonding layer is formed on the first substrate.

[0083] S102, a semiconductor-on-insulator substrate is provided, the semiconductor-on-insulator substrate includes a bottom semiconductor substrate, a buried oxide layer and a top semiconductor substrate stacked together, and a first stacked structure and a second bonding layer are formed on the semiconductor-on-insulator substrate; the first stacked structure is obtained by alternately stacking a plurality of first semiconductor layers and a plurality of second semiconductor layers.

[0084] In embodiments of this application, a first substrate 110 and a semiconductor-on-insulator substrate 310 are provided, and a first bonding layer 210 is formed on the first substrate 110, as referenced. Figure 5 As shown. A first stacked structure and a second bonding layer 220 are formed on a semiconductor-on-insulator substrate 310, as referenced. Figure 6As shown, the first stacked structure is obtained by alternating layers of a plurality of first semiconductor layers 121 and a plurality of second semiconductor layers 122. The semiconductor-on-insulator substrate 310 includes a bottom semiconductor substrate 311, a buried oxide layer 123 and a top semiconductor substrate 312 stacked together.

[0085] In one possible implementation, the first substrate 110 is a silicon substrate, a germanium substrate, or a silicon-germanium substrate, and the semiconductor-on-insulator substrate 310 is a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a silicon-germanium-on-insulator substrate. That is, the bottom semiconductor substrate 311 and the top semiconductor substrate 312 are made of silicon, germanium, or silicon-germanium.

[0086] S103, the first substrate and the semiconductor-on-insulator substrate are bonded in the direction of the second bonding layer toward the first bonding layer.

[0087] In the embodiments of this application, the first substrate 110 and the semiconductor-on-insulator substrate 310 are bonded with the second bonding layer 220 facing the first bonding layer 210. The first bonding layer 210 and the second bonding layer 220 are in direct contact to form a bottom dielectric isolation layer 200. (Reference) Figure 7 As shown, a bottom dielectric isolation layer 200 is formed as the bottom substrate of the field-effect transistor, overcoming the parasitic leakage problem of the bottom heavily doped well (GP Well) in traditional bulk silicon field-effect transistors.

[0088] As one possible implementation, the thickness of the first bonding layer 210 is greater than the thickness of the second bonding layer 220, that is, the thicker first bonding layer 210 and the thinner second bonding layer 220 are used for bonding to construct the bottom dielectric isolation layer 200.

[0089] As one possible implementation, the thickness of the first bonding layer 210 and the second bonding layer 220 is in the range of 1-1000 nm, that is, the thickness of the bottom dielectric isolation layer 200 is in the range of 1-1000 nm, thereby realizing the control of substrate parasitic leakage current problem by controlling the thickness of the bottom dielectric isolation layer 200.

[0090] As one possible implementation, the first bonding layer 210 or the second bonding layer 220 is made of an insulating material, thereby suppressing parasitic leakage current. The material of the first bonding layer 210 or the second bonding layer 220 is SiO2 or SiN. x One or more of SiNO, SiCO, SiCNO and SiCN.

[0091] In the embodiments of this application, the bottom semiconductor substrate 311 is first polished using a chemical mechanical polishing (CMP) process, and then a high-temperature sacrificial oxidation and oxide layer removal method is introduced until the bottom semiconductor substrate 311 is thinned to a thickness equal to that of the first semiconductor layer 121 or the second semiconductor layer 122.

[0092] As an example, the underlying semiconductor substrate 311 is thinned to a thickness equal to that of the second semiconductor layer 122, with reference to... Figure 7 As shown.

[0093] S104, a second stacked structure is formed on the bottom semiconductor substrate. The second stacked structure is obtained by alternately stacking multiple first semiconductor layers and multiple second semiconductor layers.

[0094] In embodiments of this application, after bonding the first substrate 110 and the semiconductor-on-insulator substrate 310, and thinning the bottom semiconductor substrate 311, a second stacked structure can be formed on the bottom semiconductor substrate 311. (Refer to...) Figure 8 As shown, the second stacked structure is formed by alternating layers of multiple first semiconductor layers 121 and multiple second semiconductor layers 122. The second stacked structure includes a bottom semiconductor substrate 311.

[0095] Specifically, depending on the device type, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be the same. For example, the material of the first semiconductor layer 121 can be silicon-germanium, and the material of the second semiconductor layer 122 can be silicon or germanium. Alternatively, depending on the device type, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be different. For example, for a P-type semiconductor device, the material of the first semiconductor layer 121 can be silicon, and the material of the second semiconductor layer 122 can be silicon-germanium. For an N-type semiconductor device, the material of the first semiconductor layer 121 can be silicon-germanium, and the material of the second semiconductor layer 122 can be silicon.

[0096] In the direction perpendicular to the plane where the bottom dielectric isolation layer 200 is located, there is a buried oxide layer 123 between the first stacked structure and the second stacked structure. That is, the first stacked structure and the second stacked structure are separated by the buried oxide layer 123, thereby forming a separation between the upper and lower transistors of the field-effect transistor.

[0097] Specifically, the material of the buried oxide layer 123 is an insulating material, and the thickness of the buried oxide layer ranges from 1 to 100 nm.

[0098] S105, the first stacked structure, the buried oxide layer and the second stacked structure are etched down to the second bonding layer to form a fin structure. The fin structure includes a top structure and a bottom structure, which are separated by the buried oxide layer.

[0099] In the embodiments of this application, the first stacked structure, the buried oxide layer 123, and the second stacked structure can be etched down to the second bonding layer 220 to form a fin structure. The fin structure includes a top structure and a bottom structure, which are separated by the buried oxide layer 123. The process flow for forming the fin structure is described in detail below.

[0100] S1051, Sidewall Transfer Process, Reference Figure 9A and Figure 9B As shown, Figure 9A and Figure 9B They are respectively for Figure 1 The cross-sections are obtained by performing cross-sections in the XX and YY directions.

[0101] In the embodiments of this application, a self-aligned sidewall transfer process is used to form the first sidewall 201. The material of the first sidewall 201 is silicon nitride. The specific formation process is as follows: a sacrificial layer 202 is covered on the second stacked structure. The material of the sacrificial layer 202 can be polycrystalline silicon or amorphous silicon. Part of the sacrificial layer 202 is etched away using photolithography to form a pattern, and silicon nitride material is deposited. Then, anisotropic etching is used to etch away the remaining sacrificial layer 202, so that only the first sidewall 201 on the stacked structure remains. The first sidewall 201 plays the role of a hard mask in the subsequent photolithography for forming fins.

[0102] S1052, forming a fin structure, reference. Figure 10A and Figure 10B As shown, Figure 10A and Figure 10B They are respectively for Figure 1 The cross-sections are obtained by performing cross-sections in the XX and YY directions.

[0103] In the embodiments of this application, the first stacked structure, the buried oxide layer 123, and the second stacked structure can be etched using an etching process to form multiple periodically distributed fins, as shown in the reference. Figure 10A and Figure 10B As shown. Etching is performed using the first sidewall 201 as a mask to form fins with a layered structure. The fin structure includes a top structure 510 and a bottom structure 520, separated by a buried oxide layer 123. The top structure 510 and bottom structure 520 form a channel region, creating a structure as shown. Figure 10B The fins are shown. The etching process can be dry etching or wet etching; in one embodiment, reactive ion etching may be used. The fin structure will be used to form nanosheets for field-effect transistors. Although Figure 10B A fin is shown, and it should be understood that any suitable number and shape of fins can be used in practical applications.

[0104] In practical applications, the first sidewall 201 can be removed after the fin structure is formed.

[0105] Since the bottom dielectric isolation layer 200 can achieve isolation between adjacent fins, there is no need to set shallow trench isolation in the field-effect transistor, thus simplifying the process flow.

[0106] S106, the first stacked structure and the second stacked structure are processed to form a field-effect transistor.

[0107] In the embodiments of this application, after forming the first stacked structure and the second stacked structure, the first stacked structure and the second stacked structure can be further processed to finally form a field-effect transistor.

[0108] Specifically, the first and second layered structures can be processed to form a nanowire stacked structure, which includes a bottom structure 520 located below the buried oxide layer 123 and a top structure 510 located above the buried oxide layer 123. The specific process is described in detail below.

[0109] S1061, forming a false gate 204 and a second sidewall 205, reference Figure 11A and Figure 11B As shown, Figure 11A and Figure 11B They are respectively for Figure 1 The cross-sections are obtained by performing cross-sections in the XX and YY directions.

[0110] In embodiments of this application, a dummy gate stack is formed on the exposed fin structure. The dummy gate stack is a multilayer structure, including a gate insulating dielectric layer (not shown), a dummy gate 204, and a hard mask layer (not shown). The dummy gate stack can be formed using processes such as thermal oxidation, chemical vapor deposition, or sputtering. The dummy gate stack spans the stack structure above the fin structure, with multiple dummy gates periodically distributed along the fin direction. The material of the dummy gate 204 can be polycrystalline silicon or amorphous silicon. The material of the hard mask layer can be oxides, carbides, organic materials, etc.

[0111] In embodiments of this application, second sidewalls 205 can be provided on both sides of the dummy gate stack, and the thickness of the second sidewalls 205 on both sides is the same. The material of the second sidewalls 205 can be a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.

[0112] S1062, etching the top structure, buried oxide layer, and bottom structure to form the top source region, top drain region, bottom source region, and bottom drain region. (Reference) Figure 12 As shown, Figure 12 To Figure 1 Obtained by performing a cross-section in the XX direction.

[0113] In the embodiments of this application, after forming the dummy gate 204 and the second sidewall 205, the dummy gate 204 and the second sidewall 205 can be used as masks to perform source and drain etching on the stacked structure through an etching process. Specifically, source and drain etching is performed on the top structure, the buried oxide layer 123, and the bottom structure to form a top source region 1101, a top drain region 1102, a bottom source region 1201, and a bottom drain region 1202. The top source region 1101 and the top drain region 1102 form a top channel region, and the bottom source region 1201 and the bottom drain region 1202 form a bottom channel region. After etching, the top source region 1101, the top drain region 1102, the bottom source region 1201, and the bottom drain region 1202 no longer have a stacked structure. (Refer to...) Figure 12 As shown.

[0114] S1063, forming a concave structure, reference. Figure 13 As shown, Figure 13 To Figure 1 Obtained by performing a cross-section in the XX direction.

[0115] In the embodiments of this application, the second semiconductor layer 122 located in the top structure 510 and the bottom structure 520 is laterally etched, that is, a portion of the second semiconductor layer 122 is etched away from the sidewalls of the top structure 510 and the bottom structure 520, without damaging the first semiconductor layer 121. The portion of the second semiconductor layer 122 missing from the first semiconductor layer 121 forms a concave structure, that is, pull-back etching is performed, etching away portions of the second semiconductor layer 122 from the bottom source region 1201 and the bottom drain region 1202 towards the bottom channel region, and from the top source region 1101 and the top drain region 1102 towards the top channel region, as referenced. Figure 13 As shown.

[0116] While selectively etching the second semiconductor layer 122 in the top structure 510 and the bottom structure 520, the buried oxide layer 123 is unaffected. The surface of the buried oxide layer 123, the surface of the first semiconductor layer 121 adjacent to the buried oxide layer 123, and the sidewalls of the etched second semiconductor layer 122 in contact with the buried oxide layer 123 also form concave structures.

[0117] S1064, forming the inner wall, see reference. Figure 14 As shown, Figure 14 To Figure 1 Obtained by performing a cross-section in the XX direction.

[0118] In the embodiments of this application, after the second semiconductor layer 122 is etched, dielectric material is deposited on the bottom structure 520 in the bottom channel region and the top structure 510 in the top channel region, i.e., the periphery of the fins. The dielectric material is etched to form inner sidewalls 206. The inner sidewalls 206 are flush with the first semiconductor layer 121 in a direction perpendicular to the plane of the first substrate 110. That is, the concave structure caused by etching S1063 is filled by the inner sidewalls 206. The material of the inner sidewalls 206 can be silicon nitride or silicon oxide.

[0119] When the inner wall 206 is formed in the concave structure, the inner wall 206 is formed on both sides of the surface of the buried oxygen layer 123 in the direction of the vertical bottom medium isolation layer 200. The inner wall 206 and the buried oxygen layer 123 constitute the intermediate medium layer. At this time, the intermediate medium layer has an H-shaped structure.

[0120] Considering that two transistors with different doping types need to be stacked one on top of the other, the source and drain of the two transistors need to be formed separately. The specific process is described in detail below.

[0121] S106a, a bottom source and a bottom drain are formed on both sides of the bottom structure; a top source and a top drain are formed on both sides of the top structure.

[0122] In the embodiments of this application, after etching the stacked structure to form the bottom source region 1201 and the bottom drain region 1202, the bottom source 131 and the bottom drain 132 can be formed in the bottom source region 1201 and the bottom drain region 1202, respectively. That is, the bottom source 131 and the bottom drain 132 are formed on both sides of the bottom structure 520. (Refer to...) Figure 15 As shown, Figure 15 To Figure 1 The cross-section is obtained by performing a cross-section in the XX direction. The surfaces of the bottom source 131 and bottom drain 132 away from the first substrate 110 can be flush with the surface of the buried oxide layer 123 near the first substrate 110.

[0123] Specifically, the source and drain materials may differ for different types of semiconductor devices. For P-type semiconductor devices, the source and drain materials are boron-doped germanium silicon, i.e., SiGe:B. For N-type semiconductor devices, the source and drain materials are carbon-doped silicon, i.e., Si:C.

[0124] In the embodiments of this application, before forming the bottom source 131 and bottom drain 132, target sidewalls 320 are deposited and etched. The target sidewalls 320 are located at least on the sidewalls of the top channel structure, thereby achieving isolation of the top channel structure. Specifically, target sidewalls 320 are respectively provided on both sides of the top channel structure, and the target sidewalls 320 on both sides have the same thickness. The material of the target sidewalls 320 can be a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.

[0125] In the embodiments of this application, after forming the target sidewall 320, a bottom source 131 and a bottom drain 132 can be formed in the bottom source region 1201 and the bottom drain region 1202, respectively. Then, a dielectric material is deposited, and a planarization process is performed to form a first dielectric layer 420. The first dielectric layer 420 covers the top structure 510 and the target sidewall 320. The first dielectric layer 420 can be etched back to the surface of the buried oxide layer 123 away from the first substrate 110, and the target sidewall 320 can also be etched to the surface of the buried oxide layer 123 away from the first substrate 110. That is, both the first dielectric layer 420 and the target sidewall 320 are etched to the buried oxide layer 123, thereby achieving isolation between the source and drain of the two transistors.

[0126] In embodiments of this application, after etching back the first dielectric layer 420 and the target sidewall 320, a top source 133 and a top drain 134 can be formed on the first dielectric layer 420 and the target sidewall 320, that is, a top source 133 and a top drain 134 are formed on both sides of the top structure 510, so as to form the source and drain of the upper transistor in the two stacked transistors, see reference. Figure 15 As shown. The top source 133 and the top drain 134 can be located on the first dielectric layer 420.

[0127] S106b, the second semiconductor layer is removed to form multiple gaps to be filled, and a gate is filled in the multiple gaps to be filled. The multiple first semiconductor layers surrounding the gate constitute a channel structure. The channel structure includes a top channel structure and a bottom channel structure, which are separated by a buried oxide layer.

[0128] In embodiments of this application, the second semiconductor layer 122 in the top and bottom channel regions can be removed, i.e., a nanosheet channel release process can be performed, so as to form a plurality of gaps 402 to be filled between the first semiconductor layer 121, as shown in the reference. Figure 17A and Figure 17B As shown, Figure 17A and Figure 17B They are respectively for Figure 1 The cross-sections are obtained by performing cross-sections in the XX and YY directions. Then, a second type of work function layer 720 is formed in multiple gaps 402 to be filled.

[0129] Specifically, the second semiconductor layer 122 in the stacked structure located in the top and bottom channel regions can be selectively etched to release the nanosheet channel. In other words, the stacked structure exposed by the fins is processed to remove the second semiconductor layer 122 of each layer, which serves as a sacrificial layer, to release the nanosheet formed by the first semiconductor layer 121.

[0130] In the embodiments of this application, before removing the second semiconductor layer 122 of the top channel region and the bottom channel region, the dummy gate 204 can be removed first. The specific process flow is as follows.

[0131] S106c, remove dummy gates, reference. Figure 16A and Figure 16B As shown, Figure 16A and Figure 16B They are respectively for Figure 1 The cross-sections are obtained by performing cross-sections in the XX and YY directions.

[0132] In embodiments of this application, an isolation layer 207 can be deposited on the surfaces of the dummy gate 204, the top source 133, and the top drain 134 to prevent short circuits between the dummy gate 204 and the top source 133 or the top drain 1342 in subsequent steps. The isolation layer 207 is then subjected to a chemical mechanical polishing process to planarize it. Then, as... Figure 16A and Figure 16B As shown, the dummy gate 204 formed by the aforementioned polycrystalline silicon or amorphous silicon is etched or etched away by selective etching or etching processes, that is, the dummy gate 204 is removed.

[0133] In embodiments of this application, after forming a plurality of gaps 402 to be filled, an interface layer can be formed on the surface of the first semiconductor layer 121, and the interface between the interface layer and the first semiconductor layer 121 can be passivated. Specifically, the material of the interface layer can be silicon oxide.

[0134] In embodiments of this application, after forming the interface layer, a high-k dielectric layer can be formed on the surface of the interface layer, with the high-k dielectric layer surrounding the surface of the interface layer. Specifically, the material of the high-k dielectric layer can be HfO2 or HfSiO2. x , HfON, HfSiON, HfAlOx, HfLaO x Al2O3, ZrO2, ZrSiO x One or a combination of Ta2O5 or La2O3.

[0135] To form transistors of different types, it is necessary to use isolation layers to isolate different types of transistors and different types of work function layers to realize different types of transistors. The specific process flow is introduced below.

[0136] S106d forms a second type of work function layer in all the gaps to be filled.

[0137] In embodiments of this application, a second type of work function layer 720 can be formed in all the gaps 402 to be filled, particularly in the multiple gaps 402 to be filled in the bottom structure 520, the second type of work function layer 720 surrounding the surface of the high-k dielectric layer. Specifically, the second type of work function layer 720 is a P-type work function layer (P-WFL).

[0138] S106e, filling the gaps to be filled in the bottom structure with a protective layer.

[0139] In embodiments of this application, an isolation material can be deposited, and then the isolation material can be etched back to the position of the buried oxide layer 123 to form a protective layer. Specifically, the isolation material can be etched back to 1 / 2 of the position of the buried oxide layer 123. The protective layer fills the gaps 402 to be filled in the bottom structure 520.

[0140] S106f, remove the second type of work function layer in the gap to be filled in the top structure, and form a first type of work function layer in the gap to be filled in the top structure.

[0141] In the embodiments of this application, using a protective layer as a mask, the second type of work function layer 720 in the gap 402 to be filled in the top structure 510 is removed, and a first type of work function layer 710 is formed in the gap 402 to be filled in the top structure 510. Thus, a first type of work function layer 710 is formed in the top structure 510, and a second type of work function layer 720 is formed in the bottom structure 520. Specifically, the first type of work function layer 710 is an N-type work function layer (N-WFL). The second type of work function layer 720 in the gap 402 to be filled in the top structure 510 can be removed using an etching process.

[0142] S106g, remove the protective layer.

[0143] In the embodiments of this application, after forming the first type of work function layer 710 and the second type of work function layer 720, the protective layer can be removed.

[0144] In practical applications, the protective layer can be removed first, and then the first type of work function layer 710 can be formed in all the gaps 402 to be filled. That is, the second type of work function layer 720 is formed first in the gaps 402 to be filled in the bottom structure 520, and then the first type of work function layer 710 is formed.

[0145] In the embodiments of this application, after the nanosheet channel is released, there are multiple gaps 402 to be filled between the multiple first semiconductor layers 121. A gate 160 can be filled into these gaps 402. The gate 160 surrounds the first semiconductor layers 121, forming a ring gate structure. Specifically, the gate 160 surrounds a first type work function layer 710 and a second type work function layer 720. The stack of multiple first semiconductor layers 121 forms a top channel structure and a bottom channel structure, i.e., forms the nanosheet channel of a field-effect transistor. (Refer to...) Figure 18A and Figure 18B As shown, Figure 18A and Figure 18B They are respectively for Figure 1 The cross-sections are obtained by performing cross-sections in the XX and YY directions.

[0146] In practical applications, in addition to forming the gate 160 in the gap 402 to be filled, the gate 160 also covers the spacer layer 207 and the space after the dummy gate 204 is removed. The gate 160 covered by the spacer layer 207 can be chemically mechanically polished to perform planarization.

[0147] In embodiments of this application, after forming the gate 160, dielectric deposition can be performed on the top of the field-effect transistor away from the first substrate 110 to form a top dielectric layer 171. Contact hole etching is then performed in the top dielectric layer 171, etching down to the surface of the top source 133 or the top drain 134. Metal material is deposited in the contact holes to form the contact electrodes 620 of the top source 133 or the top drain 134. (Refer to...) Figure 19A and Figure 19B As shown, Figure 19A and Figure 19B They are respectively for Figure 1 The cross-sections are obtained by performing cross-sections in the XX and YY directions.

[0148] In embodiments of this application, the first substrate 110 may also be removed, as shown in the reference. Figure 20A and Figure 20B As shown, Figure 20A and Figure 20B They are respectively for Figure 1 Cross sections are obtained in the XX and YY directions to form a bottom dielectric isolation layer 200 as the bottom substrate of the field-effect transistor, overcoming the parasitic leakage problem of the bottom heavily doped well (GP Well) in traditional bulk silicon field-effect transistors.

[0149] After removing the first substrate 110, dielectric deposition can be performed on the surface of the bottom dielectric isolation layer 200 away from the buried oxide layer 123 to form a bottom dielectric layer 172. Back contact hole etching is then performed in the bottom dielectric layer 172, etching down to the surface of the bottom source 131 or bottom drain 132. Metal material is then deposited in the back contact holes to form the back contact 610 of the bottom source 131 or bottom drain 132. (Refer to...) Figure 2 and Figure 3 As shown. That is, the bottom dielectric isolation layer 200 includes a back contact 610, which is connected to the bottom source 131 or the bottom drain 132, thereby realizing the electrical lead-out of the field-effect transistor. The material of the back contact 610 is a metallic material.

[0150] Therefore, the field-effect transistors provided in this application form a bottom dielectric isolation layer through wafer bonding. This bottom dielectric isolation layer can reduce the volatility of high-Fin etching processes in field-effect transistors and optimize the isolation between back contacts and electrodes. The intermediate dielectric insulating layer of the field-effect transistor is formed using a buried oxide layer in an SOI or GeOI substrate, effectively reducing the complexity of the intermediate dielectric insulating layer formation process and mitigating the Ge diffusion problem in heavily doped SiGe layers. Furthermore, the manufacturing method is compatible with mainstream CFET integrated circuit manufacturing technologies for devices and cell circuits.

[0151] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the structural embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the structural embodiments. The structural embodiments described above are merely illustrative, and those skilled in the art can understand and implement them without creative effort.

[0152] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method of manufacturing a field effect transistor, characterized by, The method comprises: providing a first substrate, forming a first bonding layer on the first substrate; providing a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a bottom semiconductor substrate, a buried oxide layer and a top semiconductor substrate stacked, forming a first stack structure and a second bonding layer on the semiconductor-on-insulator substrate; the first stack structure is obtained by alternately stacking a plurality of first semiconductor layers and a plurality of second semiconductor layers; bonding the first substrate and the semiconductor-on-insulator substrate in a direction of the second bonding layer towards the first bonding layer; forming a second stack structure on the bottom semiconductor substrate, the second stack structure being obtained by alternately stacking a plurality of first semiconductor layers and a plurality of second semiconductor layers; processing the first stack structure and the second stack structure to form a field effect transistor; the processing of the first stack structure and the second stack structure to form a field effect transistor comprises: processing the first stack structure and the second stack structure to form a nanowire stack structure, the nanowire stack structure comprising a bottom structure below the buried oxide layer and a top structure above the buried oxide layer; forming a bottom source and a bottom drain on both sides of the bottom structure; forming a top source and a top drain on both sides of the top structure; removing the second semiconductor layer to form a plurality of to-be-filled gaps, filling a gate in a plurality of the to-be-filled gaps, a plurality of the first semiconductor layers surrounded by the gate forming a channel structure, the channel structure comprising a top channel structure and a bottom channel structure, the top channel structure and the bottom channel structure being separated by the buried oxide layer.

2. The production method according to claim 1, characterized by Before forming a bottom source and a bottom drain on both sides of the bottom structure, the method further comprises: lateral etching the second semiconductor layer located in the top structure and the bottom structure to form a concave structure; forming an inner sidewall in the concave structure.

3. The production method according to claim 2, characterized by The forming of the inner sidewall in the concave structure comprises: forming an inner sidewall along the upper and lower surfaces on both sides of the buried oxide layer in a direction perpendicular to the surfaces of the first bonding layer and the second bonding layer, the inner sidewall and the buried oxide layer forming an intermediate dielectric layer.

4. The production method according to claim 1, characterized by After forming a bottom source and a bottom drain on both sides of the bottom structure and before forming a top source and a top drain on both sides of the top structure, the method further comprises: forming a first dielectric layer between the bottom source and the bottom drain on both sides of the bottom structure and the top source and the top drain on both sides of the top structure.

5. The production method according to claim 1, characterized by Before filling a gate in a plurality of the to-be-filled gaps, the method further comprises: forming a second work function layer in the plurality of to-be-filled gaps of the bottom structure; forming a first work function layer in the plurality of to-be-filled gaps of the top structure.

6. The production method according to any one of claims 1 to 5, characterized by, Before forming a second stack structure on the bottom semiconductor substrate, the method further comprises: thinning the bottom semiconductor substrate to a thickness of the thickness of the first semiconductor layer or the second semiconductor layer.

7. A field effect transistor, characterized by The field effect transistor is manufactured according to the manufacturing method of the field effect transistor according to any one of claims 1 to 6, and the field effect transistor comprises: a bottom dielectric isolation layer comprising a first bonding layer and a second bonding layer; a top source, a top drain, a top channel structure, a bottom source, a bottom drain and a bottom channel structure disposed on the bottom dielectric isolation layer, the top channel structure and the bottom channel structure overlap in a direction perpendicular to a plane on which the bottom dielectric isolation layer lies, and the top channel structure and the bottom channel structure are isolated by an intermediate dielectric layer; the top channel structure is between the top source and the top drain, the bottom channel structure is between the bottom source and the bottom drain, and the top channel structure and the bottom channel structure comprise a plurality of nanosheet formed stacks; a gate surrounding the nanosheet.

8. The field effect transistor of claim 7, wherein, The first substrate is a silicon substrate, a germanium substrate or a germanium-silicon substrate, and the semiconductor-on-insulator substrate is a silicon-on-insulator substrate, a germanium-on-insulator substrate or a germanium-silicon-on-insulator substrate.

9. The field effect transistor according to any one of claims 7-8, characterized in that, The intermediate dielectric layer comprises a first portion in the center and a second portion on both sides of the first portion, wherein the second portion extends along the surfaces of the first portion on both sides in a direction perpendicular to the surface of the bottom dielectric isolation layer, and the thickness of the second portion is greater than the thickness of the first portion.

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