Ferroelectric semi-floating gate transistor with multilevel storage and logic functions and preparation method thereof

Abstract

The invention relates to a ferroelectric semi-floating gate transistor with multi-level storage and logic functions and a preparation method of the ferroelectric semi-floating gate transistor. The first graphene layer and the second graphene layer are arranged on the SiO2 / Si substrate at intervals; the alpha-In2Se3 thin layer is arranged on the first graphene layer; the h-BN thin layer is arranged on the alpha-In2Se3 thin layer and the second graphene layer; the WSe2 thin layer is arranged on the h-BN thin layer; the source electrode and the drain electrode are arranged at the two ends of the WSe2 thin layer respectively, and the grid electrode is arranged on the surface of the second graphene layer; the transistor is prepared through a mechanical stripping process, shows excellent storage and photoelectric characteristics, and has high programming / erasing ratio, good durability and retentivity of more than 104 seconds. Through double-gate modulation, a multi-level storage function with at least seven controllable programming states is realized, and three digital logic gate operations can be executed under ultra-low bias voltage of 10mV.

Description

Technical Field

[0001] The present invention relates to the field of transistors, and in particular, to a ferroelectric semi-floating gate transistor with multi-level storage and logic functions and a method for manufacturing the same. Background Art

[0002] The rapid development of artificial intelligence (AI) technology has led to a surge in the scale and complexity of models, and the demand for efficient data storage and processing capabilities has also been increasing day by day. Due to the separation of storage and computing units, the traditional von Neumann architecture faces energy consumption and latency problems, which limits the processing speed and energy efficiency. To address this challenge, multifunctional devices have been developed to integrate data storage, sensing, and computing into one device. This is particularly suitable for applications such as deep learning that require a large amount of parallel processing, where matrix operations can be directly performed within one device, reducing external memory access and power consumption and improving the processing speed.

[0003] In recent years, two-dimensional (2D) ferroelectric materials such as α-In 2 Se 3 have been increasingly applied to ferroelectric floating gate transistors or ferroelectric field effect transistors due to their unique ferroelectric polarization characteristics. Ferroelectric polarization enables the device to retain the stored charge for a long time without being affected by the outside even after power-off, thereby realizing long-term data storage and reducing the power consumption and latency problems caused by frequent data transmission in the traditional von Neumann architecture. However, it is still difficult to combine multiple functions such as non-volatile memory and digital logic operations in a single device, which is crucial for the development of high-integration and low-power integrated circuit applications. Therefore, exploring the integration of storage and computing functions on a single transistor is a key step in promoting the development of integrated circuits and artificial intelligence. Summary of the Invention

[0004] Aiming at the technical problems existing in the prior art, the primary object of the present invention is to provide a ferroelectric semi-floating gate transistor with multi-level storage and logic functions, which can simultaneously realize multi-level memory and logic operations.

[0005] On the one hand, the present invention provides a ferroelectric semi-floating gate transistor with multi-level storage and logic functions, including a SiO 2 / Si substrate; a first graphene layer and a second graphene layer disposed on the SiO 2 layer, with a gap between the first graphene layer and the second graphene layer; an α-In 2 Se 3 thin layer disposed on the first graphene layer without contacting the second graphene layer; an h-BN thin layer disposed on the α-In 2 Se 3 thin layer and the second graphene layer; a WSe 2 thin layer disposed on the h-BN thin layer, and a WSe 2The boundary of the thin layer does not exceed the boundary range of the h-BN thin layer;

[0006] The source electrode and the drain electrode are respectively arranged at both ends on the WSe 2 thin layer, and the gate electrode is arranged on the surface of the second graphene layer.

[0007] On the one hand, the present invention provides a preparation method of a ferroelectric semi-floating gate transistor with multi-level storage and logic functions, including the following steps:

[0008] Adopt a mechanical exfoliation process to arrange a first graphene layer and a second graphene layer at intervals on the SiO 2 / Si substrate;

[0009] Adopt a mechanical exfoliation process to arrange an α-In 2 Se 3 thin layer on the first graphene layer, and the α-In 2 Se 3 thin layer does not contact the second graphene layer;

[0010] Adopt a mechanical exfoliation process to arrange an h-BN thin layer on the α-In 2 Se 3 thin layer and the second graphene layer;

[0011] Adopt a mechanical exfoliation process to arrange a WSe 2 thin layer on the h-BN thin layer, and the boundary of the WSe 2 thin layer does not exceed the boundary range of the h-BN thin layer;

[0012] On both ends of the WSe 2 thin layer, arrange source electrode metal and drain electrode metal, and arrange gate electrode metal on the surface of the second graphene layer

[0013] Anneal in an inert gas.

[0014] Further, on the projection plane of the ferroelectric semi-floating gate transistor, the WSe 2 thin layer and the α-In 2 Se 3 thin layer and the second graphene layer at least partially overlap.

[0015] Further, the h-BN thin layer completely covers the α-In 2 Se 3 thin layer and exposes part of the second graphene layer.

[0016] Further, the Si substrate is a bottom gate.

[0017] Further, the first graphene layer is a charge storage layer, and the second graphene layer is a control gate.

[0018] Furthermore, the thickness of the first graphene layer is 2 nm to 30 nm; the thickness of the second graphene layer is 2 nm to 30 nm.

[0019] Furthermore, the thickness of the α-In 2 Se 3 thin layer is 35 nm to 55 nm;

[0020] the thickness of the h-BN thin layer is 2 nm to 5 nm;

[0021] the thickness of the WSe 2 thin layer is 20 nm to 35 nm.

[0022] Furthermore, the annealing time is 20 to 40 min, and the annealing temperature is 100 to 150 °C.

[0023] Furthermore, the source and drain are Au electrodes, and the thickness of the Au electrodes is 45 to 55 nm;

[0024] the gate is an Au electrode, and the thickness of the Au electrode is 45 to 55 nm.

[0025] Furthermore, by applying different programming voltage pulses on the bottom gate and the gate, a multi-level storage function with at least 7 programming states is achieved;

[0026] Taking the bottom gate, the gate, and the optical signal as three logic input terminals, and the channel current as the logic output terminal, this ferroelectric floating-gate transistor is an optoelectronic logic gate.

[0027] Compared with the prior art, the present invention has at least the following beneficial effects:

[0028] By selecting WSe 2 with advantages such as a layered two-dimensional structure thin film, high mobility, good optical response, and easy peeling, and the ferroelectric material α-In 2 Se 3 with spontaneous polarization phenomenon, a tungsten diselenide / boron nitride / indium selenide / graphene ferroelectric semi-floating-gate transistor is constructed. This ferroelectric semi-floating-gate transistor consists of two parts. One part realizes the non-volatile memory function based on the WSe 2 / h-BN / α-In 2 Se 3 / Graphene heterostructure, and the other part realizes the conductance modulation function based on the WSe 2 / h-BN / Graphene heterostructure; with the help of the ferroelectric polarization field, the device realizes the improvement of non-volatile memory performance. Compared with the device without α-In 2 Se 3Compared with the devices of the layer, it has a higher programming / erasing ratio, more significant differences in programming and erasing states, and a longer retention time. By applying voltage pulses simultaneously on the bottom silicon and graphene gate, multi-level storage function can be achieved, and "AND", "NOR", and "OR" logic gate operations can be performed under a low bias voltage of 10 mV. This ferroelectric semi-floating gate structure makes this transistor an ideal choice for integration into artificial intelligence devices when dealing with complex logic operations. Brief Description of the Drawings

[0029] Figure 1 It is a schematic diagram of the device structure of the ferroelectric semi-floating gate transistor according to an embodiment of the present invention.

[0030] Figure 2 It is an optical microscope image of the ferroelectric semi-floating gate transistor obtained by preparing according to an embodiment of the present invention.

[0031] Figure 3 It is the data curve of the ferroelectric semi-floating gate transistor obtained by preparing according to an embodiment of the present invention, where (a) is the storage performance endurance test of this transistor; (b) is the storage performance persistence test of this transistor; (c) is the multi-level storage performance demonstration of the transistor.

[0032] Figure 4 It is the logic gate function demonstration of the ferroelectric semi-floating gate transistor obtained by preparing according to an embodiment of the present invention, where (a) is the AND gate function demonstration; (b) is the NOR gate function demonstration; (c) is the OR gate function demonstration. Detailed Embodiments

[0033] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings of the present invention. The described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present invention. The experimental methods described in the following embodiments are all conventional methods unless otherwise specified; the reagents and materials described are all available from public commercial channels unless otherwise specified.

[0034] Spatial relative terms such as "beneath", "below", "under", "above", "over", "on" etc. are used in this specification to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device except for those different from the orientations shown in the figures.

[0035] In addition, the use of terms such as "first" and "second" to describe various elements, layers, regions, sections, etc. is not intended to be restrictive. The terms "having", "containing", "including", "comprising", etc. are open-ended terms indicating the presence of the stated element or feature, but do not exclude additional elements or features, unless the context clearly dictates otherwise.

[0036] As Figure 1 shown, an embodiment of the present invention provides a ferroelectric semi-floating gate transistor having multi-level storage and logic functions, which includes a SiO 2 / Si substrate, a WSe 2 thin layer, a thin layer of h-BN, an α-In 2 Se 3 thin layer, a thin layer of graphene, and electrodes.

[0037] The thin layer of graphene has a first graphene layer and a second graphene layer with the same or different thicknesses. The first graphene layer and the second graphene layer are spaced apart and disposed on the SiO 2 layer on the Si substrate. The thicknesses of the first graphene layer and the second graphene layer are 2 to 30 nm. The α-In 2 Se 3 thin layer is disposed on the first graphene layer. The thickness of the α-In 2 Se 3 thin layer is 35 to 55 nm; the h-BN thin layer is disposed on the α-In 2 Se 3 thin layer and the second graphene layer. The h-BN thin layer completely covers the α-In 2 Se 3 thin layer and exposes a part of the second graphene layer. The thickness of the h-BN thin layer is 2 to 5 nm.

[0038] The WSe 2 thin layer is disposed on the h-BN thin layer. The boundary of the WSe 2 thin layer does not exceed the boundary range of the h-BN thin layer. The thickness of the WSe 2 thin layer is 20 nm to 35 nm; on the projection plane of the ferroelectric semi-floating gate transistor, the WSe 2 thin layer at least partially overlaps with the α-In 2 Se 3 thin layer and the second graphene layer.

[0039] The two ends of the WSe 2 thin layer are respectively provided with a source electrode and a drain electrode. The gate electrode is disposed on the surface of the second graphene layer. The source electrode and the drain electrode are made of an Au layer with a thickness of 45 to 65 nm; the gate electrode is made of an Au layer with a thickness of 45 to 65 nm.

[0040] As Figure 1As shown, the ferroelectric half-floating gate transistor consists of two parts: one part is based on the WSe 2 / h-BN / α-In 2 Se 3 / Graphene heterostructure, stacked from top to bottom, serving as the channel, insulator, half-floating gate, and charge storage layer respectively; the other part is based on the WSe 2 / h-BN / Graphene heterostructure, serving as the channel, insulator, and control gate respectively. These two parts respectively achieve the functions of non-volatile memory and conductance modulation.

[0041] An embodiment of the present invention provides a preparation method for this transistor, including the following steps.

[0042] First, soak the SiO 2 / Si growth substrate in acetone solution, isopropyl alcohol solution, and deionized water respectively, and the soaking time for each time is 5 minutes.

[0043] Then, adopt the mechanical exfoliation process. Use blue tape to stick to the single crystal to obtain a single crystal tape, use PDMS to stick to the single crystal tape to obtain Graphene / PDMS. Select a 2 - 5nm thin layer of Graphene under an optical microscope, and cover the PDMS with the Graphene side on the surface of the SiO 2 / Si substrate, and a first graphene layer is formed on the surface of the SiO 2 / Si substrate; subsequently, according to this exfoliation method, transfer another thin layer of graphene to the surface of this SiO 2 / Si substrate, and it does not contact the previous graphene layer, and a second graphene layer is formed on the surface of the SiO 2 / Si substrate.

[0044] Continue to transfer the thin layer of α-In 2 Se 3 to the first graphene layer by using the same mechanical exfoliation process without contacting the second graphene layer.

[0045] Then, the steps of obtaining thin layers of h-BN and WSe 2 by mechanical exfoliation of single crystals include using PDMS to stick to the single crystal tape to obtain h-BN / PDMS, and completely covering the surface of α-In 2 Se 3 with the PDMS with the h-BN side, which is used to improve the device stability and reduce interface defects, and cover a part of the second graphene layer (i.e., the thin layer graphene without the α-In 2 Se 3 thin layer on the upper layer), exposing a part sufficient for photolithography electrodes.

[0046] Subsequently, the thin layer of WSe 2When transferred to a thin layer of h-BN, at least WSe 2 Thin layer and α-In 2 Se 3 The thin layer and the second graphene part overlap and cannot exceed the boundary of the h-BN thin layer.

[0047] Next, a positive photoresist was selected, and the photoresist was set to 4000 rpm mode for 60 seconds of spin coating. It was then baked on a heating table at 100°C for 5 to 10 minutes, and the source and drain electrode patterns and gate patterns were patterned using ultraviolet laser etching.

[0048] Next, an electron beam evaporation process was used to evaporate a 45-65 nm Au layer at a rate of 0.01 nm / s. After the evaporation, the Au layer was placed in acetone for ten minutes to dissolve the photoresist and remove the excess Au layer. 2 A source electrode and a drain electrode are formed at two ends of the channel surface, and a gate electrode is formed on the surface of the second graphene layer.

[0049] Finally, the device was placed in a glove box and annealed in argon at 150 °C for 30 minutes to increase the contact between different materials and improve the stability of the device, thereby obtaining the final WSe 2 / h-BN / α-In 2 Se 3 / Graphene ferroelectric semi-floating gate transistor devices.

[0050] Figure 2 The WSe prepared by one embodiment of the present invention is shown. 2 / h-BN / α-In 2 Se 3 / Graphene ferroelectric semi-floating gate transistor optical microscope image. The source electrode and drain electrode are respectively set on a thin layer of WSe 2 At both ends, the gate electrode is set on one end of the thin layer of graphene, and the bottom gate is the substrate Si. The scale is 10μm.

[0051] Figure 3 In the figure, (a) shows that the device durability was further tested by repeatedly switching the device between the programming and erasing states. After 1000 cycles, the current levels in both states are still very stable, which means that the memory device has excellent endurance; (b) after 10000 seconds, the device programming / erasing state current ratio is still more than 10 4 , showing that the device has excellent durability; (c) Figure shows -60V negative V SiPulses are used for the erasure operation, and the resulting low current level is designated as the "0" state. Positive V with different amplitudes (10, 20, 30, 40, 50, and 60 V) Si Pulses are used for the programming operation, generating different current levels, which can be respectively designated as "1", "2", "3", "4", "5", and "6" states, demonstrating effective multi-level storage capabilities.

[0052] Figure 4 As shown, where the bottom silicon gate (A), graphene gate (B), and 635 nm optical signal (C) are three logic input terminals, and the channel current is regarded as the logic output terminal (S). In short, by applying different gate voltage configurations to V within the HRS (high resistance state) or LRS (low resistance state) Si and V Gr respectively, AND or NOR logic operations can be achieved; in addition, the OR logic function is achieved by utilizing the optical input and varying V Gr voltage.

[0053] The above-provided WSe 2 / h-BN / α-In 2 Se 3 / Graphene ferroelectric semi-floating gate transistor can achieve multi-level storage and optoelectronic logic gates, showing excellent storage and optoelectronic characteristics. Thanks to the ferroelectric polarization of α-In 2 Se 3 , the non-volatile storage capacity of this device is improved, with a high programming / erasure (P / E) ratio of 10 6 and good durability of more than 1000 times. A retention time of more than 10 4 seconds. Through dual-gate modulation by applying different programming voltage pulses on silicon and graphene, this device can achieve a multi-level storage function with at least 7 programming states. By taking the dual gate and optical signal as inputs, this device can also act as an optoelectronic logic gate, realizing "AND", "NOR", and "OR" digital logic processing at an extremely small bias voltage of 10 mV, with the advantages of low power consumption and multi-functionality. Compared with the traditional floating gate transistor architecture, the ferroelectric semi-floating gate layer provides a promising solution for integrating high-performance multi-level non-volatile memories and various digital logic operations.

[0054] The above embodiments are the preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement methods and are all included in the protection scope of the present invention.

Claims

1. A ferroelectric semi-floating gate transistor with multi-level storage and logic functions, characterized in that: The invention comprises a SiO2 / Si substrate; a first graphene layer and a second graphene layer arranged on the SiO2 layer, wherein a gap exists between the first graphene layer and the second graphene layer; an α-In2Se3 thin layer is arranged on the first graphene layer and does not contact the second graphene layer; an h-BN thin layer is arranged on the α-In2Se3 thin layer and the second graphene layer; a WSe2 thin layer is arranged on the h-BN thin layer, and the boundary of the WSe2 thin layer does not exceed the boundary range of the h-BN thin layer; The source electrode and the drain electrode are respectively arranged at two ends of the WSe2 thin layer, and the gate electrode is arranged on the surface of the second graphene layer.

2. A method for preparing a ferroelectric semi-floating gate transistor with multi-level storage and logic functions, characterized in that: The following steps are involved: A first graphene layer and a second graphene layer are arranged on a SiO2 / Si substrate by using a mechanical peeling process; A thin layer of α-In2Se3 is disposed on the first graphene layer by a mechanical exfoliation process, and the thin layer of α-In2Se3 does not contact the second graphene layer; A h-BN thin layer is disposed on the α-In2Se3 thin layer and the second graphene layer using a mechanical exfoliation process; A WSe2 thin layer is disposed on the h-BN thin layer by a mechanical exfoliation process, and the boundary of the WSe2 thin layer does not exceed the boundary range of the h-BN thin layer; The source metal and drain metal are set at both ends of the WSe2 thin layer, and the gate metal is set on the surface of the second graphene layer. Annealing in inert gas.

3. The ferroelectric floating-gate transistor according to claim 1, or the preparation method according to claim 2, characterized in that: On the projection plane of the ferroelectric semi-floating gate transistor, the WSe2 thin layer at least partially overlaps with the α-In2Se3 thin layer and the second graphene layer.

4. The ferroelectric floating-gate transistor or the preparation method according to claim 3, characterized in that: The h-BN thin layer completely covers the α-In2Se3 thin layer and partially exposes the second graphene layer.

5. The ferroelectric floating-gate transistor or the preparation method according to claim 3, characterized in that: The Si substrate is a bottom gate.

6. The ferroelectric floating-gate transistor or the method for preparing the same according to claim 5, characterized in that: The first graphene layer is a charge storage layer, and the second graphene layer is a control gate; the thickness of the first graphene layer is 2nm to 30nm; the thickness of the second graphene layer is 2nm to 30nm.

7. The ferroelectric semi-floating gate transistor or the preparation method according to claim 6, characterized in that: The thickness of the α-In2Se3 thin layer is 35nm to 55nm; The thickness of the h-BN thin layer is 2nm to 5nm; The thickness of the WSe2 thin layer is 20nm to 35nm.

8. The ferroelectric floating-gate transistor or the method for preparing the same according to claim 2, characterized in that: The annealing time is 20 to 40 minutes, and the annealing temperature is 100 to 150°C.

9. The ferroelectric floating-gate transistor or the method for preparing the same according to claim 7, characterized in that: The source and drain are Au electrodes, and the thickness of the Au electrodes is 45-55 nm; The gate is an Au electrode, and the thickness of the Au electrode is 45-55 nm.

10. The ferroelectric floating-gate transistor or the method for preparing the same according to claim 6, characterized in that: By applying different programming voltage pulses on the bottom gate and the gate, a multi-level storage function with at least 7 programming states is realized; The bottom gate, the gate and the optical signal are used as three logic input terminals, the channel current is used as a logic output terminal, and the ferroelectric floating gate transistor is a photoelectric logic gate.

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